2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.112541 # Number of seconds simulated
4 sim_ticks 112540655000 # Number of ticks simulated
5 final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 123771 # Simulator instruction rate (inst/s)
8 host_op_rate 148600 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 51015836 # Simulator tick rate (ticks/s)
10 host_mem_usage 322668 # Number of bytes of host memory used
11 host_seconds 2205.99 # Real time elapsed on the host
12 sim_insts 273037219 # Number of instructions simulated
13 sim_ops 327811601 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 623680 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.readReqs 9745 # Number of read requests accepted
37 system.physmem.writeReqs 0 # Number of write requests accepted
38 system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue
39 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
40 system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM
41 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
42 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
43 system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side
44 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
45 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
46 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
47 system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
48 system.physmem.perBankRdBursts::0 803 # Per bank write bursts
49 system.physmem.perBankRdBursts::1 999 # Per bank write bursts
50 system.physmem.perBankRdBursts::2 769 # Per bank write bursts
51 system.physmem.perBankRdBursts::3 645 # Per bank write bursts
52 system.physmem.perBankRdBursts::4 618 # Per bank write bursts
53 system.physmem.perBankRdBursts::5 484 # Per bank write bursts
54 system.physmem.perBankRdBursts::6 251 # Per bank write bursts
55 system.physmem.perBankRdBursts::7 363 # Per bank write bursts
56 system.physmem.perBankRdBursts::8 300 # Per bank write bursts
57 system.physmem.perBankRdBursts::9 432 # Per bank write bursts
58 system.physmem.perBankRdBursts::10 486 # Per bank write bursts
59 system.physmem.perBankRdBursts::11 534 # Per bank write bursts
60 system.physmem.perBankRdBursts::12 696 # Per bank write bursts
61 system.physmem.perBankRdBursts::13 850 # Per bank write bursts
62 system.physmem.perBankRdBursts::14 782 # Per bank write bursts
63 system.physmem.perBankRdBursts::15 733 # Per bank write bursts
64 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
76 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
77 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
78 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
79 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
80 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
81 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
82 system.physmem.totGap 112540488500 # Total gap between requests
83 system.physmem.readPktSize::0 0 # Read request sizes (log2)
84 system.physmem.readPktSize::1 0 # Read request sizes (log2)
85 system.physmem.readPktSize::2 0 # Read request sizes (log2)
86 system.physmem.readPktSize::3 0 # Read request sizes (log2)
87 system.physmem.readPktSize::4 0 # Read request sizes (log2)
88 system.physmem.readPktSize::5 0 # Read request sizes (log2)
89 system.physmem.readPktSize::6 9745 # Read request sizes (log2)
90 system.physmem.writePktSize::0 0 # Write request sizes (log2)
91 system.physmem.writePktSize::1 0 # Write request sizes (log2)
92 system.physmem.writePktSize::2 0 # Write request sizes (log2)
93 system.physmem.writePktSize::3 0 # Write request sizes (log2)
94 system.physmem.writePktSize::4 0 # Write request sizes (log2)
95 system.physmem.writePktSize::5 0 # Write request sizes (log2)
96 system.physmem.writePktSize::6 0 # Write request sizes (log2)
97 system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
129 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
193 system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation
207 system.physmem.totQLat 248191131 # Total ticks spent queuing
208 system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM
209 system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers
210 system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst
211 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
212 system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst
213 system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s
214 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
215 system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s
216 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
217 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
218 system.physmem.busUtil 0.04 # Data bus utilization in percentage
219 system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
220 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
221 system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
222 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
223 system.physmem.readRowHits 8500 # Number of row buffer hits during reads
224 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
225 system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads
226 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
227 system.physmem.avgGap 11548536.53 # Average gap between requests
228 system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined
229 system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states
230 system.physmem.memoryStateTime::REF 3757780000 # Time in different power states
231 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
232 system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states
233 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
234 system.membus.trans_dist::ReadReq 9170 # Transaction distribution
235 system.membus.trans_dist::ReadResp 9170 # Transaction distribution
236 system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
237 system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
238 system.membus.trans_dist::ReadExReq 575 # Transaction distribution
239 system.membus.trans_dist::ReadExResp 575 # Transaction distribution
240 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes)
241 system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes)
242 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes)
243 system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes)
244 system.membus.snoops 0 # Total snoops (count)
245 system.membus.snoop_fanout::samples 9746 # Request fanout histogram
246 system.membus.snoop_fanout::mean 0 # Request fanout histogram
247 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
248 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
249 system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram
250 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
251 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
252 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
253 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
254 system.membus.snoop_fanout::total 9746 # Request fanout histogram
255 system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks)
256 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
257 system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks)
258 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
259 system.cpu_clk_domain.clock 500 # Clock period in ticks
260 system.cpu.branchPred.lookups 37763717 # Number of BP lookups
261 system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted
262 system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect
263 system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups
264 system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits
265 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
266 system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage
267 system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target.
268 system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
269 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
270 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
271 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
272 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
273 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
274 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
275 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
276 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
277 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
278 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
279 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
280 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
281 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
282 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
283 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
284 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
285 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
286 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
287 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
288 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
289 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
290 system.cpu.dtb.inst_hits 0 # ITB inst hits
291 system.cpu.dtb.inst_misses 0 # ITB inst misses
292 system.cpu.dtb.read_hits 0 # DTB read hits
293 system.cpu.dtb.read_misses 0 # DTB read misses
294 system.cpu.dtb.write_hits 0 # DTB write hits
295 system.cpu.dtb.write_misses 0 # DTB write misses
296 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
297 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
298 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
299 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
300 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
301 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
302 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
303 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
304 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
305 system.cpu.dtb.read_accesses 0 # DTB read accesses
306 system.cpu.dtb.write_accesses 0 # DTB write accesses
307 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
308 system.cpu.dtb.hits 0 # DTB hits
309 system.cpu.dtb.misses 0 # DTB misses
310 system.cpu.dtb.accesses 0 # DTB accesses
311 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
312 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
313 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
314 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
315 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
316 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
317 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
318 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
319 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
320 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
321 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
322 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
323 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
324 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
325 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
326 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
327 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
328 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
329 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
330 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
331 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
332 system.cpu.itb.inst_hits 0 # ITB inst hits
333 system.cpu.itb.inst_misses 0 # ITB inst misses
334 system.cpu.itb.read_hits 0 # DTB read hits
335 system.cpu.itb.read_misses 0 # DTB read misses
336 system.cpu.itb.write_hits 0 # DTB write hits
337 system.cpu.itb.write_misses 0 # DTB write misses
338 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
339 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
340 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
341 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
342 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
343 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
344 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
345 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
346 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
347 system.cpu.itb.read_accesses 0 # DTB read accesses
348 system.cpu.itb.write_accesses 0 # DTB write accesses
349 system.cpu.itb.inst_accesses 0 # ITB inst accesses
350 system.cpu.itb.hits 0 # DTB hits
351 system.cpu.itb.misses 0 # DTB misses
352 system.cpu.itb.accesses 0 # DTB accesses
353 system.cpu.workload.num_syscalls 191 # Number of system calls
354 system.cpu.numCycles 225081311 # number of cpu cycles simulated
355 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
356 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
357 system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss
358 system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed
359 system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered
360 system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken
361 system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked
362 system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing
363 system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
364 system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
365 system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR
366 system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched
367 system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed
368 system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
379 system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total)
380 system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle
381 system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle
382 system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle
383 system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked
384 system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running
385 system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking
386 system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing
387 system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch
388 system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction
389 system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode
390 system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode
391 system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing
392 system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle
393 system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking
394 system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst
395 system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running
396 system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking
397 system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename
398 system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename
399 system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full
400 system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full
401 system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full
402 system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full
403 system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers
404 system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed
405 system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made
406 system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups
407 system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups
408 system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
409 system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing
410 system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed
411 system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed
412 system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer
413 system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit.
414 system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit.
415 system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads.
416 system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores.
417 system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec)
418 system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ
419 system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued
420 system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued
421 system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling
422 system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph
423 system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed
424 system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle
434 system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
436 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
437 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
438 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
439 system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
440 system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle
441 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
442 system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available
443 system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available
444 system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
445 system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
446 system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
447 system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
448 system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
449 system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
450 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available
466 system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available
467 system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available
468 system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available
469 system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available
470 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available
471 system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available
472 system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available
473 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
474 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
475 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
476 system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued
477 system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued
478 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued
479 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued
480 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued
481 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued
482 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued
483 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued
484 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued
500 system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued
501 system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued
502 system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued
503 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued
504 system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued
505 system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued
506 system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued
507 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
508 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
509 system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued
510 system.cpu.iq.rate 1.538412 # Inst issue rate
511 system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested
512 system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst)
513 system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads
514 system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes
515 system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses
516 system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads
517 system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes
518 system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses
519 system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses
520 system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses
521 system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores
522 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
523 system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed
524 system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed
525 system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations
526 system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed
527 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
528 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
529 system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled
530 system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked
531 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
532 system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing
533 system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking
534 system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking
535 system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ
536 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
537 system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions
538 system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions
539 system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions
540 system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall
541 system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall
542 system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations
543 system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly
544 system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly
545 system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute
546 system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions
547 system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed
548 system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute
549 system.cpu.iew.exec_swp 0 # number of swp insts executed
550 system.cpu.iew.exec_nop 864 # number of nop insts executed
551 system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed
552 system.cpu.iew.exec_branches 31752179 # Number of branches executed
553 system.cpu.iew.exec_stores 84582729 # Number of stores executed
554 system.cpu.iew.exec_rate 1.520806 # Inst execution rate
555 system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit
556 system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back
557 system.cpu.iew.wb_producers 153543382 # num instructions producing a value
558 system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value
559 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
560 system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle
561 system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back
562 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
563 system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit
564 system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
565 system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted
566 system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle
576 system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle
578 system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle
579 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
580 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
581 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
582 system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle
583 system.cpu.commit.committedInsts 273037831 # Number of instructions committed
584 system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed
585 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
586 system.cpu.commit.refs 168107892 # Number of memory references committed
587 system.cpu.commit.loads 85732275 # Number of loads committed
588 system.cpu.commit.membars 11033 # Number of memory barriers committed
589 system.cpu.commit.branches 30563525 # Number of branches committed
590 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
591 system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
592 system.cpu.commit.function_calls 6225114 # Number of function calls committed.
593 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
594 system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction
595 system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
596 system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
597 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
598 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
599 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
600 system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
601 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
602 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
615 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
616 system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
617 system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
618 system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
619 system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
620 system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
621 system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
622 system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
623 system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
624 system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
625 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
626 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
627 system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
628 system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached
629 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
630 system.cpu.rob.rob_reads 561656707 # The number of ROB reads
631 system.cpu.rob.rob_writes 705358338 # The number of ROB writes
632 system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself
633 system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling
634 system.cpu.committedInsts 273037219 # Number of Instructions Simulated
635 system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated
636 system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction
637 system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads
638 system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle
639 system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads
640 system.cpu.int_regfile_reads 331187238 # number of integer regfile reads
641 system.cpu.int_regfile_writes 136909181 # number of integer regfile writes
642 system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads
643 system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes
644 system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads
645 system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes
646 system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads
647 system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
648 system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution
649 system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution
650 system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution
651 system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution
652 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
653 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
654 system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution
655 system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution
656 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes)
657 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes)
658 system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes)
659 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes)
660 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes)
661 system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes)
662 system.cpu.toL2Bus.snoops 50213 # Total snoops (count)
663 system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram
664 system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram
665 system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram
666 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
667 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
668 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
669 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
670 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
671 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
672 system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram
673 system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram
674 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
675 system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
676 system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
677 system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram
678 system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks)
679 system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
680 system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks)
681 system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
682 system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks)
683 system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
684 system.cpu.icache.tags.replacements 715368 # number of replacements
685 system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use
686 system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks.
687 system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks.
688 system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks.
689 system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit.
690 system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor
691 system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy
692 system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy
693 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
694 system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
695 system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
696 system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
697 system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
698 system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id
699 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
700 system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses
701 system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses
702 system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits
703 system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits
704 system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits
705 system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits
706 system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits
707 system.cpu.icache.overall_hits::total 88391816 # number of overall hits
708 system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses
709 system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses
710 system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses
711 system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses
712 system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses
713 system.cpu.icache.overall_misses::total 719790 # number of overall misses
714 system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles
715 system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles
716 system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles
717 system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles
718 system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles
719 system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles
720 system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses)
721 system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses)
722 system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses
723 system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses
724 system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses
725 system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses
726 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses
727 system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
728 system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses
729 system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses
730 system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses
731 system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses
732 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency
733 system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency
734 system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
735 system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency
736 system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
737 system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency
738 system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked
739 system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked
740 system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked
741 system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
742 system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked
743 system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked
744 system.cpu.icache.fast_writes 0 # number of fast writes performed
745 system.cpu.icache.cache_copies 0 # number of cache copies performed
746 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits
747 system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits
748 system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits
749 system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits
750 system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits
751 system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits
752 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses
753 system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses
754 system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses
755 system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses
756 system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses
757 system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses
758 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles
759 system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles
760 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles
761 system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles
762 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles
763 system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles
764 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses
765 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses
766 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses
767 system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses
768 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses
769 system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses
770 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency
771 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency
772 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
773 system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
774 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
775 system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
776 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
777 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified
778 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr
779 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache
780 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue
781 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
782 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated
783 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued
784 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page
785 system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
786 system.cpu.l2cache.tags.replacements 0 # number of replacements
787 system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use
788 system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks.
789 system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks.
790 system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks.
791 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
792 system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor
793 system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor
794 system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor
795 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor
796 system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy
797 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy
798 system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy
799 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy
800 system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy
801 system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id
802 system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id
803 system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id
804 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id
805 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id
806 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id
807 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
808 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
809 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id
810 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id
811 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id
812 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id
813 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id
814 system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses
815 system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses
816 system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits
817 system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits
818 system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits
819 system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits
820 system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits
821 system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
822 system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
823 system.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits
824 system.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits
825 system.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits
826 system.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits
827 system.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits
828 system.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits
829 system.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits
830 system.cpu.l2cache.overall_hits::total 2247270 # number of overall hits
831 system.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses
832 system.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses
833 system.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses
834 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
835 system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
836 system.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses
837 system.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses
838 system.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses
839 system.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses
840 system.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses
841 system.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses
842 system.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses
843 system.cpu.l2cache.overall_misses::total 1965 # number of overall misses
844 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles
845 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles
846 system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles
847 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles
848 system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles
849 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles
850 system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles
851 system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles
852 system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles
853 system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles
854 system.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles
855 system.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles
856 system.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles
857 system.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses)
858 system.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses)
859 system.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses)
860 system.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses)
861 system.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses)
862 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
863 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
864 system.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses)
865 system.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses)
866 system.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses
867 system.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses
868 system.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses
869 system.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses
870 system.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses
871 system.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses
872 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses
873 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses
874 system.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses
875 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
876 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
877 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses
878 system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses
879 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses
880 system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses
881 system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses
882 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses
883 system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses
884 system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses
885 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency
886 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency
887 system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency
888 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency
889 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency
890 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency
891 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency
892 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency
893 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency
894 system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency
895 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency
896 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency
897 system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency
898 system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked
899 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
900 system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked
901 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
902 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked
903 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
904 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
905 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
906 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
907 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits
908 system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits
909 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits
910 system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits
911 system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
912 system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits
913 system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits
914 system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
915 system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits
916 system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits
917 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses
918 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses
919 system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses
920 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses
921 system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses
922 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
923 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
924 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses
925 system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses
926 system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses
927 system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses
928 system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses
929 system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses
930 system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses
931 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses
932 system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses
933 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles
934 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles
935 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles
936 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles
937 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles
938 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles
939 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles
940 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles
941 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles
942 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles
943 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles
944 system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles
945 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles
946 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles
947 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles
948 system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles
949 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses
950 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses
951 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
952 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
953 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
954 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
955 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
956 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses
957 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses
958 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses
959 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses
960 system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses
961 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses
962 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses
963 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
964 system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses
965 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency
966 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency
967 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency
968 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency
969 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency
970 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
971 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
972 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency
973 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency
974 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
975 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
976 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency
977 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
978 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
979 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency
980 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency
981 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
982 system.cpu.dcache.tags.replacements 1533746 # number of replacements
983 system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use
984 system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks.
985 system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks.
986 system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks.
987 system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit.
988 system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor
989 system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
990 system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
991 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
992 system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
993 system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
994 system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
995 system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
996 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
997 system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses
998 system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses
999 system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits
1000 system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits
1001 system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits
1002 system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits
1003 system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits
1004 system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits
1005 system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
1006 system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
1007 system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
1008 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
1009 system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits
1010 system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits
1011 system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits
1012 system.cpu.dcache.overall_hits::total 163781573 # number of overall hits
1013 system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses
1014 system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses
1015 system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses
1016 system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses
1017 system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses
1018 system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses
1019 system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
1020 system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
1021 system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses
1022 system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses
1023 system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses
1024 system.cpu.dcache.overall_misses::total 3771680 # number of overall misses
1025 system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles
1026 system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles
1027 system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles
1028 system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles
1029 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles
1030 system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles
1031 system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles
1032 system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles
1033 system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles
1034 system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles
1035 system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses)
1036 system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses)
1037 system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
1038 system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
1039 system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses)
1040 system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses)
1041 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
1042 system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
1043 system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
1044 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
1045 system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses
1046 system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses
1047 system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses
1048 system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses
1049 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses
1050 system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses
1051 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses
1052 system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses
1053 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses
1054 system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses
1055 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
1056 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
1057 system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses
1058 system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses
1059 system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses
1060 system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses
1061 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency
1062 system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency
1063 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency
1064 system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency
1065 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency
1066 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency
1067 system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency
1068 system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency
1069 system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency
1070 system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency
1071 system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
1072 system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked
1073 system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
1074 system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked
1075 system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked
1076 system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked
1077 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1078 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1079 system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks
1080 system.cpu.dcache.writebacks::total 966282 # number of writebacks
1081 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits
1082 system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits
1083 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits
1084 system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits
1085 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
1086 system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
1087 system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits
1088 system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits
1089 system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits
1090 system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits
1091 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses
1092 system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses
1093 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses
1094 system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses
1095 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
1096 system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
1097 system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses
1098 system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses
1099 system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses
1100 system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses
1101 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles
1102 system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles
1103 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles
1104 system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles
1105 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles
1106 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles
1107 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles
1108 system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles
1109 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles
1110 system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles
1111 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses
1112 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses
1113 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses
1114 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses
1115 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
1116 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
1117 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses
1118 system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses
1119 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses
1120 system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses
1121 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency
1122 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency
1123 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency
1124 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency
1125 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency
1126 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency
1127 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency
1128 system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency
1129 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency
1130 system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency
1131 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1133 ---------- End Simulation Statistics ----------
projects / gem5.git / blob