2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.104498 # Number of seconds simulated
4 sim_ticks 104497559500 # Number of ticks simulated
5 final_tick 104497559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 155883 # Simulator instruction rate (inst/s)
8 host_tick_rate 46665641 # Simulator tick rate (ticks/s)
9 host_mem_usage 228988 # Number of bytes of host memory used
10 host_seconds 2239.28 # Real time elapsed on the host
11 sim_insts 349066034 # Number of instructions simulated
12 system.physmem.bytes_read 464512 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 192704 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 7258 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 4445195 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 1844100 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 4445195 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.dtb.inst_hits 0 # ITB inst hits
22 system.cpu.dtb.inst_misses 0 # ITB inst misses
23 system.cpu.dtb.read_hits 0 # DTB read hits
24 system.cpu.dtb.read_misses 0 # DTB read misses
25 system.cpu.dtb.write_hits 0 # DTB write hits
26 system.cpu.dtb.write_misses 0 # DTB write misses
27 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
28 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
29 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
30 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
31 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
32 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
33 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
34 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
35 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
36 system.cpu.dtb.read_accesses 0 # DTB read accesses
37 system.cpu.dtb.write_accesses 0 # DTB write accesses
38 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
39 system.cpu.dtb.hits 0 # DTB hits
40 system.cpu.dtb.misses 0 # DTB misses
41 system.cpu.dtb.accesses 0 # DTB accesses
42 system.cpu.itb.inst_hits 0 # ITB inst hits
43 system.cpu.itb.inst_misses 0 # ITB inst misses
44 system.cpu.itb.read_hits 0 # DTB read hits
45 system.cpu.itb.read_misses 0 # DTB read misses
46 system.cpu.itb.write_hits 0 # DTB write hits
47 system.cpu.itb.write_misses 0 # DTB write misses
48 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
49 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
50 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
51 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
52 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
53 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
54 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
55 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
56 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
57 system.cpu.itb.read_accesses 0 # DTB read accesses
58 system.cpu.itb.write_accesses 0 # DTB write accesses
59 system.cpu.itb.inst_accesses 0 # ITB inst accesses
60 system.cpu.itb.hits 0 # DTB hits
61 system.cpu.itb.misses 0 # DTB misses
62 system.cpu.itb.accesses 0 # DTB accesses
63 system.cpu.workload.num_syscalls 191 # Number of system calls
64 system.cpu.numCycles 208995120 # number of cpu cycles simulated
65 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
66 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
67 system.cpu.BPredUnit.lookups 38326507 # Number of BP lookups
68 system.cpu.BPredUnit.condPredicted 21101495 # Number of conditional branches predicted
69 system.cpu.BPredUnit.condIncorrect 3258977 # Number of conditional branches incorrect
70 system.cpu.BPredUnit.BTBLookups 27386254 # Number of BTB lookups
71 system.cpu.BPredUnit.BTBHits 21276883 # Number of BTB hits
72 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
73 system.cpu.BPredUnit.usedRAS 7682399 # Number of times the RAS was used to get a target.
74 system.cpu.BPredUnit.RASInCorrect 61114 # Number of incorrect RAS predictions.
75 system.cpu.fetch.icacheStallCycles 43645867 # Number of cycles fetch is stalled on an Icache miss
76 system.cpu.fetch.Insts 338408122 # Number of instructions fetch has processed
77 system.cpu.fetch.Branches 38326507 # Number of branches that fetch encountered
78 system.cpu.fetch.predictedBranches 28959282 # Number of branches that fetch has predicted taken
79 system.cpu.fetch.Cycles 79027162 # Number of cycles fetch has run and was not squashing or blocked
80 system.cpu.fetch.SquashCycles 10989913 # Number of cycles fetch has spent squashing
81 system.cpu.fetch.BlockedCycles 78526305 # Number of cycles fetch has spent blocked
82 system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
83 system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps
84 system.cpu.fetch.CacheLines 41243030 # Number of cache lines fetched
85 system.cpu.fetch.IcacheSquashes 908340 # Number of outstanding Icache misses that were squashed
86 system.cpu.fetch.rateDist::samples 208882385 # Number of instructions fetched each cycle (Total)
87 system.cpu.fetch.rateDist::mean 2.119969 # Number of instructions fetched each cycle (Total)
88 system.cpu.fetch.rateDist::stdev 3.192320 # Number of instructions fetched each cycle (Total)
89 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
90 system.cpu.fetch.rateDist::0 130507129 62.48% 62.48% # Number of instructions fetched each cycle (Total)
91 system.cpu.fetch.rateDist::1 9423807 4.51% 66.99% # Number of instructions fetched each cycle (Total)
92 system.cpu.fetch.rateDist::2 6028759 2.89% 69.88% # Number of instructions fetched each cycle (Total)
93 system.cpu.fetch.rateDist::3 6771553 3.24% 73.12% # Number of instructions fetched each cycle (Total)
94 system.cpu.fetch.rateDist::4 5439017 2.60% 75.72% # Number of instructions fetched each cycle (Total)
95 system.cpu.fetch.rateDist::5 4859666 2.33% 78.05% # Number of instructions fetched each cycle (Total)
96 system.cpu.fetch.rateDist::6 3802857 1.82% 79.87% # Number of instructions fetched each cycle (Total)
97 system.cpu.fetch.rateDist::7 4240079 2.03% 81.90% # Number of instructions fetched each cycle (Total)
98 system.cpu.fetch.rateDist::8 37809518 18.10% 100.00% # Number of instructions fetched each cycle (Total)
99 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
100 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
101 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
102 system.cpu.fetch.rateDist::total 208882385 # Number of instructions fetched each cycle (Total)
103 system.cpu.fetch.branchRate 0.183385 # Number of branch fetches per cycle
104 system.cpu.fetch.rate 1.619215 # Number of inst fetches per cycle
105 system.cpu.decode.IdleCycles 51208963 # Number of cycles decode is idle
106 system.cpu.decode.BlockedCycles 73647751 # Number of cycles decode is blocked
107 system.cpu.decode.RunCycles 72596931 # Number of cycles decode is running
108 system.cpu.decode.UnblockCycles 3816657 # Number of cycles decode is unblocking
109 system.cpu.decode.SquashCycles 7612083 # Number of cycles decode is squashing
110 system.cpu.decode.BranchResolved 7463930 # Number of times decode resolved a branch
111 system.cpu.decode.BranchMispred 71162 # Number of times decode detected a branch misprediction
112 system.cpu.decode.DecodedInsts 431701457 # Number of instructions handled by decode
113 system.cpu.decode.SquashedInsts 197547 # Number of squashed instructions handled by decode
114 system.cpu.rename.SquashCycles 7612083 # Number of cycles rename is squashing
115 system.cpu.rename.IdleCycles 58859623 # Number of cycles rename is idle
116 system.cpu.rename.BlockCycles 1188483 # Number of cycles rename is blocking
117 system.cpu.rename.serializeStallCycles 57604104 # count of cycles rename stalled for serializing inst
118 system.cpu.rename.RunCycles 68958235 # Number of cycles rename is running
119 system.cpu.rename.UnblockCycles 14659857 # Number of cycles rename is unblocking
120 system.cpu.rename.RenamedInsts 416634975 # Number of instructions processed by rename
121 system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
122 system.cpu.rename.LSQFullEvents 8024802 # Number of times rename has blocked due to LSQ full
123 system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
124 system.cpu.rename.RenamedOperands 455431964 # Number of destination operands rename has renamed
125 system.cpu.rename.RenameLookups 2446622850 # Number of register rename lookups that rename has made
126 system.cpu.rename.int_rename_lookups 1351809132 # Number of integer rename lookups
127 system.cpu.rename.fp_rename_lookups 1094813718 # Number of floating rename lookups
128 system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
129 system.cpu.rename.UndoneMaps 70863365 # Number of HB maps that are undone due to squashing
130 system.cpu.rename.serializingInsts 3987641 # count of serializing insts renamed
131 system.cpu.rename.tempSerializingInsts 4044473 # count of temporary serializing insts renamed
132 system.cpu.rename.skidInsts 48252141 # count of insts added to the skid buffer
133 system.cpu.memDep0.insertedLoads 108792162 # Number of loads inserted to the mem dependence unit.
134 system.cpu.memDep0.insertedStores 93099672 # Number of stores inserted to the mem dependence unit.
135 system.cpu.memDep0.conflictingLoads 3342545 # Number of conflicting loads.
136 system.cpu.memDep0.conflictingStores 2273908 # Number of conflicting stores.
137 system.cpu.iq.iqInstsAdded 394239255 # Number of instructions added to the IQ (excludes non-spec)
138 system.cpu.iq.iqNonSpecInstsAdded 3865155 # Number of non-speculative instructions added to the IQ
139 system.cpu.iq.iqInstsIssued 379120981 # Number of instructions issued
140 system.cpu.iq.iqSquashedInstsIssued 1801347 # Number of squashed instructions issued
141 system.cpu.iq.iqSquashedInstsExamined 46369193 # Number of squashed instructions iterated over during squash; mainly for profiling
142 system.cpu.iq.iqSquashedOperandsExamined 143590674 # Number of squashed operands that are examined and possibly removed from graph
143 system.cpu.iq.iqSquashedNonSpecRemoved 309514 # Number of squashed non-spec instructions that were removed
144 system.cpu.iq.issued_per_cycle::samples 208882385 # Number of insts issued each cycle
145 system.cpu.iq.issued_per_cycle::mean 1.814997 # Number of insts issued each cycle
146 system.cpu.iq.issued_per_cycle::stdev 1.995935 # Number of insts issued each cycle
147 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
148 system.cpu.iq.issued_per_cycle::0 82049002 39.28% 39.28% # Number of insts issued each cycle
149 system.cpu.iq.issued_per_cycle::1 34801326 16.66% 55.94% # Number of insts issued each cycle
150 system.cpu.iq.issued_per_cycle::2 24478546 11.72% 67.66% # Number of insts issued each cycle
151 system.cpu.iq.issued_per_cycle::3 18529016 8.87% 76.53% # Number of insts issued each cycle
152 system.cpu.iq.issued_per_cycle::4 21712805 10.39% 86.92% # Number of insts issued each cycle
153 system.cpu.iq.issued_per_cycle::5 15357191 7.35% 94.28% # Number of insts issued each cycle
154 system.cpu.iq.issued_per_cycle::6 8402907 4.02% 98.30% # Number of insts issued each cycle
155 system.cpu.iq.issued_per_cycle::7 2691838 1.29% 99.59% # Number of insts issued each cycle
156 system.cpu.iq.issued_per_cycle::8 859754 0.41% 100.00% # Number of insts issued each cycle
157 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
158 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
159 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
160 system.cpu.iq.issued_per_cycle::total 208882385 # Number of insts issued each cycle
161 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
162 system.cpu.iq.fu_full::IntAlu 2250 0.01% 0.01% # attempts to use FU when none available
163 system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
164 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
165 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
166 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
167 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
168 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
169 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
170 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
171 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
172 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
173 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
174 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
175 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
176 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
177 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
178 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
179 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
180 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
181 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
182 system.cpu.iq.fu_full::SimdFloatAdd 10815 0.06% 0.10% # attempts to use FU when none available
183 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
184 system.cpu.iq.fu_full::SimdFloatCmp 2509 0.01% 0.12% # attempts to use FU when none available
185 system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
186 system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
187 system.cpu.iq.fu_full::SimdFloatMisc 64370 0.37% 0.49% # attempts to use FU when none available
188 system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available
189 system.cpu.iq.fu_full::SimdFloatMultAcc 177500 1.02% 1.52% # attempts to use FU when none available
190 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
191 system.cpu.iq.fu_full::MemRead 9658261 55.66% 57.18% # attempts to use FU when none available
192 system.cpu.iq.fu_full::MemWrite 7430721 42.82% 100.00% # attempts to use FU when none available
193 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
194 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
195 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
196 system.cpu.iq.FU_type_0::IntAlu 129606192 34.19% 34.19% # Type of FU issued
197 system.cpu.iq.FU_type_0::IntMult 2147281 0.57% 34.75% # Type of FU issued
198 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
199 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
200 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
201 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
202 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
203 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
204 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
205 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
206 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
207 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
208 system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 34.75% # Type of FU issued
209 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
210 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
211 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
212 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
213 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
214 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
215 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
216 system.cpu.iq.FU_type_0::SimdFloatAdd 6746387 1.78% 36.53% # Type of FU issued
217 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
218 system.cpu.iq.FU_type_0::SimdFloatCmp 8673518 2.29% 38.82% # Type of FU issued
219 system.cpu.iq.FU_type_0::SimdFloatCvt 3499070 0.92% 39.74% # Type of FU issued
220 system.cpu.iq.FU_type_0::SimdFloatDiv 1584810 0.42% 40.16% # Type of FU issued
221 system.cpu.iq.FU_type_0::SimdFloatMisc 21149805 5.58% 45.74% # Type of FU issued
222 system.cpu.iq.FU_type_0::SimdFloatMult 7187648 1.90% 47.64% # Type of FU issued
223 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147289 1.89% 49.52% # Type of FU issued
224 system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
225 system.cpu.iq.FU_type_0::MemRead 103746274 27.36% 76.93% # Type of FU issued
226 system.cpu.iq.FU_type_0::MemWrite 87457408 23.07% 100.00% # Type of FU issued
227 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
228 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
229 system.cpu.iq.FU_type_0::total 379120981 # Type of FU issued
230 system.cpu.iq.rate 1.814018 # Inst issue rate
231 system.cpu.iq.fu_busy_cnt 17352648 # FU busy when requested
232 system.cpu.iq.fu_busy_rate 0.045771 # FU busy rate (busy events/executed inst)
233 system.cpu.iq.int_inst_queue_reads 735350759 # Number of integer instruction queue reads
234 system.cpu.iq.int_inst_queue_writes 310614656 # Number of integer instruction queue writes
235 system.cpu.iq.int_inst_queue_wakeup_accesses 251531674 # Number of integer instruction queue wakeup accesses
236 system.cpu.iq.fp_inst_queue_reads 250927583 # Number of floating instruction queue reads
237 system.cpu.iq.fp_inst_queue_writes 133866908 # Number of floating instruction queue writes
238 system.cpu.iq.fp_inst_queue_wakeup_accesses 118270115 # Number of floating instruction queue wakeup accesses
239 system.cpu.iq.int_alu_accesses 267600383 # Number of integer alu accesses
240 system.cpu.iq.fp_alu_accesses 128873246 # Number of floating point alu accesses
241 system.cpu.iew.lsq.thread0.forwLoads 7282081 # Number of loads that had data forwarded from stores
242 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
243 system.cpu.iew.lsq.thread0.squashedLoads 14143162 # Number of loads squashed
244 system.cpu.iew.lsq.thread0.ignoredResponses 112354 # Number of memory responses ignored because the instruction is squashed
245 system.cpu.iew.lsq.thread0.memOrderViolation 8279 # Number of memory ordering violations
246 system.cpu.iew.lsq.thread0.squashedStores 10723841 # Number of stores squashed
247 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
248 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
249 system.cpu.iew.lsq.thread0.rescheduledLoads 272 # Number of loads that were rescheduled
250 system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
251 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
252 system.cpu.iew.iewSquashCycles 7612083 # Number of cycles IEW is squashing
253 system.cpu.iew.iewBlockCycles 19341 # Number of cycles IEW is blocking
254 system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
255 system.cpu.iew.iewDispatchedInsts 398151655 # Number of instructions dispatched to IQ
256 system.cpu.iew.iewDispSquashedInsts 2633597 # Number of squashed instructions skipped by dispatch
257 system.cpu.iew.iewDispLoadInsts 108792162 # Number of dispatched load instructions
258 system.cpu.iew.iewDispStoreInsts 93099672 # Number of dispatched store instructions
259 system.cpu.iew.iewDispNonSpecInsts 3853935 # Number of dispatched non-speculative instructions
260 system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
261 system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
262 system.cpu.iew.memOrderViolationEvents 8279 # Number of memory order violations
263 system.cpu.iew.predictedTakenIncorrect 3193235 # Number of branches that were predicted taken incorrectly
264 system.cpu.iew.predictedNotTakenIncorrect 309338 # Number of branches that were predicted not taken incorrectly
265 system.cpu.iew.branchMispredicts 3502573 # Number of branch mispredicts detected at execute
266 system.cpu.iew.iewExecutedInsts 373031388 # Number of executed instructions
267 system.cpu.iew.iewExecLoadInsts 102121270 # Number of load instructions executed
268 system.cpu.iew.iewExecSquashedInsts 6089593 # Number of squashed instructions skipped in execute
269 system.cpu.iew.exec_swp 0 # number of swp insts executed
270 system.cpu.iew.exec_nop 47245 # number of nop insts executed
271 system.cpu.iew.exec_refs 188074720 # number of memory reference insts executed
272 system.cpu.iew.exec_branches 32215232 # Number of branches executed
273 system.cpu.iew.exec_stores 85953450 # Number of stores executed
274 system.cpu.iew.exec_rate 1.784881 # Inst execution rate
275 system.cpu.iew.wb_sent 370805637 # cumulative count of insts sent to commit
276 system.cpu.iew.wb_count 369801789 # cumulative count of insts written-back
277 system.cpu.iew.wb_producers 175613931 # num instructions producing a value
278 system.cpu.iew.wb_consumers 345608979 # num instructions consuming a value
279 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
280 system.cpu.iew.wb_rate 1.769428 # insts written-back per cycle
281 system.cpu.iew.wb_fanout 0.508129 # average fanout of values written-back
282 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
283 system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
284 system.cpu.commit.commitSquashedInsts 49085191 # The number of squashed insts skipped by commit
285 system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
286 system.cpu.commit.branchMispredicts 3229927 # The number of times a branch was mispredicted
287 system.cpu.commit.committed_per_cycle::samples 201270303 # Number of insts commited each cycle
288 system.cpu.commit.committed_per_cycle::mean 1.734318 # Number of insts commited each cycle
289 system.cpu.commit.committed_per_cycle::stdev 2.320939 # Number of insts commited each cycle
290 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
291 system.cpu.commit.committed_per_cycle::0 89873146 44.65% 44.65% # Number of insts commited each cycle
292 system.cpu.commit.committed_per_cycle::1 39586205 19.67% 64.32% # Number of insts commited each cycle
293 system.cpu.commit.committed_per_cycle::2 17962686 8.92% 73.25% # Number of insts commited each cycle
294 system.cpu.commit.committed_per_cycle::3 13145817 6.53% 79.78% # Number of insts commited each cycle
295 system.cpu.commit.committed_per_cycle::4 14573998 7.24% 87.02% # Number of insts commited each cycle
296 system.cpu.commit.committed_per_cycle::5 7584463 3.77% 90.79% # Number of insts commited each cycle
297 system.cpu.commit.committed_per_cycle::6 3507612 1.74% 92.53% # Number of insts commited each cycle
298 system.cpu.commit.committed_per_cycle::7 3437369 1.71% 94.24% # Number of insts commited each cycle
299 system.cpu.commit.committed_per_cycle::8 11599007 5.76% 100.00% # Number of insts commited each cycle
300 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
301 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
302 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
303 system.cpu.commit.committed_per_cycle::total 201270303 # Number of insts commited each cycle
304 system.cpu.commit.count 349066646 # Number of instructions committed
305 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
306 system.cpu.commit.refs 177024831 # Number of memory references committed
307 system.cpu.commit.loads 94649000 # Number of loads committed
308 system.cpu.commit.membars 11033 # Number of memory barriers committed
309 system.cpu.commit.branches 30521879 # Number of branches committed
310 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
311 system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
312 system.cpu.commit.function_calls 6225114 # Number of function calls committed.
313 system.cpu.commit.bw_lim_events 11599007 # number cycles where commit BW limit reached
314 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
315 system.cpu.rob.rob_reads 587820610 # The number of ROB reads
316 system.cpu.rob.rob_writes 803918901 # The number of ROB writes
317 system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
318 system.cpu.idleCycles 112735 # Total number of cycles that the CPU has spent unscheduled due to idling
319 system.cpu.committedInsts 349066034 # Number of Instructions Simulated
320 system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
321 system.cpu.cpi 0.598727 # CPI: Cycles Per Instruction
322 system.cpu.cpi_total 0.598727 # CPI: Total CPI of All Threads
323 system.cpu.ipc 1.670211 # IPC: Instructions Per Cycle
324 system.cpu.ipc_total 1.670211 # IPC: Total IPC of All Threads
325 system.cpu.int_regfile_reads 1781871579 # number of integer regfile reads
326 system.cpu.int_regfile_writes 235815438 # number of integer regfile writes
327 system.cpu.fp_regfile_reads 188771754 # number of floating regfile reads
328 system.cpu.fp_regfile_writes 133861667 # number of floating regfile writes
329 system.cpu.misc_regfile_reads 1003473737 # number of misc regfile reads
330 system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
331 system.cpu.icache.replacements 14107 # number of replacements
332 system.cpu.icache.tagsinuse 1842.677380 # Cycle average of tags in use
333 system.cpu.icache.total_refs 41226387 # Total number of references to valid blocks.
334 system.cpu.icache.sampled_refs 15987 # Sample count of references to valid blocks.
335 system.cpu.icache.avg_refs 2578.744417 # Average number of references to valid blocks.
336 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
337 system.cpu.icache.occ_blocks::0 1842.677380 # Average occupied blocks per context
338 system.cpu.icache.occ_percent::0 0.899745 # Average percentage of cache occupancy
339 system.cpu.icache.ReadReq_hits 41226387 # number of ReadReq hits
340 system.cpu.icache.demand_hits 41226387 # number of demand (read+write) hits
341 system.cpu.icache.overall_hits 41226387 # number of overall hits
342 system.cpu.icache.ReadReq_misses 16643 # number of ReadReq misses
343 system.cpu.icache.demand_misses 16643 # number of demand (read+write) misses
344 system.cpu.icache.overall_misses 16643 # number of overall misses
345 system.cpu.icache.ReadReq_miss_latency 201090500 # number of ReadReq miss cycles
346 system.cpu.icache.demand_miss_latency 201090500 # number of demand (read+write) miss cycles
347 system.cpu.icache.overall_miss_latency 201090500 # number of overall miss cycles
348 system.cpu.icache.ReadReq_accesses 41243030 # number of ReadReq accesses(hits+misses)
349 system.cpu.icache.demand_accesses 41243030 # number of demand (read+write) accesses
350 system.cpu.icache.overall_accesses 41243030 # number of overall (read+write) accesses
351 system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
352 system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
353 system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
354 system.cpu.icache.ReadReq_avg_miss_latency 12082.587274 # average ReadReq miss latency
355 system.cpu.icache.demand_avg_miss_latency 12082.587274 # average overall miss latency
356 system.cpu.icache.overall_avg_miss_latency 12082.587274 # average overall miss latency
357 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
358 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
359 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
360 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
361 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
362 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
363 system.cpu.icache.fast_writes 0 # number of fast writes performed
364 system.cpu.icache.cache_copies 0 # number of cache copies performed
365 system.cpu.icache.writebacks 0 # number of writebacks
366 system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
367 system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
368 system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
369 system.cpu.icache.ReadReq_mshr_misses 16006 # number of ReadReq MSHR misses
370 system.cpu.icache.demand_mshr_misses 16006 # number of demand (read+write) MSHR misses
371 system.cpu.icache.overall_mshr_misses 16006 # number of overall MSHR misses
372 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
373 system.cpu.icache.ReadReq_mshr_miss_latency 136032000 # number of ReadReq MSHR miss cycles
374 system.cpu.icache.demand_mshr_miss_latency 136032000 # number of demand (read+write) MSHR miss cycles
375 system.cpu.icache.overall_mshr_miss_latency 136032000 # number of overall MSHR miss cycles
376 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
377 system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
378 system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
379 system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
380 system.cpu.icache.ReadReq_avg_mshr_miss_latency 8498.812945 # average ReadReq mshr miss latency
381 system.cpu.icache.demand_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
382 system.cpu.icache.overall_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
383 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
384 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
385 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
386 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
387 system.cpu.dcache.replacements 1408 # number of replacements
388 system.cpu.dcache.tagsinuse 3101.194672 # Cycle average of tags in use
389 system.cpu.dcache.total_refs 176614084 # Total number of references to valid blocks.
390 system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks.
391 system.cpu.dcache.avg_refs 38427.781549 # Average number of references to valid blocks.
392 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
393 system.cpu.dcache.occ_blocks::0 3101.194672 # Average occupied blocks per context
394 system.cpu.dcache.occ_percent::0 0.757128 # Average percentage of cache occupancy
395 system.cpu.dcache.ReadReq_hits 94558380 # number of ReadReq hits
396 system.cpu.dcache.WriteReq_hits 82033210 # number of WriteReq hits
397 system.cpu.dcache.LoadLockedReq_hits 11361 # number of LoadLockedReq hits
398 system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
399 system.cpu.dcache.demand_hits 176591590 # number of demand (read+write) hits
400 system.cpu.dcache.overall_hits 176591590 # number of overall hits
401 system.cpu.dcache.ReadReq_misses 3380 # number of ReadReq misses
402 system.cpu.dcache.WriteReq_misses 19484 # number of WriteReq misses
403 system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
404 system.cpu.dcache.demand_misses 22864 # number of demand (read+write) misses
405 system.cpu.dcache.overall_misses 22864 # number of overall misses
406 system.cpu.dcache.ReadReq_miss_latency 111762500 # number of ReadReq miss cycles
407 system.cpu.dcache.WriteReq_miss_latency 649531500 # number of WriteReq miss cycles
408 system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
409 system.cpu.dcache.demand_miss_latency 761294000 # number of demand (read+write) miss cycles
410 system.cpu.dcache.overall_miss_latency 761294000 # number of overall miss cycles
411 system.cpu.dcache.ReadReq_accesses 94561760 # number of ReadReq accesses(hits+misses)
412 system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
413 system.cpu.dcache.LoadLockedReq_accesses 11363 # number of LoadLockedReq accesses(hits+misses)
414 system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
415 system.cpu.dcache.demand_accesses 176614454 # number of demand (read+write) accesses
416 system.cpu.dcache.overall_accesses 176614454 # number of overall (read+write) accesses
417 system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
418 system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
419 system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
420 system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
421 system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
422 system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402 # average ReadReq miss latency
423 system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850 # average WriteReq miss latency
424 system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
425 system.cpu.dcache.demand_avg_miss_latency 33296.623513 # average overall miss latency
426 system.cpu.dcache.overall_avg_miss_latency 33296.623513 # average overall miss latency
427 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
428 system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
429 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
430 system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
431 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
432 system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
433 system.cpu.dcache.fast_writes 0 # number of fast writes performed
434 system.cpu.dcache.cache_copies 0 # number of cache copies performed
435 system.cpu.dcache.writebacks 1030 # number of writebacks
436 system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits
437 system.cpu.dcache.WriteReq_mshr_hits 16619 # number of WriteReq MSHR hits
438 system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
439 system.cpu.dcache.demand_mshr_hits 18249 # number of demand (read+write) MSHR hits
440 system.cpu.dcache.overall_mshr_hits 18249 # number of overall MSHR hits
441 system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
442 system.cpu.dcache.WriteReq_mshr_misses 2865 # number of WriteReq MSHR misses
443 system.cpu.dcache.demand_mshr_misses 4615 # number of demand (read+write) MSHR misses
444 system.cpu.dcache.overall_mshr_misses 4615 # number of overall MSHR misses
445 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
446 system.cpu.dcache.ReadReq_mshr_miss_latency 53437000 # number of ReadReq MSHR miss cycles
447 system.cpu.dcache.WriteReq_mshr_miss_latency 101725000 # number of WriteReq MSHR miss cycles
448 system.cpu.dcache.demand_mshr_miss_latency 155162000 # number of demand (read+write) MSHR miss cycles
449 system.cpu.dcache.overall_mshr_miss_latency 155162000 # number of overall MSHR miss cycles
450 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
451 system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
452 system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
453 system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
454 system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
455 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571 # average ReadReq mshr miss latency
456 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202 # average WriteReq mshr miss latency
457 system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
458 system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
459 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
460 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
461 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
462 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
463 system.cpu.l2cache.replacements 57 # number of replacements
464 system.cpu.l2cache.tagsinuse 3897.011564 # Cycle average of tags in use
465 system.cpu.l2cache.total_refs 13334 # Total number of references to valid blocks.
466 system.cpu.l2cache.sampled_refs 5354 # Sample count of references to valid blocks.
467 system.cpu.l2cache.avg_refs 2.490474 # Average number of references to valid blocks.
468 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
469 system.cpu.l2cache.occ_blocks::0 3518.810301 # Average occupied blocks per context
470 system.cpu.l2cache.occ_blocks::1 378.201262 # Average occupied blocks per context
471 system.cpu.l2cache.occ_percent::0 0.107386 # Average percentage of cache occupancy
472 system.cpu.l2cache.occ_percent::1 0.011542 # Average percentage of cache occupancy
473 system.cpu.l2cache.ReadReq_hits 13251 # number of ReadReq hits
474 system.cpu.l2cache.Writeback_hits 1030 # number of Writeback hits
475 system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
476 system.cpu.l2cache.demand_hits 13270 # number of demand (read+write) hits
477 system.cpu.l2cache.overall_hits 13270 # number of overall hits
478 system.cpu.l2cache.ReadReq_misses 4485 # number of ReadReq misses
479 system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
480 system.cpu.l2cache.ReadExReq_misses 2828 # number of ReadExReq misses
481 system.cpu.l2cache.demand_misses 7313 # number of demand (read+write) misses
482 system.cpu.l2cache.overall_misses 7313 # number of overall misses
483 system.cpu.l2cache.ReadReq_miss_latency 153892500 # number of ReadReq miss cycles
484 system.cpu.l2cache.ReadExReq_miss_latency 97502000 # number of ReadExReq miss cycles
485 system.cpu.l2cache.demand_miss_latency 251394500 # number of demand (read+write) miss cycles
486 system.cpu.l2cache.overall_miss_latency 251394500 # number of overall miss cycles
487 system.cpu.l2cache.ReadReq_accesses 17736 # number of ReadReq accesses(hits+misses)
488 system.cpu.l2cache.Writeback_accesses 1030 # number of Writeback accesses(hits+misses)
489 system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
490 system.cpu.l2cache.ReadExReq_accesses 2847 # number of ReadExReq accesses(hits+misses)
491 system.cpu.l2cache.demand_accesses 20583 # number of demand (read+write) accesses
492 system.cpu.l2cache.overall_accesses 20583 # number of overall (read+write) accesses
493 system.cpu.l2cache.ReadReq_miss_rate 0.252876 # miss rate for ReadReq accesses
494 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
495 system.cpu.l2cache.ReadExReq_miss_rate 0.993326 # miss rate for ReadExReq accesses
496 system.cpu.l2cache.demand_miss_rate 0.355293 # miss rate for demand accesses
497 system.cpu.l2cache.overall_miss_rate 0.355293 # miss rate for overall accesses
498 system.cpu.l2cache.ReadReq_avg_miss_latency 34312.709030 # average ReadReq miss latency
499 system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.369165 # average ReadExReq miss latency
500 system.cpu.l2cache.demand_avg_miss_latency 34376.384521 # average overall miss latency
501 system.cpu.l2cache.overall_avg_miss_latency 34376.384521 # average overall miss latency
502 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
503 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
504 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
505 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
506 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
507 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
508 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
509 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
510 system.cpu.l2cache.writebacks 0 # number of writebacks
511 system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
512 system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
513 system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
514 system.cpu.l2cache.ReadReq_mshr_misses 4430 # number of ReadReq MSHR misses
515 system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
516 system.cpu.l2cache.ReadExReq_mshr_misses 2828 # number of ReadExReq MSHR misses
517 system.cpu.l2cache.demand_mshr_misses 7258 # number of demand (read+write) MSHR misses
518 system.cpu.l2cache.overall_mshr_misses 7258 # number of overall MSHR misses
519 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
520 system.cpu.l2cache.ReadReq_mshr_miss_latency 138008000 # number of ReadReq MSHR miss cycles
521 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles
522 system.cpu.l2cache.ReadExReq_mshr_miss_latency 88479500 # number of ReadExReq MSHR miss cycles
523 system.cpu.l2cache.demand_mshr_miss_latency 226487500 # number of demand (read+write) MSHR miss cycles
524 system.cpu.l2cache.overall_mshr_miss_latency 226487500 # number of overall MSHR miss cycles
525 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
526 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249774 # mshr miss rate for ReadReq accesses
527 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
528 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993326 # mshr miss rate for ReadExReq accesses
529 system.cpu.l2cache.demand_mshr_miss_rate 0.352621 # mshr miss rate for demand accesses
530 system.cpu.l2cache.overall_mshr_miss_rate 0.352621 # mshr miss rate for overall accesses
531 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.047404 # average ReadReq mshr miss latency
532 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
533 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31286.951909 # average ReadExReq mshr miss latency
534 system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
535 system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
536 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
537 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
538 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
539 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
541 ---------- End Simulation Statistics ----------
projects / gem5.git / blob