2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.071023 # Number of seconds simulated
4 sim_ticks 71023388000 # Number of ticks simulated
5 final_tick 71023388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 129198 # Simulator instruction rate (inst/s)
8 host_op_rate 165172 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 33606101 # Simulator tick rate (ticks/s)
10 host_mem_usage 240544 # Number of bytes of host memory used
11 host_seconds 2113.41 # Real time elapsed on the host
12 sim_insts 273048441 # Number of instructions simulated
13 sim_ops 349076165 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 467712 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory
19 system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory
20 system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory
21 system.physmem.num_reads::total 7308 # Number of read requests responded to by this memory
22 system.physmem.bw_read::cpu.inst 2743885 # Total read bandwidth from this memory (bytes/s)
23 system.physmem.bw_read::cpu.data 3841439 # Total read bandwidth from this memory (bytes/s)
24 system.physmem.bw_read::total 6585324 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_inst_read::cpu.inst 2743885 # Instruction read bandwidth from this memory (bytes/s)
26 system.physmem.bw_inst_read::total 2743885 # Instruction read bandwidth from this memory (bytes/s)
27 system.physmem.bw_total::cpu.inst 2743885 # Total bandwidth to/from this memory (bytes/s)
28 system.physmem.bw_total::cpu.data 3841439 # Total bandwidth to/from this memory (bytes/s)
29 system.physmem.bw_total::total 6585324 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.readReqs 7308 # Total number of read requests seen
31 system.physmem.writeReqs 0 # Total number of write requests seen
32 system.physmem.cpureqs 7308 # Reqs generatd by CPU via cache - shady
33 system.physmem.bytesRead 467712 # Total number of bytes read from memory
34 system.physmem.bytesWritten 0 # Total number of bytes written to memory
35 system.physmem.bytesConsumedRd 467712 # bytesRead derated as per pkt->getSize()
36 system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37 system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39 system.physmem.perBankRdReqs::0 345 # Track reads on a per bank basis
40 system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis
41 system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis
42 system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis
43 system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis
44 system.physmem.perBankRdReqs::5 461 # Track reads on a per bank basis
45 system.physmem.perBankRdReqs::6 441 # Track reads on a per bank basis
46 system.physmem.perBankRdReqs::7 510 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::12 363 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::13 415 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::15 362 # Track reads on a per bank basis
55 system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56 system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57 system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58 system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59 system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60 system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61 system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62 system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73 system.physmem.totGap 71023232000 # Total gap between requests
74 system.physmem.readPktSize::0 0 # Categorize read packet sizes
75 system.physmem.readPktSize::1 0 # Categorize read packet sizes
76 system.physmem.readPktSize::2 0 # Categorize read packet sizes
77 system.physmem.readPktSize::3 0 # Categorize read packet sizes
78 system.physmem.readPktSize::4 0 # Categorize read packet sizes
79 system.physmem.readPktSize::5 0 # Categorize read packet sizes
80 system.physmem.readPktSize::6 7308 # Categorize read packet sizes
81 system.physmem.readPktSize::7 0 # Categorize read packet sizes
82 system.physmem.readPktSize::8 0 # Categorize read packet sizes
83 system.physmem.writePktSize::0 0 # categorize write packet sizes
84 system.physmem.writePktSize::1 0 # categorize write packet sizes
85 system.physmem.writePktSize::2 0 # categorize write packet sizes
86 system.physmem.writePktSize::3 0 # categorize write packet sizes
87 system.physmem.writePktSize::4 0 # categorize write packet sizes
88 system.physmem.writePktSize::5 0 # categorize write packet sizes
89 system.physmem.writePktSize::6 0 # categorize write packet sizes
90 system.physmem.writePktSize::7 0 # categorize write packet sizes
91 system.physmem.writePktSize::8 0 # categorize write packet sizes
92 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98 system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101 system.physmem.rdQLenPdf::0 4207 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::1 2152 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::2 666 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::3 201 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::4 75 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167 system.physmem.totQLat 41389289 # Total cycles spent in queuing delays
168 system.physmem.totMemAccLat 172709289 # Sum of mem lat for all requests
169 system.physmem.totBusLat 29232000 # Total cycles spent in databus access
170 system.physmem.totBankLat 102088000 # Total cycles spent in bank access
171 system.physmem.avgQLat 5663.56 # Average queueing delay per request
172 system.physmem.avgBankLat 13969.35 # Average bank access latency per request
173 system.physmem.avgBusLat 4000.00 # Average bus latency per request
174 system.physmem.avgMemAccLat 23632.91 # Average memory access latency
175 system.physmem.avgRdBW 6.59 # Average achieved read bandwidth in MB/s
176 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177 system.physmem.avgConsumedRdBW 6.59 # Average consumed read bandwidth in MB/s
178 system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180 system.physmem.busUtil 0.04 # Data bus utilization in percentage
181 system.physmem.avgRdQLen 0.00 # Average read queue length over time
182 system.physmem.avgWrQLen 0.00 # Average write queue length over time
183 system.physmem.readRowHits 6370 # Number of row buffer hits during reads
184 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185 system.physmem.readRowHitRate 87.16 # Row buffer hit rate for reads
186 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187 system.physmem.avgGap 9718559.39 # Average gap between requests
188 system.cpu.dtb.inst_hits 0 # ITB inst hits
189 system.cpu.dtb.inst_misses 0 # ITB inst misses
190 system.cpu.dtb.read_hits 0 # DTB read hits
191 system.cpu.dtb.read_misses 0 # DTB read misses
192 system.cpu.dtb.write_hits 0 # DTB write hits
193 system.cpu.dtb.write_misses 0 # DTB write misses
194 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
195 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
196 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
197 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
198 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
199 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
200 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
201 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
202 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
203 system.cpu.dtb.read_accesses 0 # DTB read accesses
204 system.cpu.dtb.write_accesses 0 # DTB write accesses
205 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
206 system.cpu.dtb.hits 0 # DTB hits
207 system.cpu.dtb.misses 0 # DTB misses
208 system.cpu.dtb.accesses 0 # DTB accesses
209 system.cpu.itb.inst_hits 0 # ITB inst hits
210 system.cpu.itb.inst_misses 0 # ITB inst misses
211 system.cpu.itb.read_hits 0 # DTB read hits
212 system.cpu.itb.read_misses 0 # DTB read misses
213 system.cpu.itb.write_hits 0 # DTB write hits
214 system.cpu.itb.write_misses 0 # DTB write misses
215 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
216 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
217 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
218 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
219 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
220 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
221 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
222 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
223 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
224 system.cpu.itb.read_accesses 0 # DTB read accesses
225 system.cpu.itb.write_accesses 0 # DTB write accesses
226 system.cpu.itb.inst_accesses 0 # ITB inst accesses
227 system.cpu.itb.hits 0 # DTB hits
228 system.cpu.itb.misses 0 # DTB misses
229 system.cpu.itb.accesses 0 # DTB accesses
230 system.cpu.workload.num_syscalls 191 # Number of system calls
231 system.cpu.numCycles 142046777 # number of cpu cycles simulated
232 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
233 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
234 system.cpu.BPredUnit.lookups 43162042 # Number of BP lookups
235 system.cpu.BPredUnit.condPredicted 21862143 # Number of conditional branches predicted
236 system.cpu.BPredUnit.condIncorrect 2121703 # Number of conditional branches incorrect
237 system.cpu.BPredUnit.BTBLookups 28877793 # Number of BTB lookups
238 system.cpu.BPredUnit.BTBHits 17918646 # Number of BTB hits
239 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
240 system.cpu.BPredUnit.usedRAS 6972885 # Number of times the RAS was used to get a target.
241 system.cpu.BPredUnit.RASInCorrect 7671 # Number of incorrect RAS predictions.
242 system.cpu.fetch.icacheStallCycles 40968439 # Number of cycles fetch is stalled on an Icache miss
243 system.cpu.fetch.Insts 329355833 # Number of instructions fetch has processed
244 system.cpu.fetch.Branches 43162042 # Number of branches that fetch encountered
245 system.cpu.fetch.predictedBranches 24891531 # Number of branches that fetch has predicted taken
246 system.cpu.fetch.Cycles 73809901 # Number of cycles fetch has run and was not squashing or blocked
247 system.cpu.fetch.SquashCycles 8464308 # Number of cycles fetch has spent squashing
248 system.cpu.fetch.BlockedCycles 20842753 # Number of cycles fetch has spent blocked
249 system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
250 system.cpu.fetch.PendingTrapStallCycles 2971 # Number of stall cycles due to pending traps
251 system.cpu.fetch.CacheLines 39491995 # Number of cache lines fetched
252 system.cpu.fetch.IcacheSquashes 707720 # Number of outstanding Icache misses that were squashed
253 system.cpu.fetch.rateDist::samples 141956225 # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::mean 2.979912 # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::stdev 3.453592 # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::0 68825893 48.48% 48.48% # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::1 7402388 5.21% 53.70% # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::2 5830184 4.11% 57.81% # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.rateDist::3 6288593 4.43% 62.24% # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::4 4967322 3.50% 65.73% # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::5 4323548 3.05% 68.78% # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::6 3311772 2.33% 71.11% # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.rateDist::7 4321361 3.04% 74.16% # Number of instructions fetched each cycle (Total)
265 system.cpu.fetch.rateDist::8 36685164 25.84% 100.00% # Number of instructions fetched each cycle (Total)
266 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
267 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
268 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
269 system.cpu.fetch.rateDist::total 141956225 # Number of instructions fetched each cycle (Total)
270 system.cpu.fetch.branchRate 0.303858 # Number of branch fetches per cycle
271 system.cpu.fetch.rate 2.318643 # Number of inst fetches per cycle
272 system.cpu.decode.IdleCycles 47854672 # Number of cycles decode is idle
273 system.cpu.decode.BlockedCycles 16043866 # Number of cycles decode is blocked
274 system.cpu.decode.RunCycles 69433090 # Number of cycles decode is running
275 system.cpu.decode.UnblockCycles 2362421 # Number of cycles decode is unblocking
276 system.cpu.decode.SquashCycles 6262176 # Number of cycles decode is squashing
277 system.cpu.decode.BranchResolved 7513619 # Number of times decode resolved a branch
278 system.cpu.decode.BranchMispred 70716 # Number of times decode detected a branch misprediction
279 system.cpu.decode.DecodedInsts 415062954 # Number of instructions handled by decode
280 system.cpu.decode.SquashedInsts 220817 # Number of squashed instructions handled by decode
281 system.cpu.rename.SquashCycles 6262176 # Number of cycles rename is squashing
282 system.cpu.rename.IdleCycles 53639950 # Number of cycles rename is idle
283 system.cpu.rename.BlockCycles 1545689 # Number of cycles rename is blocking
284 system.cpu.rename.serializeStallCycles 333184 # count of cycles rename stalled for serializing inst
285 system.cpu.rename.RunCycles 65936980 # Number of cycles rename is running
286 system.cpu.rename.UnblockCycles 14238246 # Number of cycles rename is unblocking
287 system.cpu.rename.RenamedInsts 404539854 # Number of instructions processed by rename
288 system.cpu.rename.ROBFullEvents 67 # Number of times rename has blocked due to ROB full
289 system.cpu.rename.IQFullEvents 1667551 # Number of times rename has blocked due to IQ full
290 system.cpu.rename.LSQFullEvents 10176735 # Number of times rename has blocked due to LSQ full
291 system.cpu.rename.FullRegisterEvents 553 # Number of times there has been no free registers
292 system.cpu.rename.RenamedOperands 443995291 # Number of destination operands rename has renamed
293 system.cpu.rename.RenameLookups 2389355526 # Number of register rename lookups that rename has made
294 system.cpu.rename.int_rename_lookups 1302857658 # Number of integer rename lookups
295 system.cpu.rename.fp_rename_lookups 1086497868 # Number of floating rename lookups
296 system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed
297 system.cpu.rename.UndoneMaps 59410345 # Number of HB maps that are undone due to squashing
298 system.cpu.rename.serializingInsts 14542 # count of serializing insts renamed
299 system.cpu.rename.tempSerializingInsts 14541 # count of temporary serializing insts renamed
300 system.cpu.rename.skidInsts 35671511 # count of insts added to the skid buffer
301 system.cpu.memDep0.insertedLoads 105577606 # Number of loads inserted to the mem dependence unit.
302 system.cpu.memDep0.insertedStores 93228051 # Number of stores inserted to the mem dependence unit.
303 system.cpu.memDep0.conflictingLoads 4593885 # Number of conflicting loads.
304 system.cpu.memDep0.conflictingStores 5660351 # Number of conflicting stores.
305 system.cpu.iq.iqInstsAdded 392311117 # Number of instructions added to the IQ (excludes non-spec)
306 system.cpu.iq.iqNonSpecInstsAdded 25611 # Number of non-speculative instructions added to the IQ
307 system.cpu.iq.iqInstsIssued 378254160 # Number of instructions issued
308 system.cpu.iq.iqSquashedInstsIssued 1403521 # Number of squashed instructions issued
309 system.cpu.iq.iqSquashedInstsExamined 42287591 # Number of squashed instructions iterated over during squash; mainly for profiling
310 system.cpu.iq.iqSquashedOperandsExamined 111052876 # Number of squashed operands that are examined and possibly removed from graph
311 system.cpu.iq.iqSquashedNonSpecRemoved 1134 # Number of squashed non-spec instructions that were removed
312 system.cpu.iq.issued_per_cycle::samples 141956225 # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::mean 2.664583 # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::stdev 2.042822 # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
316 system.cpu.iq.issued_per_cycle::0 28896984 20.36% 20.36% # Number of insts issued each cycle
317 system.cpu.iq.issued_per_cycle::1 20515288 14.45% 34.81% # Number of insts issued each cycle
318 system.cpu.iq.issued_per_cycle::2 20937445 14.75% 49.56% # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::3 18231025 12.84% 62.40% # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::4 24110473 16.98% 79.38% # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::5 15997056 11.27% 90.65% # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::6 9050570 6.38% 97.03% # Number of insts issued each cycle
323 system.cpu.iq.issued_per_cycle::7 3298757 2.32% 99.35% # Number of insts issued each cycle
324 system.cpu.iq.issued_per_cycle::8 918627 0.65% 100.00% # Number of insts issued each cycle
325 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
326 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
327 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
328 system.cpu.iq.issued_per_cycle::total 141956225 # Number of insts issued each cycle
329 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
330 system.cpu.iq.fu_full::IntAlu 9062 0.05% 0.05% # attempts to use FU when none available
331 system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available
332 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
333 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
334 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
335 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
336 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
337 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
338 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdFloatAdd 45808 0.25% 0.33% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdFloatCmp 7711 0.04% 0.37% # attempts to use FU when none available
353 system.cpu.iq.fu_full::SimdFloatCvt 383 0.00% 0.38% # attempts to use FU when none available
354 system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available
355 system.cpu.iq.fu_full::SimdFloatMisc 193806 1.08% 1.45% # attempts to use FU when none available
356 system.cpu.iq.fu_full::SimdFloatMult 5491 0.03% 1.49% # attempts to use FU when none available
357 system.cpu.iq.fu_full::SimdFloatMultAcc 241038 1.34% 2.83% # attempts to use FU when none available
358 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
359 system.cpu.iq.fu_full::MemRead 9458380 52.63% 55.45% # attempts to use FU when none available
360 system.cpu.iq.fu_full::MemWrite 8006771 44.55% 100.00% # attempts to use FU when none available
361 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
362 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
363 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
364 system.cpu.iq.FU_type_0::IntAlu 128369790 33.94% 33.94% # Type of FU issued
365 system.cpu.iq.FU_type_0::IntMult 2174598 0.57% 34.51% # Type of FU issued
366 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued
367 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued
368 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued
369 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued
370 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued
371 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued
372 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdFloatAdd 6843583 1.81% 36.32% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdFloatCmp 8689764 2.30% 38.62% # Type of FU issued
387 system.cpu.iq.FU_type_0::SimdFloatCvt 3465929 0.92% 39.54% # Type of FU issued
388 system.cpu.iq.FU_type_0::SimdFloatDiv 1622822 0.43% 39.96% # Type of FU issued
389 system.cpu.iq.FU_type_0::SimdFloatMisc 21343412 5.64% 45.61% # Type of FU issued
390 system.cpu.iq.FU_type_0::SimdFloatMult 7172666 1.90% 47.50% # Type of FU issued
391 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136167 1.89% 49.39% # Type of FU issued
392 system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.44% # Type of FU issued
393 system.cpu.iq.FU_type_0::MemRead 102562726 27.11% 76.55% # Type of FU issued
394 system.cpu.iq.FU_type_0::MemWrite 88697415 23.45% 100.00% # Type of FU issued
395 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
396 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
397 system.cpu.iq.FU_type_0::total 378254160 # Type of FU issued
398 system.cpu.iq.rate 2.662884 # Inst issue rate
399 system.cpu.iq.fu_busy_cnt 17973147 # FU busy when requested
400 system.cpu.iq.fu_busy_rate 0.047516 # FU busy rate (busy events/executed inst)
401 system.cpu.iq.int_inst_queue_reads 666559792 # Number of integer instruction queue reads
402 system.cpu.iq.int_inst_queue_writes 301879538 # Number of integer instruction queue writes
403 system.cpu.iq.int_inst_queue_wakeup_accesses 252435570 # Number of integer instruction queue wakeup accesses
404 system.cpu.iq.fp_inst_queue_reads 251281421 # Number of floating instruction queue reads
405 system.cpu.iq.fp_inst_queue_writes 132758695 # Number of floating instruction queue writes
406 system.cpu.iq.fp_inst_queue_wakeup_accesses 118859507 # Number of floating instruction queue wakeup accesses
407 system.cpu.iq.int_alu_accesses 266684443 # Number of integer alu accesses
408 system.cpu.iq.fp_alu_accesses 129542864 # Number of floating point alu accesses
409 system.cpu.iew.lsq.thread0.forwLoads 10845590 # Number of loads that had data forwarded from stores
410 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
411 system.cpu.iew.lsq.thread0.squashedLoads 10926514 # Number of loads squashed
412 system.cpu.iew.lsq.thread0.ignoredResponses 120350 # Number of memory responses ignored because the instruction is squashed
413 system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations
414 system.cpu.iew.lsq.thread0.squashedStores 10850116 # Number of stores squashed
415 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
416 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
417 system.cpu.iew.lsq.thread0.rescheduledLoads 27154 # Number of loads that were rescheduled
418 system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked
419 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
420 system.cpu.iew.iewSquashCycles 6262176 # Number of cycles IEW is squashing
421 system.cpu.iew.iewBlockCycles 55211 # Number of cycles IEW is blocking
422 system.cpu.iew.iewUnblockCycles 11686 # Number of cycles IEW is unblocking
423 system.cpu.iew.iewDispatchedInsts 392346402 # Number of instructions dispatched to IQ
424 system.cpu.iew.iewDispSquashedInsts 1078418 # Number of squashed instructions skipped by dispatch
425 system.cpu.iew.iewDispLoadInsts 105577606 # Number of dispatched load instructions
426 system.cpu.iew.iewDispStoreInsts 93228051 # Number of dispatched store instructions
427 system.cpu.iew.iewDispNonSpecInsts 14439 # Number of dispatched non-speculative instructions
428 system.cpu.iew.iewIQFullEvents 194 # Number of times the IQ has become full, causing a stall
429 system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall
430 system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations
431 system.cpu.iew.predictedTakenIncorrect 1702737 # Number of branches that were predicted taken incorrectly
432 system.cpu.iew.predictedNotTakenIncorrect 499287 # Number of branches that were predicted not taken incorrectly
433 system.cpu.iew.branchMispredicts 2202024 # Number of branch mispredicts detected at execute
434 system.cpu.iew.iewExecutedInsts 373561232 # Number of executed instructions
435 system.cpu.iew.iewExecLoadInsts 101191974 # Number of load instructions executed
436 system.cpu.iew.iewExecSquashedInsts 4692928 # Number of squashed instructions skipped in execute
437 system.cpu.iew.exec_swp 0 # number of swp insts executed
438 system.cpu.iew.exec_nop 9674 # number of nop insts executed
439 system.cpu.iew.exec_refs 188550520 # number of memory reference insts executed
440 system.cpu.iew.exec_branches 38725245 # Number of branches executed
441 system.cpu.iew.exec_stores 87358546 # Number of stores executed
442 system.cpu.iew.exec_rate 2.629847 # Inst execution rate
443 system.cpu.iew.wb_sent 372099364 # cumulative count of insts sent to commit
444 system.cpu.iew.wb_count 371295077 # cumulative count of insts written-back
445 system.cpu.iew.wb_producers 184920977 # num instructions producing a value
446 system.cpu.iew.wb_consumers 367888043 # num instructions consuming a value
447 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
448 system.cpu.iew.wb_rate 2.613893 # insts written-back per cycle
449 system.cpu.iew.wb_fanout 0.502656 # average fanout of values written-back
450 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
451 system.cpu.commit.commitSquashedInsts 43269770 # The number of squashed insts skipped by commit
452 system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards
453 system.cpu.commit.branchMispredicts 2051746 # The number of times a branch was mispredicted
454 system.cpu.commit.committed_per_cycle::samples 135694050 # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::mean 2.572528 # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::stdev 2.654395 # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
458 system.cpu.commit.committed_per_cycle::0 38297743 28.22% 28.22% # Number of insts commited each cycle
459 system.cpu.commit.committed_per_cycle::1 29217550 21.53% 49.76% # Number of insts commited each cycle
460 system.cpu.commit.committed_per_cycle::2 13522381 9.97% 59.72% # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::3 11119570 8.19% 67.92% # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::4 13774007 10.15% 78.07% # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::5 7289874 5.37% 83.44% # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::6 3949510 2.91% 86.35% # Number of insts commited each cycle
465 system.cpu.commit.committed_per_cycle::7 3974023 2.93% 89.28% # Number of insts commited each cycle
466 system.cpu.commit.committed_per_cycle::8 14549392 10.72% 100.00% # Number of insts commited each cycle
467 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
468 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
469 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
470 system.cpu.commit.committed_per_cycle::total 135694050 # Number of insts commited each cycle
471 system.cpu.commit.committedInsts 273049053 # Number of instructions committed
472 system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed
473 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
474 system.cpu.commit.refs 177029027 # Number of memory references committed
475 system.cpu.commit.loads 94651092 # Number of loads committed
476 system.cpu.commit.membars 11033 # Number of memory barriers committed
477 system.cpu.commit.branches 36549055 # Number of branches committed
478 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
479 system.cpu.commit.int_insts 279593983 # Number of committed integer instructions.
480 system.cpu.commit.function_calls 6225112 # Number of function calls committed.
481 system.cpu.commit.bw_lim_events 14549392 # number cycles where commit BW limit reached
482 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
483 system.cpu.rob.rob_reads 513488682 # The number of ROB reads
484 system.cpu.rob.rob_writes 790959694 # The number of ROB writes
485 system.cpu.timesIdled 2717 # Number of times that the entire CPU went into an idle state and unscheduled itself
486 system.cpu.idleCycles 90552 # Total number of cycles that the CPU has spent unscheduled due to idling
487 system.cpu.committedInsts 273048441 # Number of Instructions Simulated
488 system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated
489 system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated
490 system.cpu.cpi 0.520226 # CPI: Cycles Per Instruction
491 system.cpu.cpi_total 0.520226 # CPI: Total CPI of All Threads
492 system.cpu.ipc 1.922243 # IPC: Instructions Per Cycle
493 system.cpu.ipc_total 1.922243 # IPC: Total IPC of All Threads
494 system.cpu.int_regfile_reads 1784209945 # number of integer regfile reads
495 system.cpu.int_regfile_writes 236299492 # number of integer regfile writes
496 system.cpu.fp_regfile_reads 189823111 # number of floating regfile reads
497 system.cpu.fp_regfile_writes 133661428 # number of floating regfile writes
498 system.cpu.misc_regfile_reads 991633784 # number of misc regfile reads
499 system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes
500 system.cpu.icache.replacements 13962 # number of replacements
501 system.cpu.icache.tagsinuse 1856.548325 # Cycle average of tags in use
502 system.cpu.icache.total_refs 39475406 # Total number of references to valid blocks.
503 system.cpu.icache.sampled_refs 15856 # Sample count of references to valid blocks.
504 system.cpu.icache.avg_refs 2489.619450 # Average number of references to valid blocks.
505 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
506 system.cpu.icache.occ_blocks::cpu.inst 1856.548325 # Average occupied blocks per requestor
507 system.cpu.icache.occ_percent::cpu.inst 0.906518 # Average percentage of cache occupancy
508 system.cpu.icache.occ_percent::total 0.906518 # Average percentage of cache occupancy
509 system.cpu.icache.ReadReq_hits::cpu.inst 39475406 # number of ReadReq hits
510 system.cpu.icache.ReadReq_hits::total 39475406 # number of ReadReq hits
511 system.cpu.icache.demand_hits::cpu.inst 39475406 # number of demand (read+write) hits
512 system.cpu.icache.demand_hits::total 39475406 # number of demand (read+write) hits
513 system.cpu.icache.overall_hits::cpu.inst 39475406 # number of overall hits
514 system.cpu.icache.overall_hits::total 39475406 # number of overall hits
515 system.cpu.icache.ReadReq_misses::cpu.inst 16589 # number of ReadReq misses
516 system.cpu.icache.ReadReq_misses::total 16589 # number of ReadReq misses
517 system.cpu.icache.demand_misses::cpu.inst 16589 # number of demand (read+write) misses
518 system.cpu.icache.demand_misses::total 16589 # number of demand (read+write) misses
519 system.cpu.icache.overall_misses::cpu.inst 16589 # number of overall misses
520 system.cpu.icache.overall_misses::total 16589 # number of overall misses
521 system.cpu.icache.ReadReq_miss_latency::cpu.inst 174124000 # number of ReadReq miss cycles
522 system.cpu.icache.ReadReq_miss_latency::total 174124000 # number of ReadReq miss cycles
523 system.cpu.icache.demand_miss_latency::cpu.inst 174124000 # number of demand (read+write) miss cycles
524 system.cpu.icache.demand_miss_latency::total 174124000 # number of demand (read+write) miss cycles
525 system.cpu.icache.overall_miss_latency::cpu.inst 174124000 # number of overall miss cycles
526 system.cpu.icache.overall_miss_latency::total 174124000 # number of overall miss cycles
527 system.cpu.icache.ReadReq_accesses::cpu.inst 39491995 # number of ReadReq accesses(hits+misses)
528 system.cpu.icache.ReadReq_accesses::total 39491995 # number of ReadReq accesses(hits+misses)
529 system.cpu.icache.demand_accesses::cpu.inst 39491995 # number of demand (read+write) accesses
530 system.cpu.icache.demand_accesses::total 39491995 # number of demand (read+write) accesses
531 system.cpu.icache.overall_accesses::cpu.inst 39491995 # number of overall (read+write) accesses
532 system.cpu.icache.overall_accesses::total 39491995 # number of overall (read+write) accesses
533 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000420 # miss rate for ReadReq accesses
534 system.cpu.icache.ReadReq_miss_rate::total 0.000420 # miss rate for ReadReq accesses
535 system.cpu.icache.demand_miss_rate::cpu.inst 0.000420 # miss rate for demand accesses
536 system.cpu.icache.demand_miss_rate::total 0.000420 # miss rate for demand accesses
537 system.cpu.icache.overall_miss_rate::cpu.inst 0.000420 # miss rate for overall accesses
538 system.cpu.icache.overall_miss_rate::total 0.000420 # miss rate for overall accesses
539 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10496.353005 # average ReadReq miss latency
540 system.cpu.icache.ReadReq_avg_miss_latency::total 10496.353005 # average ReadReq miss latency
541 system.cpu.icache.demand_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency
542 system.cpu.icache.demand_avg_miss_latency::total 10496.353005 # average overall miss latency
543 system.cpu.icache.overall_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency
544 system.cpu.icache.overall_avg_miss_latency::total 10496.353005 # average overall miss latency
545 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
546 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
547 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
548 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
549 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
550 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
551 system.cpu.icache.fast_writes 0 # number of fast writes performed
552 system.cpu.icache.cache_copies 0 # number of cache copies performed
553 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 733 # number of ReadReq MSHR hits
554 system.cpu.icache.ReadReq_mshr_hits::total 733 # number of ReadReq MSHR hits
555 system.cpu.icache.demand_mshr_hits::cpu.inst 733 # number of demand (read+write) MSHR hits
556 system.cpu.icache.demand_mshr_hits::total 733 # number of demand (read+write) MSHR hits
557 system.cpu.icache.overall_mshr_hits::cpu.inst 733 # number of overall MSHR hits
558 system.cpu.icache.overall_mshr_hits::total 733 # number of overall MSHR hits
559 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15856 # number of ReadReq MSHR misses
560 system.cpu.icache.ReadReq_mshr_misses::total 15856 # number of ReadReq MSHR misses
561 system.cpu.icache.demand_mshr_misses::cpu.inst 15856 # number of demand (read+write) MSHR misses
562 system.cpu.icache.demand_mshr_misses::total 15856 # number of demand (read+write) MSHR misses
563 system.cpu.icache.overall_mshr_misses::cpu.inst 15856 # number of overall MSHR misses
564 system.cpu.icache.overall_mshr_misses::total 15856 # number of overall MSHR misses
565 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125938500 # number of ReadReq MSHR miss cycles
566 system.cpu.icache.ReadReq_mshr_miss_latency::total 125938500 # number of ReadReq MSHR miss cycles
567 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125938500 # number of demand (read+write) MSHR miss cycles
568 system.cpu.icache.demand_mshr_miss_latency::total 125938500 # number of demand (read+write) MSHR miss cycles
569 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125938500 # number of overall MSHR miss cycles
570 system.cpu.icache.overall_mshr_miss_latency::total 125938500 # number of overall MSHR miss cycles
571 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for ReadReq accesses
572 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses
573 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for demand accesses
574 system.cpu.icache.demand_mshr_miss_rate::total 0.000401 # mshr miss rate for demand accesses
575 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for overall accesses
576 system.cpu.icache.overall_mshr_miss_rate::total 0.000401 # mshr miss rate for overall accesses
577 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7942.640010 # average ReadReq mshr miss latency
578 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7942.640010 # average ReadReq mshr miss latency
579 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency
580 system.cpu.icache.demand_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency
581 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency
582 system.cpu.icache.overall_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency
583 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
584 system.cpu.dcache.replacements 1428 # number of replacements
585 system.cpu.dcache.tagsinuse 3114.448538 # Cycle average of tags in use
586 system.cpu.dcache.total_refs 172176390 # Total number of references to valid blocks.
587 system.cpu.dcache.sampled_refs 4628 # Sample count of references to valid blocks.
588 system.cpu.dcache.avg_refs 37203.195765 # Average number of references to valid blocks.
589 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
590 system.cpu.dcache.occ_blocks::cpu.data 3114.448538 # Average occupied blocks per requestor
591 system.cpu.dcache.occ_percent::cpu.data 0.760363 # Average percentage of cache occupancy
592 system.cpu.dcache.occ_percent::total 0.760363 # Average percentage of cache occupancy
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594 system.cpu.dcache.ReadReq_hits::total 90117753 # number of ReadReq hits
595 system.cpu.dcache.WriteReq_hits::cpu.data 82031823 # number of WriteReq hits
596 system.cpu.dcache.WriteReq_hits::total 82031823 # number of WriteReq hits
597 system.cpu.dcache.LoadLockedReq_hits::cpu.data 13562 # number of LoadLockedReq hits
598 system.cpu.dcache.LoadLockedReq_hits::total 13562 # number of LoadLockedReq hits
599 system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits
600 system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits
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602 system.cpu.dcache.demand_hits::total 172149576 # number of demand (read+write) hits
603 system.cpu.dcache.overall_hits::cpu.data 172149576 # number of overall hits
604 system.cpu.dcache.overall_hits::total 172149576 # number of overall hits
605 system.cpu.dcache.ReadReq_misses::cpu.data 3920 # number of ReadReq misses
606 system.cpu.dcache.ReadReq_misses::total 3920 # number of ReadReq misses
607 system.cpu.dcache.WriteReq_misses::cpu.data 20837 # number of WriteReq misses
608 system.cpu.dcache.WriteReq_misses::total 20837 # number of WriteReq misses
609 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
610 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
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612 system.cpu.dcache.demand_misses::total 24757 # number of demand (read+write) misses
613 system.cpu.dcache.overall_misses::cpu.data 24757 # number of overall misses
614 system.cpu.dcache.overall_misses::total 24757 # number of overall misses
615 system.cpu.dcache.ReadReq_miss_latency::cpu.data 107051000 # number of ReadReq miss cycles
616 system.cpu.dcache.ReadReq_miss_latency::total 107051000 # number of ReadReq miss cycles
617 system.cpu.dcache.WriteReq_miss_latency::cpu.data 536036000 # number of WriteReq miss cycles
618 system.cpu.dcache.WriteReq_miss_latency::total 536036000 # number of WriteReq miss cycles
619 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 83000 # number of LoadLockedReq miss cycles
620 system.cpu.dcache.LoadLockedReq_miss_latency::total 83000 # number of LoadLockedReq miss cycles
621 system.cpu.dcache.demand_miss_latency::cpu.data 643087000 # number of demand (read+write) miss cycles
622 system.cpu.dcache.demand_miss_latency::total 643087000 # number of demand (read+write) miss cycles
623 system.cpu.dcache.overall_miss_latency::cpu.data 643087000 # number of overall miss cycles
624 system.cpu.dcache.overall_miss_latency::total 643087000 # number of overall miss cycles
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626 system.cpu.dcache.ReadReq_accesses::total 90121673 # number of ReadReq accesses(hits+misses)
627 system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
628 system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
629 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13564 # number of LoadLockedReq accesses(hits+misses)
630 system.cpu.dcache.LoadLockedReq_accesses::total 13564 # number of LoadLockedReq accesses(hits+misses)
631 system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses)
632 system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses)
633 system.cpu.dcache.demand_accesses::cpu.data 172174333 # number of demand (read+write) accesses
634 system.cpu.dcache.demand_accesses::total 172174333 # number of demand (read+write) accesses
635 system.cpu.dcache.overall_accesses::cpu.data 172174333 # number of overall (read+write) accesses
636 system.cpu.dcache.overall_accesses::total 172174333 # number of overall (read+write) accesses
637 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses
638 system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses
639 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000254 # miss rate for WriteReq accesses
640 system.cpu.dcache.WriteReq_miss_rate::total 0.000254 # miss rate for WriteReq accesses
641 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses
642 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses
643 system.cpu.dcache.demand_miss_rate::cpu.data 0.000144 # miss rate for demand accesses
644 system.cpu.dcache.demand_miss_rate::total 0.000144 # miss rate for demand accesses
645 system.cpu.dcache.overall_miss_rate::cpu.data 0.000144 # miss rate for overall accesses
646 system.cpu.dcache.overall_miss_rate::total 0.000144 # miss rate for overall accesses
647 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27308.928571 # average ReadReq miss latency
648 system.cpu.dcache.ReadReq_avg_miss_latency::total 27308.928571 # average ReadReq miss latency
649 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25725.200365 # average WriteReq miss latency
650 system.cpu.dcache.WriteReq_avg_miss_latency::total 25725.200365 # average WriteReq miss latency
651 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41500 # average LoadLockedReq miss latency
652 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41500 # average LoadLockedReq miss latency
653 system.cpu.dcache.demand_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency
654 system.cpu.dcache.demand_avg_miss_latency::total 25975.966393 # average overall miss latency
655 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency
656 system.cpu.dcache.overall_avg_miss_latency::total 25975.966393 # average overall miss latency
657 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
658 system.cpu.dcache.blocked_cycles::no_targets 365 # number of cycles access was blocked
659 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
660 system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
661 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
662 system.cpu.dcache.avg_blocked_cycles::no_targets 30.416667 # average number of cycles each access was blocked
663 system.cpu.dcache.fast_writes 0 # number of fast writes performed
664 system.cpu.dcache.cache_copies 0 # number of cache copies performed
665 system.cpu.dcache.writebacks::writebacks 1045 # number of writebacks
666 system.cpu.dcache.writebacks::total 1045 # number of writebacks
667 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2105 # number of ReadReq MSHR hits
668 system.cpu.dcache.ReadReq_mshr_hits::total 2105 # number of ReadReq MSHR hits
669 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18024 # number of WriteReq MSHR hits
670 system.cpu.dcache.WriteReq_mshr_hits::total 18024 # number of WriteReq MSHR hits
671 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
672 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
673 system.cpu.dcache.demand_mshr_hits::cpu.data 20129 # number of demand (read+write) MSHR hits
674 system.cpu.dcache.demand_mshr_hits::total 20129 # number of demand (read+write) MSHR hits
675 system.cpu.dcache.overall_mshr_hits::cpu.data 20129 # number of overall MSHR hits
676 system.cpu.dcache.overall_mshr_hits::total 20129 # number of overall MSHR hits
677 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1815 # number of ReadReq MSHR misses
678 system.cpu.dcache.ReadReq_mshr_misses::total 1815 # number of ReadReq MSHR misses
679 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2813 # number of WriteReq MSHR misses
680 system.cpu.dcache.WriteReq_mshr_misses::total 2813 # number of WriteReq MSHR misses
681 system.cpu.dcache.demand_mshr_misses::cpu.data 4628 # number of demand (read+write) MSHR misses
682 system.cpu.dcache.demand_mshr_misses::total 4628 # number of demand (read+write) MSHR misses
683 system.cpu.dcache.overall_mshr_misses::cpu.data 4628 # number of overall MSHR misses
684 system.cpu.dcache.overall_mshr_misses::total 4628 # number of overall MSHR misses
685 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50564500 # number of ReadReq MSHR miss cycles
686 system.cpu.dcache.ReadReq_mshr_miss_latency::total 50564500 # number of ReadReq MSHR miss cycles
687 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84395500 # number of WriteReq MSHR miss cycles
688 system.cpu.dcache.WriteReq_mshr_miss_latency::total 84395500 # number of WriteReq MSHR miss cycles
689 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 134960000 # number of demand (read+write) MSHR miss cycles
690 system.cpu.dcache.demand_mshr_miss_latency::total 134960000 # number of demand (read+write) MSHR miss cycles
691 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 134960000 # number of overall MSHR miss cycles
692 system.cpu.dcache.overall_mshr_miss_latency::total 134960000 # number of overall MSHR miss cycles
693 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
694 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
695 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
696 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
697 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
698 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
699 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
700 system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
701 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27859.228650 # average ReadReq mshr miss latency
702 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27859.228650 # average ReadReq mshr miss latency
703 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30001.955208 # average WriteReq mshr miss latency
704 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30001.955208 # average WriteReq mshr miss latency
705 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency
706 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency
707 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency
708 system.cpu.dcache.overall_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency
709 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
710 system.cpu.l2cache.replacements 0 # number of replacements
711 system.cpu.l2cache.tagsinuse 3987.642168 # Cycle average of tags in use
712 system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks.
713 system.cpu.l2cache.sampled_refs 5425 # Sample count of references to valid blocks.
714 system.cpu.l2cache.avg_refs 2.435207 # Average number of references to valid blocks.
715 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
716 system.cpu.l2cache.occ_blocks::writebacks 370.156310 # Average occupied blocks per requestor
717 system.cpu.l2cache.occ_blocks::cpu.inst 2800.588114 # Average occupied blocks per requestor
718 system.cpu.l2cache.occ_blocks::cpu.data 816.897744 # Average occupied blocks per requestor
719 system.cpu.l2cache.occ_percent::writebacks 0.011296 # Average percentage of cache occupancy
720 system.cpu.l2cache.occ_percent::cpu.inst 0.085467 # Average percentage of cache occupancy
721 system.cpu.l2cache.occ_percent::cpu.data 0.024930 # Average percentage of cache occupancy
722 system.cpu.l2cache.occ_percent::total 0.121693 # Average percentage of cache occupancy
723 system.cpu.l2cache.ReadReq_hits::cpu.inst 12793 # number of ReadReq hits
724 system.cpu.l2cache.ReadReq_hits::cpu.data 306 # number of ReadReq hits
725 system.cpu.l2cache.ReadReq_hits::total 13099 # number of ReadReq hits
726 system.cpu.l2cache.Writeback_hits::writebacks 1045 # number of Writeback hits
727 system.cpu.l2cache.Writeback_hits::total 1045 # number of Writeback hits
728 system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits
729 system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits
730 system.cpu.l2cache.demand_hits::cpu.inst 12793 # number of demand (read+write) hits
731 system.cpu.l2cache.demand_hits::cpu.data 326 # number of demand (read+write) hits
732 system.cpu.l2cache.demand_hits::total 13119 # number of demand (read+write) hits
733 system.cpu.l2cache.overall_hits::cpu.inst 12793 # number of overall hits
734 system.cpu.l2cache.overall_hits::cpu.data 326 # number of overall hits
735 system.cpu.l2cache.overall_hits::total 13119 # number of overall hits
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737 system.cpu.l2cache.ReadReq_misses::cpu.data 1508 # number of ReadReq misses
738 system.cpu.l2cache.ReadReq_misses::total 4571 # number of ReadReq misses
739 system.cpu.l2cache.ReadExReq_misses::cpu.data 2794 # number of ReadExReq misses
740 system.cpu.l2cache.ReadExReq_misses::total 2794 # number of ReadExReq misses
741 system.cpu.l2cache.demand_misses::cpu.inst 3063 # number of demand (read+write) misses
742 system.cpu.l2cache.demand_misses::cpu.data 4302 # number of demand (read+write) misses
743 system.cpu.l2cache.demand_misses::total 7365 # number of demand (read+write) misses
744 system.cpu.l2cache.overall_misses::cpu.inst 3063 # number of overall misses
745 system.cpu.l2cache.overall_misses::cpu.data 4302 # number of overall misses
746 system.cpu.l2cache.overall_misses::total 7365 # number of overall misses
747 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 97211500 # number of ReadReq miss cycles
748 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48306000 # number of ReadReq miss cycles
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751 system.cpu.l2cache.ReadExReq_miss_latency::total 81468500 # number of ReadExReq miss cycles
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754 system.cpu.l2cache.demand_miss_latency::total 226986000 # number of demand (read+write) miss cycles
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756 system.cpu.l2cache.overall_miss_latency::cpu.data 129774500 # number of overall miss cycles
757 system.cpu.l2cache.overall_miss_latency::total 226986000 # number of overall miss cycles
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759 system.cpu.l2cache.ReadReq_accesses::cpu.data 1814 # number of ReadReq accesses(hits+misses)
760 system.cpu.l2cache.ReadReq_accesses::total 17670 # number of ReadReq accesses(hits+misses)
761 system.cpu.l2cache.Writeback_accesses::writebacks 1045 # number of Writeback accesses(hits+misses)
762 system.cpu.l2cache.Writeback_accesses::total 1045 # number of Writeback accesses(hits+misses)
763 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2814 # number of ReadExReq accesses(hits+misses)
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772 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.831312 # miss rate for ReadReq accesses
773 system.cpu.l2cache.ReadReq_miss_rate::total 0.258687 # miss rate for ReadReq accesses
774 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992893 # miss rate for ReadExReq accesses
775 system.cpu.l2cache.ReadExReq_miss_rate::total 0.992893 # miss rate for ReadExReq accesses
776 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193176 # miss rate for demand accesses
777 system.cpu.l2cache.demand_miss_rate::cpu.data 0.929559 # miss rate for demand accesses
778 system.cpu.l2cache.demand_miss_rate::total 0.359549 # miss rate for demand accesses
779 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193176 # miss rate for overall accesses
780 system.cpu.l2cache.overall_miss_rate::cpu.data 0.929559 # miss rate for overall accesses
781 system.cpu.l2cache.overall_miss_rate::total 0.359549 # miss rate for overall accesses
782 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31737.349004 # average ReadReq miss latency
783 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 32033.156499 # average ReadReq miss latency
784 system.cpu.l2cache.ReadReq_avg_miss_latency::total 31834.937650 # average ReadReq miss latency
785 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 29158.375089 # average ReadExReq miss latency
786 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 29158.375089 # average ReadExReq miss latency
787 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31737.349004 # average overall miss latency
788 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 30166.085542 # average overall miss latency
789 system.cpu.l2cache.demand_avg_miss_latency::total 30819.551935 # average overall miss latency
790 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31737.349004 # average overall miss latency
791 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 30166.085542 # average overall miss latency
792 system.cpu.l2cache.overall_avg_miss_latency::total 30819.551935 # average overall miss latency
793 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
794 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
795 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
796 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
797 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
798 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
799 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
800 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
801 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits
802 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits
803 system.cpu.l2cache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
804 system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits
805 system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits
806 system.cpu.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
807 system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits
808 system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits
809 system.cpu.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits
810 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3045 # number of ReadReq MSHR misses
811 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1469 # number of ReadReq MSHR misses
812 system.cpu.l2cache.ReadReq_mshr_misses::total 4514 # number of ReadReq MSHR misses
813 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2794 # number of ReadExReq MSHR misses
814 system.cpu.l2cache.ReadExReq_mshr_misses::total 2794 # number of ReadExReq MSHR misses
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824 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72139117 # number of ReadExReq MSHR miss cycles
825 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72139117 # number of ReadExReq MSHR miss cycles
826 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85814425 # number of demand (read+write) MSHR miss cycles
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828 system.cpu.l2cache.demand_mshr_miss_latency::total 200376190 # number of demand (read+write) MSHR miss cycles
829 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85814425 # number of overall MSHR miss cycles
830 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114561765 # number of overall MSHR miss cycles
831 system.cpu.l2cache.overall_mshr_miss_latency::total 200376190 # number of overall MSHR miss cycles
832 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for ReadReq accesses
833 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809813 # mshr miss rate for ReadReq accesses
834 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255461 # mshr miss rate for ReadReq accesses
835 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992893 # mshr miss rate for ReadExReq accesses
836 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992893 # mshr miss rate for ReadExReq accesses
837 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for demand accesses
838 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for demand accesses
839 system.cpu.l2cache.demand_mshr_miss_rate::total 0.356766 # mshr miss rate for demand accesses
840 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for overall accesses
841 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for overall accesses
842 system.cpu.l2cache.overall_mshr_miss_rate::total 0.356766 # mshr miss rate for overall accesses
843 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28182.077176 # average ReadReq mshr miss latency
844 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 28878.589517 # average ReadReq mshr miss latency
845 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 28408.744572 # average ReadReq mshr miss latency
846 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 25819.297423 # average ReadExReq mshr miss latency
847 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 25819.297423 # average ReadExReq mshr miss latency
848 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency
849 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency
850 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency
851 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency
852 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency
853 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency
854 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
856 ---------- End Simulation Statistics ----------
projects / gem5.git / blob