2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.068504 # Number of seconds simulated
4 sim_ticks 68503867000 # Number of ticks simulated
5 final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 147835 # Simulator instruction rate (inst/s)
8 host_op_rate 189000 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 37091215 # Simulator tick rate (ticks/s)
10 host_mem_usage 278164 # Number of bytes of host memory used
11 host_seconds 1846.90 # Real time elapsed on the host
12 sim_insts 273036725 # Number of instructions simulated
13 sim_ops 349064449 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 466240 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory
21 system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory
24 system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s)
25 system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s)
30 system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.readReqs 7286 # Number of read requests accepted
33 system.physmem.writeReqs 0 # Number of write requests accepted
34 system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue
35 system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36 system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM
37 system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38 system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39 system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side
40 system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41 system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43 system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
44 system.physmem.perBankRdBursts::0 606 # Per bank write bursts
45 system.physmem.perBankRdBursts::1 800 # Per bank write bursts
46 system.physmem.perBankRdBursts::2 608 # Per bank write bursts
47 system.physmem.perBankRdBursts::3 526 # Per bank write bursts
48 system.physmem.perBankRdBursts::4 443 # Per bank write bursts
49 system.physmem.perBankRdBursts::5 354 # Per bank write bursts
50 system.physmem.perBankRdBursts::6 164 # Per bank write bursts
51 system.physmem.perBankRdBursts::7 219 # Per bank write bursts
52 system.physmem.perBankRdBursts::8 207 # Per bank write bursts
53 system.physmem.perBankRdBursts::9 291 # Per bank write bursts
54 system.physmem.perBankRdBursts::10 322 # Per bank write bursts
55 system.physmem.perBankRdBursts::11 415 # Per bank write bursts
56 system.physmem.perBankRdBursts::12 529 # Per bank write bursts
57 system.physmem.perBankRdBursts::13 687 # Per bank write bursts
58 system.physmem.perBankRdBursts::14 611 # Per bank write bursts
59 system.physmem.perBankRdBursts::15 504 # Per bank write bursts
60 system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61 system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62 system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63 system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64 system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65 system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66 system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67 system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68 system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69 system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70 system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71 system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72 system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73 system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74 system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75 system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78 system.physmem.totGap 68503846500 # Total gap between requests
79 system.physmem.readPktSize::0 0 # Read request sizes (log2)
80 system.physmem.readPktSize::1 0 # Read request sizes (log2)
81 system.physmem.readPktSize::2 0 # Read request sizes (log2)
82 system.physmem.readPktSize::3 0 # Read request sizes (log2)
83 system.physmem.readPktSize::4 0 # Read request sizes (log2)
84 system.physmem.readPktSize::5 0 # Read request sizes (log2)
85 system.physmem.readPktSize::6 7286 # Read request sizes (log2)
86 system.physmem.writePktSize::0 0 # Write request sizes (log2)
87 system.physmem.writePktSize::1 0 # Write request sizes (log2)
88 system.physmem.writePktSize::2 0 # Write request sizes (log2)
89 system.physmem.writePktSize::3 0 # Write request sizes (log2)
90 system.physmem.writePktSize::4 0 # Write request sizes (log2)
91 system.physmem.writePktSize::5 0 # Write request sizes (log2)
92 system.physmem.writePktSize::6 0 # Write request sizes (log2)
93 system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see
94 system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see
95 system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125 system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126 system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127 system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157 system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation
158 system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation
159 system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation
160 system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation
223 system.physmem.totQLat 62980000 # Total ticks spent queuing
224 system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM
225 system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers
226 system.physmem.totBankLat 98670000 # Total ticks spent accessing banks
227 system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst
228 system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst
229 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
230 system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst
231 system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s
232 system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
233 system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s
234 system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
235 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
236 system.physmem.busUtil 0.05 # Data bus utilization in percentage
237 system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
238 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
239 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
240 system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
241 system.physmem.readRowHits 6000 # Number of row buffer hits during reads
242 system.physmem.writeRowHits 0 # Number of row buffer hits during writes
243 system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads
244 system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
245 system.physmem.avgGap 9402120.02 # Average gap between requests
246 system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined
247 system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state
248 system.membus.throughput 6806039 # Throughput (bytes/s)
249 system.membus.trans_dist::ReadReq 4462 # Transaction distribution
250 system.membus.trans_dist::ReadResp 4461 # Transaction distribution
251 system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
252 system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
253 system.membus.trans_dist::ReadExReq 2824 # Transaction distribution
254 system.membus.trans_dist::ReadExResp 2824 # Transaction distribution
255 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes)
256 system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes)
257 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes)
258 system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes)
259 system.membus.data_through_bus 466240 # Total data (bytes)
260 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
261 system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks)
262 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
263 system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks)
264 system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
265 system.cpu_clk_domain.clock 500 # Clock period in ticks
266 system.cpu.branchPred.lookups 35407535 # Number of BP lookups
267 system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted
268 system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect
269 system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups
270 system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits
271 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
272 system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage
273 system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target.
274 system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions.
275 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
276 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
277 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
278 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
279 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
280 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
281 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
282 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
283 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
284 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
285 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
286 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
287 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
288 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
296 system.cpu.dtb.inst_hits 0 # ITB inst hits
297 system.cpu.dtb.inst_misses 0 # ITB inst misses
298 system.cpu.dtb.read_hits 0 # DTB read hits
299 system.cpu.dtb.read_misses 0 # DTB read misses
300 system.cpu.dtb.write_hits 0 # DTB write hits
301 system.cpu.dtb.write_misses 0 # DTB write misses
302 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
303 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
304 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
305 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
306 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
307 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
308 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
309 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
310 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
311 system.cpu.dtb.read_accesses 0 # DTB read accesses
312 system.cpu.dtb.write_accesses 0 # DTB write accesses
313 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
314 system.cpu.dtb.hits 0 # DTB hits
315 system.cpu.dtb.misses 0 # DTB misses
316 system.cpu.dtb.accesses 0 # DTB accesses
317 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
318 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
319 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
320 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
321 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
322 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
323 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
324 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
325 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
326 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
327 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
328 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
329 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
330 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
331 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
332 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
333 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
334 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
335 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
336 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
337 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
338 system.cpu.itb.inst_hits 0 # ITB inst hits
339 system.cpu.itb.inst_misses 0 # ITB inst misses
340 system.cpu.itb.read_hits 0 # DTB read hits
341 system.cpu.itb.read_misses 0 # DTB read misses
342 system.cpu.itb.write_hits 0 # DTB write hits
343 system.cpu.itb.write_misses 0 # DTB write misses
344 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
345 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
346 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
347 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
348 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
349 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
350 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
351 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
352 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353 system.cpu.itb.read_accesses 0 # DTB read accesses
354 system.cpu.itb.write_accesses 0 # DTB write accesses
355 system.cpu.itb.inst_accesses 0 # ITB inst accesses
356 system.cpu.itb.hits 0 # DTB hits
357 system.cpu.itb.misses 0 # DTB misses
358 system.cpu.itb.accesses 0 # DTB accesses
359 system.cpu.workload.num_syscalls 191 # Number of system calls
360 system.cpu.numCycles 137007735 # number of cpu cycles simulated
361 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
362 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
363 system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss
364 system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed
365 system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered
366 system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken
367 system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked
368 system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing
369 system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked
370 system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
371 system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps
372 system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR
373 system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched
374 system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed
375 system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
379 system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total)
380 system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total)
381 system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total)
382 system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total)
383 system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total)
384 system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total)
385 system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total)
386 system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total)
387 system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total)
388 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
389 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
390 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
391 system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total)
392 system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle
393 system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle
394 system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle
395 system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked
396 system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running
397 system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking
398 system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing
399 system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch
400 system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction
401 system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode
402 system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode
403 system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing
404 system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle
405 system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking
406 system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst
407 system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running
408 system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking
409 system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename
410 system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full
411 system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full
412 system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full
413 system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers
414 system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed
415 system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made
416 system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups
417 system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups
418 system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
419 system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing
420 system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed
421 system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed
422 system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer
423 system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit.
424 system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit.
425 system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads.
426 system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores.
427 system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec)
428 system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ
429 system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued
430 system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued
431 system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling
432 system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph
433 system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed
434 system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle
436 system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle
437 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
438 system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle
439 system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle
440 system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle
441 system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle
442 system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle
443 system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle
444 system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle
445 system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle
446 system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle
447 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
448 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
449 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
450 system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle
451 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
452 system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available
453 system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available
454 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
455 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
456 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
457 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
458 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
459 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
460 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
466 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
467 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
468 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
469 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
470 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
471 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
472 system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available
473 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
474 system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available
475 system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available
476 system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available
477 system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available
478 system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available
479 system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available
480 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available
481 system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available
482 system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available
483 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
484 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
485 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
486 system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued
487 system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued
488 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued
489 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued
490 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued
491 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued
492 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued
493 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued
494 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued
500 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued
501 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued
502 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued
503 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued
504 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued
505 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued
506 system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued
507 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued
508 system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued
509 system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued
510 system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued
511 system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued
512 system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued
513 system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued
514 system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued
515 system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued
516 system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued
517 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
518 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
519 system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued
520 system.cpu.iq.rate 2.731341 # Inst issue rate
521 system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested
522 system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst)
523 system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads
524 system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes
525 system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses
526 system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads
527 system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes
528 system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses
529 system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses
530 system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses
531 system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores
532 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
533 system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed
534 system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed
535 system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations
536 system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed
537 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
538 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
539 system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled
540 system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked
541 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
542 system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing
543 system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking
544 system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking
545 system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ
546 system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch
547 system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions
548 system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions
549 system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions
550 system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall
551 system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall
552 system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations
553 system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly
554 system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly
555 system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute
556 system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions
557 system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed
558 system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute
559 system.cpu.iew.exec_swp 0 # number of swp insts executed
560 system.cpu.iew.exec_nop 1661 # number of nop insts executed
561 system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed
562 system.cpu.iew.exec_branches 32009347 # Number of branches executed
563 system.cpu.iew.exec_stores 87218543 # Number of stores executed
564 system.cpu.iew.exec_rate 2.702456 # Inst execution rate
565 system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit
566 system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back
567 system.cpu.iew.wb_producers 183055174 # num instructions producing a value
568 system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value
569 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
570 system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle
571 system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back
572 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
573 system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit
574 system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
575 system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted
576 system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle
578 system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle
579 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
580 system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle
581 system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle
582 system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle
583 system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle
584 system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle
585 system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle
586 system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle
587 system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle
588 system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle
589 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
590 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
591 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
592 system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle
593 system.cpu.commit.committedInsts 273037337 # Number of instructions committed
594 system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
595 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
596 system.cpu.commit.refs 177024331 # Number of memory references committed
597 system.cpu.commit.loads 94648748 # Number of loads committed
598 system.cpu.commit.membars 11033 # Number of memory barriers committed
599 system.cpu.commit.branches 30563497 # Number of branches committed
600 system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
601 system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
602 system.cpu.commit.function_calls 6225112 # Number of function calls committed.
603 system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached
604 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
605 system.cpu.rob.rob_reads 501462134 # The number of ROB reads
606 system.cpu.rob.rob_writes 774278104 # The number of ROB writes
607 system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself
608 system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling
609 system.cpu.committedInsts 273036725 # Number of Instructions Simulated
610 system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
611 system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
612 system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction
613 system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads
614 system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle
615 system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads
616 system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads
617 system.cpu.int_regfile_writes 233026497 # number of integer regfile writes
618 system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads
619 system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes
620 system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads
621 system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
622 system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s)
623 system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution
624 system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution
625 system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution
626 system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
627 system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
628 system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution
629 system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution
630 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes)
631 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes)
632 system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes)
633 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes)
634 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes)
635 system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes)
636 system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes)
637 system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
638 system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks)
639 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
640 system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks)
641 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
642 system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks)
643 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
644 system.cpu.icache.tags.replacements 13947 # number of replacements
645 system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use
646 system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks.
647 system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks.
648 system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks.
649 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
650 system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor
651 system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy
652 system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy
653 system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id
654 system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
655 system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
656 system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id
657 system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
658 system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id
659 system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id
660 system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses
661 system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses
662 system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits
663 system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits
664 system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits
665 system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits
666 system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits
667 system.cpu.icache.overall_hits::total 37578823 # number of overall hits
668 system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses
669 system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses
670 system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses
671 system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses
672 system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses
673 system.cpu.icache.overall_misses::total 17320 # number of overall misses
674 system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles
675 system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles
676 system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles
677 system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles
678 system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles
679 system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles
680 system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses)
681 system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses)
682 system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses
683 system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses
684 system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses
685 system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses
686 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses
687 system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses
688 system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses
689 system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses
690 system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses
691 system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses
692 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency
693 system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency
694 system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency
695 system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency
696 system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency
697 system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency
698 system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked
699 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700 system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
701 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
702 system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked
703 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704 system.cpu.icache.fast_writes 0 # number of fast writes performed
705 system.cpu.icache.cache_copies 0 # number of cache copies performed
706 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits
707 system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits
708 system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits
709 system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits
710 system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits
711 system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits
712 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses
713 system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses
714 system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # number of demand (read+write) MSHR misses
715 system.cpu.icache.demand_mshr_misses::total 15838 # number of demand (read+write) MSHR misses
716 system.cpu.icache.overall_mshr_misses::cpu.inst 15838 # number of overall MSHR misses
717 system.cpu.icache.overall_mshr_misses::total 15838 # number of overall MSHR misses
718 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359653509 # number of ReadReq MSHR miss cycles
719 system.cpu.icache.ReadReq_mshr_miss_latency::total 359653509 # number of ReadReq MSHR miss cycles
720 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359653509 # number of demand (read+write) MSHR miss cycles
721 system.cpu.icache.demand_mshr_miss_latency::total 359653509 # number of demand (read+write) MSHR miss cycles
722 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359653509 # number of overall MSHR miss cycles
723 system.cpu.icache.overall_mshr_miss_latency::total 359653509 # number of overall MSHR miss cycles
724 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses
725 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses
726 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses
727 system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses
728 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses
729 system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses
730 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501 # average ReadReq mshr miss latency
731 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501 # average ReadReq mshr miss latency
732 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency
733 system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency
734 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency
735 system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency
736 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
737 system.cpu.l2cache.tags.replacements 0 # number of replacements
738 system.cpu.l2cache.tags.tagsinuse 3937.367139 # Cycle average of tags in use
739 system.cpu.l2cache.tags.total_refs 13183 # Total number of references to valid blocks.
740 system.cpu.l2cache.tags.sampled_refs 5383 # Sample count of references to valid blocks.
741 system.cpu.l2cache.tags.avg_refs 2.449006 # Average number of references to valid blocks.
742 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
743 system.cpu.l2cache.tags.occ_blocks::writebacks 378.211483 # Average occupied blocks per requestor
744 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2780.743240 # Average occupied blocks per requestor
745 system.cpu.l2cache.tags.occ_blocks::cpu.data 778.412416 # Average occupied blocks per requestor
746 system.cpu.l2cache.tags.occ_percent::writebacks 0.011542 # Average percentage of cache occupancy
747 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084862 # Average percentage of cache occupancy
748 system.cpu.l2cache.tags.occ_percent::cpu.data 0.023755 # Average percentage of cache occupancy
749 system.cpu.l2cache.tags.occ_percent::total 0.120159 # Average percentage of cache occupancy
750 system.cpu.l2cache.tags.occ_task_id_blocks::1024 5383 # Occupied blocks per task id
751 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
752 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
753 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1236 # Occupied blocks per task id
754 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
755 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4007 # Occupied blocks per task id
756 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164276 # Percentage of cache occupancy per task id
757 system.cpu.l2cache.tags.tag_accesses 180072 # Number of tag accesses
758 system.cpu.l2cache.tags.data_accesses 180072 # Number of data accesses
759 system.cpu.l2cache.ReadReq_hits::cpu.inst 12790 # number of ReadReq hits
760 system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits
761 system.cpu.l2cache.ReadReq_hits::total 13089 # number of ReadReq hits
762 system.cpu.l2cache.Writeback_hits::writebacks 1035 # number of Writeback hits
763 system.cpu.l2cache.Writeback_hits::total 1035 # number of Writeback hits
764 system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
765 system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
766 system.cpu.l2cache.demand_hits::cpu.inst 12790 # number of demand (read+write) hits
767 system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits
768 system.cpu.l2cache.demand_hits::total 13106 # number of demand (read+write) hits
769 system.cpu.l2cache.overall_hits::cpu.inst 12790 # number of overall hits
770 system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits
771 system.cpu.l2cache.overall_hits::total 13106 # number of overall hits
772 system.cpu.l2cache.ReadReq_misses::cpu.inst 3044 # number of ReadReq misses
773 system.cpu.l2cache.ReadReq_misses::cpu.data 1470 # number of ReadReq misses
774 system.cpu.l2cache.ReadReq_misses::total 4514 # number of ReadReq misses
775 system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
776 system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
777 system.cpu.l2cache.ReadExReq_misses::cpu.data 2824 # number of ReadExReq misses
778 system.cpu.l2cache.ReadExReq_misses::total 2824 # number of ReadExReq misses
779 system.cpu.l2cache.demand_misses::cpu.inst 3044 # number of demand (read+write) misses
780 system.cpu.l2cache.demand_misses::cpu.data 4294 # number of demand (read+write) misses
781 system.cpu.l2cache.demand_misses::total 7338 # number of demand (read+write) misses
782 system.cpu.l2cache.overall_misses::cpu.inst 3044 # number of overall misses
783 system.cpu.l2cache.overall_misses::cpu.data 4294 # number of overall misses
784 system.cpu.l2cache.overall_misses::total 7338 # number of overall misses
785 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215877500 # number of ReadReq miss cycles
786 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 110553500 # number of ReadReq miss cycles
787 system.cpu.l2cache.ReadReq_miss_latency::total 326431000 # number of ReadReq miss cycles
788 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 198942750 # number of ReadExReq miss cycles
789 system.cpu.l2cache.ReadExReq_miss_latency::total 198942750 # number of ReadExReq miss cycles
790 system.cpu.l2cache.demand_miss_latency::cpu.inst 215877500 # number of demand (read+write) miss cycles
791 system.cpu.l2cache.demand_miss_latency::cpu.data 309496250 # number of demand (read+write) miss cycles
792 system.cpu.l2cache.demand_miss_latency::total 525373750 # number of demand (read+write) miss cycles
793 system.cpu.l2cache.overall_miss_latency::cpu.inst 215877500 # number of overall miss cycles
794 system.cpu.l2cache.overall_miss_latency::cpu.data 309496250 # number of overall miss cycles
795 system.cpu.l2cache.overall_miss_latency::total 525373750 # number of overall miss cycles
796 system.cpu.l2cache.ReadReq_accesses::cpu.inst 15834 # number of ReadReq accesses(hits+misses)
797 system.cpu.l2cache.ReadReq_accesses::cpu.data 1769 # number of ReadReq accesses(hits+misses)
798 system.cpu.l2cache.ReadReq_accesses::total 17603 # number of ReadReq accesses(hits+misses)
799 system.cpu.l2cache.Writeback_accesses::writebacks 1035 # number of Writeback accesses(hits+misses)
800 system.cpu.l2cache.Writeback_accesses::total 1035 # number of Writeback accesses(hits+misses)
801 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
802 system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
803 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2841 # number of ReadExReq accesses(hits+misses)
804 system.cpu.l2cache.ReadExReq_accesses::total 2841 # number of ReadExReq accesses(hits+misses)
805 system.cpu.l2cache.demand_accesses::cpu.inst 15834 # number of demand (read+write) accesses
806 system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses
807 system.cpu.l2cache.demand_accesses::total 20444 # number of demand (read+write) accesses
808 system.cpu.l2cache.overall_accesses::cpu.inst 15834 # number of overall (read+write) accesses
809 system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses
810 system.cpu.l2cache.overall_accesses::total 20444 # number of overall (read+write) accesses
811 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192245 # miss rate for ReadReq accesses
812 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830978 # miss rate for ReadReq accesses
813 system.cpu.l2cache.ReadReq_miss_rate::total 0.256434 # miss rate for ReadReq accesses
814 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
815 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
816 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994016 # miss rate for ReadExReq accesses
817 system.cpu.l2cache.ReadExReq_miss_rate::total 0.994016 # miss rate for ReadExReq accesses
818 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192245 # miss rate for demand accesses
819 system.cpu.l2cache.demand_miss_rate::cpu.data 0.931453 # miss rate for demand accesses
820 system.cpu.l2cache.demand_miss_rate::total 0.358932 # miss rate for demand accesses
821 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192245 # miss rate for overall accesses
822 system.cpu.l2cache.overall_miss_rate::cpu.data 0.931453 # miss rate for overall accesses
823 system.cpu.l2cache.overall_miss_rate::total 0.358932 # miss rate for overall accesses
824 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70919.021025 # average ReadReq miss latency
825 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75206.462585 # average ReadReq miss latency
826 system.cpu.l2cache.ReadReq_avg_miss_latency::total 72315.241471 # average ReadReq miss latency
827 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70447.149433 # average ReadExReq miss latency
828 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70447.149433 # average ReadExReq miss latency
829 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70919.021025 # average overall miss latency
830 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72076.443875 # average overall miss latency
831 system.cpu.l2cache.demand_avg_miss_latency::total 71596.313709 # average overall miss latency
832 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70919.021025 # average overall miss latency
833 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72076.443875 # average overall miss latency
834 system.cpu.l2cache.overall_avg_miss_latency::total 71596.313709 # average overall miss latency
835 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
838 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
839 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
842 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
843 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
844 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
845 system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
846 system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
847 system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
848 system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
849 system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
850 system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
851 system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
852 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3032 # number of ReadReq MSHR misses
853 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1430 # number of ReadReq MSHR misses
854 system.cpu.l2cache.ReadReq_mshr_misses::total 4462 # number of ReadReq MSHR misses
855 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
856 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
857 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2824 # number of ReadExReq MSHR misses
858 system.cpu.l2cache.ReadExReq_mshr_misses::total 2824 # number of ReadExReq MSHR misses
859 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3032 # number of demand (read+write) MSHR misses
860 system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # number of demand (read+write) MSHR misses
861 system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses
862 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3032 # number of overall MSHR misses
863 system.cpu.l2cache.overall_mshr_misses::cpu.data 4254 # number of overall MSHR misses
864 system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses
865 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 177153750 # number of ReadReq MSHR miss cycles
866 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 90029000 # number of ReadReq MSHR miss cycles
867 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267182750 # number of ReadReq MSHR miss cycles
868 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
869 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
870 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164034250 # number of ReadExReq MSHR miss cycles
871 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164034250 # number of ReadExReq MSHR miss cycles
872 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 177153750 # number of demand (read+write) MSHR miss cycles
873 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254063250 # number of demand (read+write) MSHR miss cycles
874 system.cpu.l2cache.demand_mshr_miss_latency::total 431217000 # number of demand (read+write) MSHR miss cycles
875 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 177153750 # number of overall MSHR miss cycles
876 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254063250 # number of overall MSHR miss cycles
877 system.cpu.l2cache.overall_mshr_miss_latency::total 431217000 # number of overall MSHR miss cycles
878 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for ReadReq accesses
879 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808366 # mshr miss rate for ReadReq accesses
880 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253480 # mshr miss rate for ReadReq accesses
881 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
882 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
883 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994016 # mshr miss rate for ReadExReq accesses
884 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994016 # mshr miss rate for ReadExReq accesses
885 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for demand accesses
886 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for demand accesses
887 system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses
888 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for overall accesses
889 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for overall accesses
890 system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses
891 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810 # average ReadReq mshr miss latency
892 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency
893 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency
894 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
895 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
896 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578 # average ReadExReq mshr miss latency
897 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578 # average ReadExReq mshr miss latency
898 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency
899 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency
900 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency
901 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency
902 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency
903 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency
904 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
905 system.cpu.dcache.tags.replacements 1413 # number of replacements
906 system.cpu.dcache.tags.tagsinuse 3103.986618 # Cycle average of tags in use
907 system.cpu.dcache.tags.total_refs 170973728 # Total number of references to valid blocks.
908 system.cpu.dcache.tags.sampled_refs 4610 # Sample count of references to valid blocks.
909 system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks.
910 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
911 system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor
912 system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy
913 system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy
914 system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id
915 system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
916 system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
917 system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id
918 system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
919 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id
920 system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id
921 system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses
922 system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses
923 system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits
924 system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits
925 system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits
926 system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits
927 system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits
928 system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits
929 system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
930 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
931 system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits
932 system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits
933 system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits
934 system.cpu.dcache.overall_hits::total 170951801 # number of overall hits
935 system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses
936 system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses
937 system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses
938 system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses
939 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
940 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
941 system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses
942 system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses
943 system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses
944 system.cpu.dcache.overall_misses::total 25020 # number of overall misses
945 system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles
946 system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles
947 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles
948 system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles
949 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
950 system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
951 system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles
952 system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles
953 system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles
954 system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles
955 system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses)
956 system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses)
957 system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
958 system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
959 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses)
960 system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses)
961 system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
962 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
963 system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses
964 system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses
965 system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses
966 system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses
967 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses
968 system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses
969 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
970 system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
971 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses
972 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses
973 system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses
974 system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses
975 system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses
976 system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses
977 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency
978 system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency
979 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency
980 system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency
981 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
982 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
983 system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency
984 system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency
985 system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency
986 system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency
987 system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked
988 system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked
989 system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked
990 system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
991 system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked
992 system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked
993 system.cpu.dcache.fast_writes 0 # number of fast writes performed
994 system.cpu.dcache.cache_copies 0 # number of cache copies performed
995 system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks
996 system.cpu.dcache.writebacks::total 1035 # number of writebacks
997 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits
998 system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits
999 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits
1000 system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits
1001 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
1002 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
1003 system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits
1004 system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits
1005 system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits
1006 system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits
1007 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses
1008 system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses
1009 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses
1010 system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses
1011 system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses
1012 system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses
1013 system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses
1014 system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses
1015 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles
1016 system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles
1017 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles
1018 system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles
1019 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles
1020 system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles
1021 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles
1022 system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles
1023 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
1024 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
1025 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
1026 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
1027 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
1028 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
1029 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
1030 system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
1031 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency
1032 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency
1033 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency
1034 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency
1035 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency
1036 system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency
1037 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency
1038 system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency
1039 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1041 ---------- End Simulation Statistics ----------
projects / gem5.git / blob