2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.517298 # Number of seconds simulated
4 sim_ticks 517297855500 # Number of ticks simulated
5 final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1075622 # Simulator instruction rate (inst/s)
8 host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2040106124 # Simulator tick rate (ticks/s)
10 host_mem_usage 278152 # Number of bytes of host memory used
11 host_seconds 253.56 # Real time elapsed on the host
12 sim_insts 272739286 # Number of instructions simulated
13 sim_ops 327433744 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
22 system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
23 system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
24 system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
25 system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s)
26 system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s)
31 system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s)
32 system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s)
33 system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
34 system.cpu_clk_domain.clock 500 # Clock period in ticks
35 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
36 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
44 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
45 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
46 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
47 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
48 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
49 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
50 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
51 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
55 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
56 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
57 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
65 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
66 system.cpu.dtb.walker.walks 0 # Table walker walks requested
67 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
74 system.cpu.dtb.inst_hits 0 # ITB inst hits
75 system.cpu.dtb.inst_misses 0 # ITB inst misses
76 system.cpu.dtb.read_hits 0 # DTB read hits
77 system.cpu.dtb.read_misses 0 # DTB read misses
78 system.cpu.dtb.write_hits 0 # DTB write hits
79 system.cpu.dtb.write_misses 0 # DTB write misses
80 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
81 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
82 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
83 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
84 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
85 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
86 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
87 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89 system.cpu.dtb.read_accesses 0 # DTB read accesses
90 system.cpu.dtb.write_accesses 0 # DTB write accesses
91 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92 system.cpu.dtb.hits 0 # DTB hits
93 system.cpu.dtb.misses 0 # DTB misses
94 system.cpu.dtb.accesses 0 # DTB accesses
95 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
96 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
104 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
105 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
106 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
107 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
108 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
109 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
110 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
111 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
112 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
113 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
114 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
115 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
116 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
117 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
125 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
126 system.cpu.itb.walker.walks 0 # Table walker walks requested
127 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134 system.cpu.itb.inst_hits 0 # ITB inst hits
135 system.cpu.itb.inst_misses 0 # ITB inst misses
136 system.cpu.itb.read_hits 0 # DTB read hits
137 system.cpu.itb.read_misses 0 # DTB read misses
138 system.cpu.itb.write_hits 0 # DTB write hits
139 system.cpu.itb.write_misses 0 # DTB write misses
140 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
141 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149 system.cpu.itb.read_accesses 0 # DTB read accesses
150 system.cpu.itb.write_accesses 0 # DTB write accesses
151 system.cpu.itb.inst_accesses 0 # ITB inst accesses
152 system.cpu.itb.hits 0 # DTB hits
153 system.cpu.itb.misses 0 # DTB misses
154 system.cpu.itb.accesses 0 # DTB accesses
155 system.cpu.workload.numSyscalls 191 # Number of system calls
156 system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states
157 system.cpu.numCycles 1034595711 # number of cpu cycles simulated
158 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160 system.cpu.committedInsts 272739286 # Number of instructions committed
161 system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
162 system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
163 system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
164 system.cpu.num_func_calls 12448615 # number of times a function call or return occured
165 system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
166 system.cpu.num_int_insts 258331537 # number of integer instructions
167 system.cpu.num_fp_insts 114216705 # number of float instructions
168 system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read
169 system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
170 system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
171 system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
172 system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
173 system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
174 system.cpu.num_mem_refs 168107847 # number of memory refs
175 system.cpu.num_load_insts 85732248 # Number of load instructions
176 system.cpu.num_store_insts 82375599 # Number of store instructions
177 system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
178 system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles
179 system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180 system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181 system.cpu.Branches 30563503 # Number of branches fetched
182 system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183 system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
184 system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
185 system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
186 system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
187 system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
188 system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
189 system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
190 system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction
191 system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
192 system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction
193 system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
194 system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
195 system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
196 system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
197 system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
198 system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
199 system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
200 system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
201 system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
202 system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
203 system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
204 system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
205 system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
206 system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
207 system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
208 system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
209 system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
210 system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
211 system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
212 system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
213 system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
214 system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction
215 system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction
216 system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction
217 system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction
218 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
219 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
220 system.cpu.op_class::total 327812214 # Class of executed instruction
221 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
222 system.cpu.dcache.tags.replacements 1332 # number of replacements
223 system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use
224 system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
225 system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
226 system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
227 system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
228 system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor
229 system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy
230 system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy
231 system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
232 system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
233 system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
234 system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
235 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
236 system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
237 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
238 system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
239 system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
240 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
241 system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
242 system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
243 system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
244 system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
245 system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
246 system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
247 system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
248 system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
249 system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
250 system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
251 system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
252 system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
253 system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
254 system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
255 system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
256 system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
257 system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
258 system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
259 system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
260 system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
261 system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
262 system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
263 system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
264 system.cpu.dcache.overall_misses::total 4479 # number of overall misses
265 system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles
266 system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles
267 system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles
268 system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles
269 system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles
270 system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles
271 system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles
272 system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles
273 system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
274 system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
275 system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
276 system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
277 system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
278 system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
279 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
280 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
281 system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
282 system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
283 system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
284 system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
285 system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
286 system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
287 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
288 system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
289 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
290 system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
291 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
292 system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
293 system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
294 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
295 system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
296 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
297 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency
298 system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency
299 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency
300 system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency
301 system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency
302 system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency
303 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency
304 system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency
305 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
306 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
307 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
308 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
309 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
310 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
311 system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
312 system.cpu.dcache.writebacks::total 998 # number of writebacks
313 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
314 system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
315 system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
316 system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
317 system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
318 system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
319 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
320 system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
321 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
322 system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
323 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
324 system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
325 system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
326 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
327 system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
328 system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
329 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles
330 system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles
331 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles
332 system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles
333 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles
334 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles
335 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles
336 system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles
337 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles
338 system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles
339 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
340 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
341 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
342 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
343 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
344 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
345 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
346 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
347 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
348 system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
349 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency
350 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency
351 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency
352 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency
353 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
354 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
355 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency
356 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency
357 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency
358 system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency
359 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
360 system.cpu.icache.tags.replacements 13796 # number of replacements
361 system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use
362 system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
363 system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
364 system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
365 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
366 system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor
367 system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy
368 system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy
369 system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
370 system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
371 system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
372 system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
373 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
374 system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
375 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
376 system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
377 system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
378 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
379 system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
380 system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
381 system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
382 system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
383 system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
384 system.cpu.icache.overall_hits::total 348644750 # number of overall hits
385 system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
386 system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
387 system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
388 system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
389 system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
390 system.cpu.icache.overall_misses::total 15603 # number of overall misses
391 system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles
392 system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles
393 system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles
394 system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles
395 system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles
396 system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles
397 system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
398 system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
399 system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
400 system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
401 system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
402 system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
403 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
404 system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
405 system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
406 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
407 system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
408 system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
409 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency
410 system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency
411 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
412 system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency
413 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
414 system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency
415 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
418 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
419 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421 system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
422 system.cpu.icache.writebacks::total 13796 # number of writebacks
423 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
424 system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
425 system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
426 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
427 system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
428 system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
429 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles
430 system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles
431 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles
432 system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles
433 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles
434 system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles
435 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
436 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
437 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
438 system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
439 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
440 system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
441 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency
442 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency
443 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
444 system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
445 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
446 system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
447 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
448 system.cpu.l2cache.tags.replacements 0 # number of replacements
449 system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use
450 system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks.
451 system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks.
452 system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks.
453 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
454 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor
455 system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor
456 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy
457 system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy
458 system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy
459 system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id
460 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
461 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
462 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
463 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id
464 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id
465 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id
466 system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses
467 system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses
468 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
469 system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
470 system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
471 system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
472 system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
473 system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
474 system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
475 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
476 system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
477 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
478 system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
479 system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
480 system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
481 system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
482 system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
483 system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
484 system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
485 system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
486 system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
487 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
488 system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
489 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
490 system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
491 system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses
492 system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses
493 system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
494 system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
495 system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
496 system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
497 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles
498 system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles
499 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles
500 system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles
501 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles
502 system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles
503 system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles
504 system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles
505 system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles
506 system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles
507 system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles
508 system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles
509 system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
510 system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
511 system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
512 system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
513 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
514 system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
515 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
516 system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
517 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
518 system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
519 system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
520 system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
521 system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
522 system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
523 system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
524 system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
525 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
526 system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
527 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
528 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
529 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
530 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
531 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
532 system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
533 system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
534 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
535 system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
536 system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
537 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency
538 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency
539 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency
540 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency
541 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency
542 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency
543 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
544 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
545 system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency
546 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
547 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
548 system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency
549 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
552 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
553 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
556 system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
557 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
558 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
559 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
560 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
561 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
562 system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
563 system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
564 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
565 system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
566 system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
567 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles
568 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles
569 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles
570 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles
571 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles
572 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles
573 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles
574 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles
575 system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles
576 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles
577 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles
578 system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles
579 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
580 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
581 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
582 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
583 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
584 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
585 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
586 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
587 system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
588 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
589 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
590 system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
591 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency
592 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency
593 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency
594 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency
595 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency
596 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency
597 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
598 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
599 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
600 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
601 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
602 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
603 system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
604 system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
605 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
606 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
607 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
608 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
609 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
610 system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
611 system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
612 system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
613 system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
614 system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
615 system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
616 system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
617 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
618 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
619 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
620 system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
621 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
622 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
623 system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
624 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
625 system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
626 system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
627 system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
628 system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
629 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
630 system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
631 system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
632 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
633 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
634 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
635 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
636 system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
637 system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
638 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
639 system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
640 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
641 system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
642 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
643 system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter.
644 system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
645 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
646 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
647 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
648 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
649 system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
650 system.membus.trans_dist::ReadResp 3976 # Transaction distribution
651 system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
652 system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
653 system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
654 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
655 system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
656 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
657 system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
658 system.membus.snoops 0 # Total snoops (count)
659 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
660 system.membus.snoop_fanout::samples 6833 # Request fanout histogram
661 system.membus.snoop_fanout::mean 0 # Request fanout histogram
662 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
663 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
664 system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
665 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
666 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
667 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
668 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
669 system.membus.snoop_fanout::total 6833 # Request fanout histogram
670 system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
671 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
672 system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
673 system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
675 ---------- End Simulation Statistics ----------
projects / gem5.git / blob