tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 load_offset=0
  22 mem_mode=timing
  23 mem_ranges=
  24 memories=system.physmem
  25 num_work_ids=16
  26 readfile=
  27 symbolfile=
  28 work_begin_ckpt_count=0
  29 work_begin_cpu_id_exit=-1
  30 work_begin_exit_count=0
  31 work_cpus_ckpt_count=0
  32 work_end_ckpt_count=0
  33 work_end_exit_count=0
  34 work_item_id=-1
  35 system_port=system.membus.slave[0]
  36
  37 [system.clk_domain]
  38 type=SrcClockDomain
  39 clock=1000
  40 domain_id=-1
  41 eventq_index=0
  42 init_perf_level=0
  43 voltage_domain=system.voltage_domain
  44
  45 [system.cpu]
  46 type=DerivO3CPU
  47 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  48 LFSTSize=1024
  49 LQEntries=32
  50 LSQCheckLoads=true
  51 LSQDepCheckShift=4
  52 SQEntries=32
  53 SSITSize=1024
  54 activity=0
  55 backComSize=5
  56 branchPred=system.cpu.branchPred
  57 cachePorts=200
  58 checker=Null
  59 clk_domain=system.cpu_clk_domain
  60 commitToDecodeDelay=1
  61 commitToFetchDelay=1
  62 commitToIEWDelay=1
  63 commitToRenameDelay=1
  64 commitWidth=8
  65 cpu_id=0
  66 decodeToFetchDelay=1
  67 decodeToRenameDelay=1
  68 decodeWidth=8
  69 dispatchWidth=8
  70 do_checkpoint_insts=true
  71 do_quiesce=true
  72 do_statistics_insts=true
  73 dtb=system.cpu.dtb
  74 eventq_index=0
  75 fetchBufferSize=64
  76 fetchToDecodeDelay=1
  77 fetchTrapLatency=1
  78 fetchWidth=8
  79 forwardComSize=5
  80 fuPool=system.cpu.fuPool
  81 function_trace=false
  82 function_trace_start=0
  83 iewToCommitDelay=1
  84 iewToDecodeDelay=1
  85 iewToFetchDelay=1
  86 iewToRenameDelay=1
  87 interrupts=system.cpu.interrupts
  88 isa=system.cpu.isa
  89 issueToExecuteDelay=1
  90 issueWidth=8
  91 itb=system.cpu.itb
  92 max_insts_all_threads=0
  93 max_insts_any_thread=0
  94 max_loads_all_threads=0
  95 max_loads_any_thread=0
  96 needsTSO=false
  97 numIQEntries=64
  98 numPhysCCRegs=0
  99 numPhysFloatRegs=256
 100 numPhysIntRegs=256
 101 numROBEntries=192
 102 numRobs=1
 103 numThreads=1
 104 profile=0
 105 progress_interval=0
 106 renameToDecodeDelay=1
 107 renameToFetchDelay=1
 108 renameToIEWDelay=2
 109 renameToROBDelay=1
 110 renameWidth=8
 111 simpoint_start_insts=
 112 smtCommitPolicy=RoundRobin
 113 smtFetchPolicy=SingleThread
 114 smtIQPolicy=Partitioned
 115 smtIQThreshold=100
 116 smtLSQPolicy=Partitioned
 117 smtLSQThreshold=100
 118 smtNumFetchingThreads=1
 119 smtROBPolicy=Partitioned
 120 smtROBThreshold=100
 121 socket_id=0
 122 squashWidth=8
 123 store_set_clear_period=250000
 124 switched_out=false
 125 system=system
 126 tracer=system.cpu.tracer
 127 trapLatency=13
 128 wbDepth=1
 129 wbWidth=8
 130 workload=system.cpu.workload
 131 dcache_port=system.cpu.dcache.cpu_side
 132 icache_port=system.cpu.icache.cpu_side
 133
 134 [system.cpu.branchPred]
 135 type=BranchPredictor
 136 BTBEntries=4096
 137 BTBTagSize=16
 138 RASSize=16
 139 choiceCtrBits=2
 140 choicePredictorSize=8192
 141 eventq_index=0
 142 globalCtrBits=2
 143 globalPredictorSize=8192
 144 instShiftAmt=2
 145 localCtrBits=2
 146 localHistoryTableSize=2048
 147 localPredictorSize=2048
 148 numThreads=1
 149 predType=tournament
 150
 151 [system.cpu.dcache]
 152 type=BaseCache
 153 children=tags
 154 addr_ranges=0:18446744073709551615
 155 assoc=2
 156 clk_domain=system.cpu_clk_domain
 157 eventq_index=0
 158 forward_snoops=true
 159 hit_latency=2
 160 is_top_level=true
 161 max_miss_count=0
 162 mshrs=4
 163 prefetch_on_access=false
 164 prefetcher=Null
 165 response_latency=2
 166 sequential_access=false
 167 size=262144
 168 system=system
 169 tags=system.cpu.dcache.tags
 170 tgts_per_mshr=20
 171 two_queue=false
 172 write_buffers=8
 173 cpu_side=system.cpu.dcache_port
 174 mem_side=system.cpu.toL2Bus.slave[1]
 175
 176 [system.cpu.dcache.tags]
 177 type=LRU
 178 assoc=2
 179 block_size=64
 180 clk_domain=system.cpu_clk_domain
 181 eventq_index=0
 182 hit_latency=2
 183 sequential_access=false
 184 size=262144
 185
 186 [system.cpu.dtb]
 187 type=AlphaTLB
 188 eventq_index=0
 189 size=64
 190
 191 [system.cpu.fuPool]
 192 type=FUPool
 193 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 194 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 195 eventq_index=0
 196
 197 [system.cpu.fuPool.FUList0]
 198 type=FUDesc
 199 children=opList
 200 count=6
 201 eventq_index=0
 202 opList=system.cpu.fuPool.FUList0.opList
 203
 204 [system.cpu.fuPool.FUList0.opList]
 205 type=OpDesc
 206 eventq_index=0
 207 issueLat=1
 208 opClass=IntAlu
 209 opLat=1
 210
 211 [system.cpu.fuPool.FUList1]
 212 type=FUDesc
 213 children=opList0 opList1
 214 count=2
 215 eventq_index=0
 216 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 217
 218 [system.cpu.fuPool.FUList1.opList0]
 219 type=OpDesc
 220 eventq_index=0
 221 issueLat=1
 222 opClass=IntMult
 223 opLat=3
 224
 225 [system.cpu.fuPool.FUList1.opList1]
 226 type=OpDesc
 227 eventq_index=0
 228 issueLat=19
 229 opClass=IntDiv
 230 opLat=20
 231
 232 [system.cpu.fuPool.FUList2]
 233 type=FUDesc
 234 children=opList0 opList1 opList2
 235 count=4
 236 eventq_index=0
 237 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 238
 239 [system.cpu.fuPool.FUList2.opList0]
 240 type=OpDesc
 241 eventq_index=0
 242 issueLat=1
 243 opClass=FloatAdd
 244 opLat=2
 245
 246 [system.cpu.fuPool.FUList2.opList1]
 247 type=OpDesc
 248 eventq_index=0
 249 issueLat=1
 250 opClass=FloatCmp
 251 opLat=2
 252
 253 [system.cpu.fuPool.FUList2.opList2]
 254 type=OpDesc
 255 eventq_index=0
 256 issueLat=1
 257 opClass=FloatCvt
 258 opLat=2
 259
 260 [system.cpu.fuPool.FUList3]
 261 type=FUDesc
 262 children=opList0 opList1 opList2
 263 count=2
 264 eventq_index=0
 265 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 266
 267 [system.cpu.fuPool.FUList3.opList0]
 268 type=OpDesc
 269 eventq_index=0
 270 issueLat=1
 271 opClass=FloatMult
 272 opLat=4
 273
 274 [system.cpu.fuPool.FUList3.opList1]
 275 type=OpDesc
 276 eventq_index=0
 277 issueLat=12
 278 opClass=FloatDiv
 279 opLat=12
 280
 281 [system.cpu.fuPool.FUList3.opList2]
 282 type=OpDesc
 283 eventq_index=0
 284 issueLat=24
 285 opClass=FloatSqrt
 286 opLat=24
 287
 288 [system.cpu.fuPool.FUList4]
 289 type=FUDesc
 290 children=opList
 291 count=0
 292 eventq_index=0
 293 opList=system.cpu.fuPool.FUList4.opList
 294
 295 [system.cpu.fuPool.FUList4.opList]
 296 type=OpDesc
 297 eventq_index=0
 298 issueLat=1
 299 opClass=MemRead
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5]
 303 type=FUDesc
 304 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 305 count=4
 306 eventq_index=0
 307 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 308
 309 [system.cpu.fuPool.FUList5.opList00]
 310 type=OpDesc
 311 eventq_index=0
 312 issueLat=1
 313 opClass=SimdAdd
 314 opLat=1
 315
 316 [system.cpu.fuPool.FUList5.opList01]
 317 type=OpDesc
 318 eventq_index=0
 319 issueLat=1
 320 opClass=SimdAddAcc
 321 opLat=1
 322
 323 [system.cpu.fuPool.FUList5.opList02]
 324 type=OpDesc
 325 eventq_index=0
 326 issueLat=1
 327 opClass=SimdAlu
 328 opLat=1
 329
 330 [system.cpu.fuPool.FUList5.opList03]
 331 type=OpDesc
 332 eventq_index=0
 333 issueLat=1
 334 opClass=SimdCmp
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList04]
 338 type=OpDesc
 339 eventq_index=0
 340 issueLat=1
 341 opClass=SimdCvt
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList05]
 345 type=OpDesc
 346 eventq_index=0
 347 issueLat=1
 348 opClass=SimdMisc
 349 opLat=1
 350
 351 [system.cpu.fuPool.FUList5.opList06]
 352 type=OpDesc
 353 eventq_index=0
 354 issueLat=1
 355 opClass=SimdMult
 356 opLat=1
 357
 358 [system.cpu.fuPool.FUList5.opList07]
 359 type=OpDesc
 360 eventq_index=0
 361 issueLat=1
 362 opClass=SimdMultAcc
 363 opLat=1
 364
 365 [system.cpu.fuPool.FUList5.opList08]
 366 type=OpDesc
 367 eventq_index=0
 368 issueLat=1
 369 opClass=SimdShift
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList5.opList09]
 373 type=OpDesc
 374 eventq_index=0
 375 issueLat=1
 376 opClass=SimdShiftAcc
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList10]
 380 type=OpDesc
 381 eventq_index=0
 382 issueLat=1
 383 opClass=SimdSqrt
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList5.opList11]
 387 type=OpDesc
 388 eventq_index=0
 389 issueLat=1
 390 opClass=SimdFloatAdd
 391 opLat=1
 392
 393 [system.cpu.fuPool.FUList5.opList12]
 394 type=OpDesc
 395 eventq_index=0
 396 issueLat=1
 397 opClass=SimdFloatAlu
 398 opLat=1
 399
 400 [system.cpu.fuPool.FUList5.opList13]
 401 type=OpDesc
 402 eventq_index=0
 403 issueLat=1
 404 opClass=SimdFloatCmp
 405 opLat=1
 406
 407 [system.cpu.fuPool.FUList5.opList14]
 408 type=OpDesc
 409 eventq_index=0
 410 issueLat=1
 411 opClass=SimdFloatCvt
 412 opLat=1
 413
 414 [system.cpu.fuPool.FUList5.opList15]
 415 type=OpDesc
 416 eventq_index=0
 417 issueLat=1
 418 opClass=SimdFloatDiv
 419 opLat=1
 420
 421 [system.cpu.fuPool.FUList5.opList16]
 422 type=OpDesc
 423 eventq_index=0
 424 issueLat=1
 425 opClass=SimdFloatMisc
 426 opLat=1
 427
 428 [system.cpu.fuPool.FUList5.opList17]
 429 type=OpDesc
 430 eventq_index=0
 431 issueLat=1
 432 opClass=SimdFloatMult
 433 opLat=1
 434
 435 [system.cpu.fuPool.FUList5.opList18]
 436 type=OpDesc
 437 eventq_index=0
 438 issueLat=1
 439 opClass=SimdFloatMultAcc
 440 opLat=1
 441
 442 [system.cpu.fuPool.FUList5.opList19]
 443 type=OpDesc
 444 eventq_index=0
 445 issueLat=1
 446 opClass=SimdFloatSqrt
 447 opLat=1
 448
 449 [system.cpu.fuPool.FUList6]
 450 type=FUDesc
 451 children=opList
 452 count=0
 453 eventq_index=0
 454 opList=system.cpu.fuPool.FUList6.opList
 455
 456 [system.cpu.fuPool.FUList6.opList]
 457 type=OpDesc
 458 eventq_index=0
 459 issueLat=1
 460 opClass=MemWrite
 461 opLat=1
 462
 463 [system.cpu.fuPool.FUList7]
 464 type=FUDesc
 465 children=opList0 opList1
 466 count=4
 467 eventq_index=0
 468 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 469
 470 [system.cpu.fuPool.FUList7.opList0]
 471 type=OpDesc
 472 eventq_index=0
 473 issueLat=1
 474 opClass=MemRead
 475 opLat=1
 476
 477 [system.cpu.fuPool.FUList7.opList1]
 478 type=OpDesc
 479 eventq_index=0
 480 issueLat=1
 481 opClass=MemWrite
 482 opLat=1
 483
 484 [system.cpu.fuPool.FUList8]
 485 type=FUDesc
 486 children=opList
 487 count=1
 488 eventq_index=0
 489 opList=system.cpu.fuPool.FUList8.opList
 490
 491 [system.cpu.fuPool.FUList8.opList]
 492 type=OpDesc
 493 eventq_index=0
 494 issueLat=3
 495 opClass=IprAccess
 496 opLat=3
 497
 498 [system.cpu.icache]
 499 type=BaseCache
 500 children=tags
 501 addr_ranges=0:18446744073709551615
 502 assoc=2
 503 clk_domain=system.cpu_clk_domain
 504 eventq_index=0
 505 forward_snoops=true
 506 hit_latency=2
 507 is_top_level=true
 508 max_miss_count=0
 509 mshrs=4
 510 prefetch_on_access=false
 511 prefetcher=Null
 512 response_latency=2
 513 sequential_access=false
 514 size=131072
 515 system=system
 516 tags=system.cpu.icache.tags
 517 tgts_per_mshr=20
 518 two_queue=false
 519 write_buffers=8
 520 cpu_side=system.cpu.icache_port
 521 mem_side=system.cpu.toL2Bus.slave[0]
 522
 523 [system.cpu.icache.tags]
 524 type=LRU
 525 assoc=2
 526 block_size=64
 527 clk_domain=system.cpu_clk_domain
 528 eventq_index=0
 529 hit_latency=2
 530 sequential_access=false
 531 size=131072
 532
 533 [system.cpu.interrupts]
 534 type=AlphaInterrupts
 535 eventq_index=0
 536
 537 [system.cpu.isa]
 538 type=AlphaISA
 539 eventq_index=0
 540 system=system
 541
 542 [system.cpu.itb]
 543 type=AlphaTLB
 544 eventq_index=0
 545 size=48
 546
 547 [system.cpu.l2cache]
 548 type=BaseCache
 549 children=tags
 550 addr_ranges=0:18446744073709551615
 551 assoc=8
 552 clk_domain=system.cpu_clk_domain
 553 eventq_index=0
 554 forward_snoops=true
 555 hit_latency=20
 556 is_top_level=false
 557 max_miss_count=0
 558 mshrs=20
 559 prefetch_on_access=false
 560 prefetcher=Null
 561 response_latency=20
 562 sequential_access=false
 563 size=2097152
 564 system=system
 565 tags=system.cpu.l2cache.tags
 566 tgts_per_mshr=12
 567 two_queue=false
 568 write_buffers=8
 569 cpu_side=system.cpu.toL2Bus.master[0]
 570 mem_side=system.membus.slave[1]
 571
 572 [system.cpu.l2cache.tags]
 573 type=LRU
 574 assoc=8
 575 block_size=64
 576 clk_domain=system.cpu_clk_domain
 577 eventq_index=0
 578 hit_latency=20
 579 sequential_access=false
 580 size=2097152
 581
 582 [system.cpu.toL2Bus]
 583 type=CoherentBus
 584 clk_domain=system.cpu_clk_domain
 585 eventq_index=0
 586 header_cycles=1
 587 system=system
 588 use_default_range=false
 589 width=32
 590 master=system.cpu.l2cache.cpu_side
 591 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 592
 593 [system.cpu.tracer]
 594 type=ExeTracer
 595 eventq_index=0
 596
 597 [system.cpu.workload]
 598 type=LiveProcess
 599 cmd=perlbmk -I. -I lib lgred.makerand.pl
 600 cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 601 egid=100
 602 env=
 603 errout=cerr
 604 euid=100
 605 eventq_index=0
 606 executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
 607 gid=100
 608 input=cin
 609 max_stack_size=67108864
 610 output=cout
 611 pid=100
 612 ppid=99
 613 simpoint=0
 614 system=system
 615 uid=100
 616
 617 [system.cpu_clk_domain]
 618 type=SrcClockDomain
 619 clock=500
 620 domain_id=-1
 621 eventq_index=0
 622 init_perf_level=0
 623 voltage_domain=system.voltage_domain
 624
 625 [system.dvfs_handler]
 626 type=DVFSHandler
 627 domains=
 628 enable=false
 629 eventq_index=0
 630 sys_clk_domain=system.clk_domain
 631 transition_latency=100000000
 632
 633 [system.membus]
 634 type=CoherentBus
 635 clk_domain=system.clk_domain
 636 eventq_index=0
 637 header_cycles=1
 638 system=system
 639 use_default_range=false
 640 width=8
 641 master=system.physmem.port
 642 slave=system.system_port system.cpu.l2cache.mem_side
 643
 644 [system.physmem]
 645 type=DRAMCtrl
 646 activation_limit=4
 647 addr_mapping=RoRaBaChCo
 648 banks_per_rank=8
 649 burst_length=8
 650 channels=1
 651 clk_domain=system.clk_domain
 652 conf_table_reported=true
 653 device_bus_width=8
 654 device_rowbuffer_size=1024
 655 devices_per_rank=8
 656 eventq_index=0
 657 in_addr_map=true
 658 max_accesses_per_row=16
 659 mem_sched_policy=frfcfs
 660 min_writes_per_switch=16
 661 null=false
 662 page_policy=open_adaptive
 663 range=0:134217727
 664 ranks_per_channel=2
 665 read_buffer_size=32
 666 static_backend_latency=10000
 667 static_frontend_latency=10000
 668 tBURST=5000
 669 tCK=1250
 670 tCL=13750
 671 tRAS=35000
 672 tRCD=13750
 673 tREFI=7800000
 674 tRFC=260000
 675 tRP=13750
 676 tRRD=6000
 677 tRTP=7500
 678 tRTW=2500
 679 tWR=15000
 680 tWTR=7500
 681 tXAW=30000
 682 write_buffer_size=64
 683 write_high_thresh_perc=85
 684 write_low_thresh_perc=50
 685 port=system.membus.master[0]
 686
 687 [system.voltage_domain]
 688 type=VoltageDomain
 689 eventq_index=0
 690 voltage=1.000000
 691