8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
24 memories=system.physmem
28 work_begin_ckpt_count=0
29 work_begin_cpu_id_exit=-1
30 work_begin_exit_count=0
31 work_cpus_ckpt_count=0
35 system_port=system.membus.slave[0]
41 voltage_domain=system.voltage_domain
45 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
54 branchPred=system.cpu.branchPred
57 clk_domain=system.cpu_clk_domain
68 do_checkpoint_insts=true
70 do_statistics_insts=true
78 fuPool=system.cpu.fuPool
80 function_trace_start=0
85 interrupts=system.cpu.interrupts
90 max_insts_all_threads=0
91 max_insts_any_thread=0
92 max_loads_all_threads=0
93 max_loads_any_thread=0
104 renameToDecodeDelay=1
109 simpoint_start_insts=
110 smtCommitPolicy=RoundRobin
111 smtFetchPolicy=SingleThread
112 smtIQPolicy=Partitioned
114 smtLSQPolicy=Partitioned
116 smtNumFetchingThreads=1
117 smtROBPolicy=Partitioned
121 store_set_clear_period=250000
124 tracer=system.cpu.tracer
128 workload=system.cpu.workload
129 dcache_port=system.cpu.dcache.cpu_side
130 icache_port=system.cpu.icache.cpu_side
132 [system.cpu.branchPred]
138 choicePredictorSize=8192
141 globalPredictorSize=8192
144 localHistoryTableSize=2048
145 localPredictorSize=2048
152 addr_ranges=0:18446744073709551615
154 clk_domain=system.cpu_clk_domain
161 prefetch_on_access=false
164 sequential_access=false
167 tags=system.cpu.dcache.tags
171 cpu_side=system.cpu.dcache_port
172 mem_side=system.cpu.toL2Bus.slave[1]
174 [system.cpu.dcache.tags]
178 clk_domain=system.cpu_clk_domain
181 sequential_access=false
191 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
192 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
195 [system.cpu.fuPool.FUList0]
200 opList=system.cpu.fuPool.FUList0.opList
202 [system.cpu.fuPool.FUList0.opList]
209 [system.cpu.fuPool.FUList1]
211 children=opList0 opList1
214 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
216 [system.cpu.fuPool.FUList1.opList0]
223 [system.cpu.fuPool.FUList1.opList1]
230 [system.cpu.fuPool.FUList2]
232 children=opList0 opList1 opList2
235 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
237 [system.cpu.fuPool.FUList2.opList0]
244 [system.cpu.fuPool.FUList2.opList1]
251 [system.cpu.fuPool.FUList2.opList2]
258 [system.cpu.fuPool.FUList3]
260 children=opList0 opList1 opList2
263 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
265 [system.cpu.fuPool.FUList3.opList0]
272 [system.cpu.fuPool.FUList3.opList1]
279 [system.cpu.fuPool.FUList3.opList2]
286 [system.cpu.fuPool.FUList4]
291 opList=system.cpu.fuPool.FUList4.opList
293 [system.cpu.fuPool.FUList4.opList]
300 [system.cpu.fuPool.FUList5]
302 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
305 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
307 [system.cpu.fuPool.FUList5.opList00]
314 [system.cpu.fuPool.FUList5.opList01]
321 [system.cpu.fuPool.FUList5.opList02]
328 [system.cpu.fuPool.FUList5.opList03]
335 [system.cpu.fuPool.FUList5.opList04]
342 [system.cpu.fuPool.FUList5.opList05]
349 [system.cpu.fuPool.FUList5.opList06]
356 [system.cpu.fuPool.FUList5.opList07]
363 [system.cpu.fuPool.FUList5.opList08]
370 [system.cpu.fuPool.FUList5.opList09]
377 [system.cpu.fuPool.FUList5.opList10]
384 [system.cpu.fuPool.FUList5.opList11]
391 [system.cpu.fuPool.FUList5.opList12]
398 [system.cpu.fuPool.FUList5.opList13]
405 [system.cpu.fuPool.FUList5.opList14]
412 [system.cpu.fuPool.FUList5.opList15]
419 [system.cpu.fuPool.FUList5.opList16]
423 opClass=SimdFloatMisc
426 [system.cpu.fuPool.FUList5.opList17]
430 opClass=SimdFloatMult
433 [system.cpu.fuPool.FUList5.opList18]
437 opClass=SimdFloatMultAcc
440 [system.cpu.fuPool.FUList5.opList19]
444 opClass=SimdFloatSqrt
447 [system.cpu.fuPool.FUList6]
452 opList=system.cpu.fuPool.FUList6.opList
454 [system.cpu.fuPool.FUList6.opList]
461 [system.cpu.fuPool.FUList7]
463 children=opList0 opList1
466 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
468 [system.cpu.fuPool.FUList7.opList0]
475 [system.cpu.fuPool.FUList7.opList1]
482 [system.cpu.fuPool.FUList8]
487 opList=system.cpu.fuPool.FUList8.opList
489 [system.cpu.fuPool.FUList8.opList]
499 addr_ranges=0:18446744073709551615
501 clk_domain=system.cpu_clk_domain
508 prefetch_on_access=false
511 sequential_access=false
514 tags=system.cpu.icache.tags
518 cpu_side=system.cpu.icache_port
519 mem_side=system.cpu.toL2Bus.slave[0]
521 [system.cpu.icache.tags]
525 clk_domain=system.cpu_clk_domain
528 sequential_access=false
531 [system.cpu.interrupts]
548 addr_ranges=0:18446744073709551615
550 clk_domain=system.cpu_clk_domain
557 prefetch_on_access=false
560 sequential_access=false
563 tags=system.cpu.l2cache.tags
567 cpu_side=system.cpu.toL2Bus.master[0]
568 mem_side=system.membus.slave[1]
570 [system.cpu.l2cache.tags]
574 clk_domain=system.cpu_clk_domain
577 sequential_access=false
582 clk_domain=system.cpu_clk_domain
586 use_default_range=false
588 master=system.cpu.l2cache.cpu_side
589 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
595 [system.cpu.workload]
597 cmd=perlbmk -I. -I lib lgred.makerand.pl
598 cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
604 executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
607 max_stack_size=67108864
615 [system.cpu_clk_domain]
619 voltage_domain=system.voltage_domain
623 clk_domain=system.clk_domain
627 use_default_range=false
629 master=system.physmem.port
630 slave=system.system_port system.cpu.l2cache.mem_side
635 addr_mapping=RoRaBaChCo
639 clk_domain=system.clk_domain
640 conf_table_reported=true
642 device_rowbuffer_size=1024
646 max_accesses_per_row=16
647 mem_sched_policy=frfcfs
648 min_writes_per_switch=16
650 page_policy=open_adaptive
654 static_backend_latency=10000
655 static_frontend_latency=10000
671 write_high_thresh_perc=85
672 write_low_thresh_perc=50
673 port=system.membus.master[0]
675 [system.voltage_domain]