2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.629599 # Number of seconds simulated
4 sim_ticks 629599373500 # Number of ticks simulated
5 final_tick 629599373500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 142688 # Simulator instruction rate (inst/s)
8 host_op_rate 142688 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49278187 # Simulator tick rate (ticks/s)
10 host_mem_usage 277460 # Number of bytes of host memory used
11 host_seconds 12776.43 # Real time elapsed on the host
12 sim_insts 1823043370 # Number of instructions simulated
13 sim_ops 1823043370 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 176768 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 30472704 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 176768 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 176768 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 2762 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 476136 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 280763 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 48119387 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 48400150 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 280763 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 280763 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 6801328 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 6801328 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 6801328 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 280763 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 48119387 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 55201478 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 476136 # Number of read requests accepted
40 system.physmem.writeReqs 66908 # Number of write requests accepted
41 system.physmem.readBursts 476136 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 30452800 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 4280256 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 30472704 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 29443 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 29785 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 29834 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 29781 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 29679 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 29744 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 29853 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 29847 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 29759 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 29871 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 29836 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 29910 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 29783 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 29571 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 29499 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 29630 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 4334 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 4219 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 629599315500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 476136 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 66908 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 405282 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 66881 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 3493 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 959 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 2490 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 4004 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 4022 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 4046 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 4182 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 4155 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 4085 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 4086 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 4055 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 4061 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 1513 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 21634 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 530.927244 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 283.070424 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 451.227629 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 7470 34.53% 34.53% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 2793 12.91% 47.44% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 292 1.35% 48.79% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 662 3.06% 51.85% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 618 2.86% 54.71% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 184 0.85% 55.56% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 105 0.49% 56.04% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 67 0.31% 56.35% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 9443 43.65% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 21634 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 4040 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 114.953218 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::gmean 36.941709 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::stdev 1121.982719 # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::0-2047 4021 99.53% 99.53% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.55% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.70% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::14336-16383 11 0.27% 99.98% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::total 4040 # Reads before turning the bus around for writes
220 system.physmem.wrPerTurnAround::samples 4040 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::mean 16.554208 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::gmean 16.524474 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::stdev 1.020237 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::16 3080 76.24% 76.24% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::18 645 15.97% 92.20% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::19 312 7.72% 99.93% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::total 4040 # Writes before turning the bus around for reads
230 system.physmem.totQLat 3865744500 # Total ticks spent queuing
231 system.physmem.totMemAccLat 15098494500 # Total ticks spent from burst creation until serviced by the DRAM
232 system.physmem.totBusLat 2379125000 # Total ticks spent in databus transfers
233 system.physmem.totBankLat 8853625000 # Total ticks spent accessing banks
234 system.physmem.avgQLat 8124.30 # Average queueing delay per DRAM burst
235 system.physmem.avgBankLat 18606.89 # Average bank access latency per DRAM burst
236 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
237 system.physmem.avgMemAccLat 31731.19 # Average memory access latency per DRAM burst
238 system.physmem.avgRdBW 48.37 # Average DRAM read bandwidth in MiByte/s
239 system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s
240 system.physmem.avgRdBWSys 48.40 # Average system read bandwidth in MiByte/s
241 system.physmem.avgWrBWSys 6.80 # Average system write bandwidth in MiByte/s
242 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
243 system.physmem.busUtil 0.43 # Data bus utilization in percentage
244 system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
245 system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
246 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
247 system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
248 system.physmem.readRowHits 304858 # Number of row buffer hits during reads
249 system.physmem.writeRowHits 50638 # Number of row buffer hits during writes
250 system.physmem.readRowHitRate 64.07 # Row buffer hit rate for reads
251 system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes
252 system.physmem.avgGap 1159389.14 # Average gap between requests
253 system.physmem.pageHitRate 65.50 # Row buffer hit rate, read and write combined
254 system.physmem.prechargeAllPercent 25.10 # Percentage of time for which DRAM has all the banks in precharge state
255 system.membus.throughput 55201376 # Throughput (bytes/s)
256 system.membus.trans_dist::ReadReq 409283 # Transaction distribution
257 system.membus.trans_dist::ReadResp 409282 # Transaction distribution
258 system.membus.trans_dist::Writeback 66908 # Transaction distribution
259 system.membus.trans_dist::ReadExReq 66853 # Transaction distribution
260 system.membus.trans_dist::ReadExResp 66853 # Transaction distribution
261 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019179 # Packet count per connected master and slave (bytes)
262 system.membus.pkt_count::total 1019179 # Packet count per connected master and slave (bytes)
263 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754752 # Cumulative packet size per connected master and slave (bytes)
264 system.membus.tot_pkt_size::total 34754752 # Cumulative packet size per connected master and slave (bytes)
265 system.membus.data_through_bus 34754752 # Total data (bytes)
266 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
267 system.membus.reqLayer0.occupancy 1216217500 # Layer occupancy (ticks)
268 system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
269 system.membus.respLayer1.occupancy 4476344750 # Layer occupancy (ticks)
270 system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
271 system.cpu_clk_domain.clock 500 # Clock period in ticks
272 system.cpu.branchPred.lookups 388794194 # Number of BP lookups
273 system.cpu.branchPred.condPredicted 256437181 # Number of conditional branches predicted
274 system.cpu.branchPred.condIncorrect 25515612 # Number of conditional branches incorrect
275 system.cpu.branchPred.BTBLookups 316966671 # Number of BTB lookups
276 system.cpu.branchPred.BTBHits 257889505 # Number of BTB hits
277 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
278 system.cpu.branchPred.BTBHitPct 81.361710 # BTB Hit Percentage
279 system.cpu.branchPred.usedRAS 56977055 # Number of times the RAS was used to get a target.
280 system.cpu.branchPred.RASInCorrect 6765 # Number of incorrect RAS predictions.
281 system.cpu.dtb.fetch_hits 0 # ITB hits
282 system.cpu.dtb.fetch_misses 0 # ITB misses
283 system.cpu.dtb.fetch_acv 0 # ITB acv
284 system.cpu.dtb.fetch_accesses 0 # ITB accesses
285 system.cpu.dtb.read_hits 520530320 # DTB read hits
286 system.cpu.dtb.read_misses 596868 # DTB read misses
287 system.cpu.dtb.read_acv 0 # DTB read access violations
288 system.cpu.dtb.read_accesses 521127188 # DTB read accesses
289 system.cpu.dtb.write_hits 282735636 # DTB write hits
290 system.cpu.dtb.write_misses 50248 # DTB write misses
291 system.cpu.dtb.write_acv 0 # DTB write access violations
292 system.cpu.dtb.write_accesses 282785884 # DTB write accesses
293 system.cpu.dtb.data_hits 803265956 # DTB hits
294 system.cpu.dtb.data_misses 647116 # DTB misses
295 system.cpu.dtb.data_acv 0 # DTB access violations
296 system.cpu.dtb.data_accesses 803913072 # DTB accesses
297 system.cpu.itb.fetch_hits 392575649 # ITB hits
298 system.cpu.itb.fetch_misses 637 # ITB misses
299 system.cpu.itb.fetch_acv 0 # ITB acv
300 system.cpu.itb.fetch_accesses 392576286 # ITB accesses
301 system.cpu.itb.read_hits 0 # DTB read hits
302 system.cpu.itb.read_misses 0 # DTB read misses
303 system.cpu.itb.read_acv 0 # DTB read access violations
304 system.cpu.itb.read_accesses 0 # DTB read accesses
305 system.cpu.itb.write_hits 0 # DTB write hits
306 system.cpu.itb.write_misses 0 # DTB write misses
307 system.cpu.itb.write_acv 0 # DTB write access violations
308 system.cpu.itb.write_accesses 0 # DTB write accesses
309 system.cpu.itb.data_hits 0 # DTB hits
310 system.cpu.itb.data_misses 0 # DTB misses
311 system.cpu.itb.data_acv 0 # DTB access violations
312 system.cpu.itb.data_accesses 0 # DTB accesses
313 system.cpu.workload.num_syscalls 39 # Number of system calls
314 system.cpu.numCycles 1259198748 # number of cpu cycles simulated
315 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
316 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
317 system.cpu.fetch.icacheStallCycles 407695740 # Number of cycles fetch is stalled on an Icache miss
318 system.cpu.fetch.Insts 3264617465 # Number of instructions fetch has processed
319 system.cpu.fetch.Branches 388794194 # Number of branches that fetch encountered
320 system.cpu.fetch.predictedBranches 314866560 # Number of branches that fetch has predicted taken
321 system.cpu.fetch.Cycles 628012855 # Number of cycles fetch has run and was not squashing or blocked
322 system.cpu.fetch.SquashCycles 156754099 # Number of cycles fetch has spent squashing
323 system.cpu.fetch.BlockedCycles 76226521 # Number of cycles fetch has spent blocked
324 system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
325 system.cpu.fetch.PendingTrapStallCycles 6801 # Number of stall cycles due to pending traps
326 system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
327 system.cpu.fetch.CacheLines 392575649 # Number of cache lines fetched
328 system.cpu.fetch.IcacheSquashes 11023705 # Number of outstanding Icache misses that were squashed
329 system.cpu.fetch.rateDist::samples 1242691149 # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::mean 2.627055 # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::stdev 3.139887 # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::0 614678294 49.46% 49.46% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::1 57194010 4.60% 54.07% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::2 43037577 3.46% 57.53% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::3 71548664 5.76% 63.29% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::4 128942698 10.38% 73.66% # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::5 45555972 3.67% 77.33% # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::6 41222741 3.32% 80.65% # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::7 8274333 0.67% 81.31% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::8 232236860 18.69% 100.00% # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::total 1242691149 # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.branchRate 0.308763 # Number of branch fetches per cycle
347 system.cpu.fetch.rate 2.592615 # Number of inst fetches per cycle
348 system.cpu.decode.IdleCycles 436055809 # Number of cycles decode is idle
349 system.cpu.decode.BlockedCycles 62292865 # Number of cycles decode is blocked
350 system.cpu.decode.RunCycles 604244409 # Number of cycles decode is running
351 system.cpu.decode.UnblockCycles 9361042 # Number of cycles decode is unblocking
352 system.cpu.decode.SquashCycles 130737024 # Number of cycles decode is squashing
353 system.cpu.decode.BranchResolved 31725769 # Number of times decode resolved a branch
354 system.cpu.decode.BranchMispred 12419 # Number of times decode detected a branch misprediction
355 system.cpu.decode.DecodedInsts 3186787270 # Number of instructions handled by decode
356 system.cpu.decode.SquashedInsts 46304 # Number of squashed instructions handled by decode
357 system.cpu.rename.SquashCycles 130737024 # Number of cycles rename is squashing
358 system.cpu.rename.IdleCycles 465340122 # Number of cycles rename is idle
359 system.cpu.rename.BlockCycles 27154826 # Number of cycles rename is blocking
360 system.cpu.rename.serializeStallCycles 26997 # count of cycles rename stalled for serializing inst
361 system.cpu.rename.RunCycles 583972819 # Number of cycles rename is running
362 system.cpu.rename.UnblockCycles 35459361 # Number of cycles rename is unblocking
363 system.cpu.rename.RenamedInsts 3088232608 # Number of instructions processed by rename
364 system.cpu.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full
365 system.cpu.rename.IQFullEvents 15483 # Number of times rename has blocked due to IQ full
366 system.cpu.rename.LSQFullEvents 29158265 # Number of times rename has blocked due to LSQ full
367 system.cpu.rename.RenamedOperands 2049406757 # Number of destination operands rename has renamed
368 system.cpu.rename.RenameLookups 3572462908 # Number of register rename lookups that rename has made
369 system.cpu.rename.int_rename_lookups 3487065334 # Number of integer rename lookups
370 system.cpu.rename.fp_rename_lookups 85397573 # Number of floating rename lookups
371 system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
372 system.cpu.rename.UndoneMaps 664437687 # Number of HB maps that are undone due to squashing
373 system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed
374 system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed
375 system.cpu.rename.skidInsts 110031896 # count of insts added to the skid buffer
376 system.cpu.memDep0.insertedLoads 740965992 # Number of loads inserted to the mem dependence unit.
377 system.cpu.memDep0.insertedStores 350476523 # Number of stores inserted to the mem dependence unit.
378 system.cpu.memDep0.conflictingLoads 68460641 # Number of conflicting loads.
379 system.cpu.memDep0.conflictingStores 8808840 # Number of conflicting stores.
380 system.cpu.iq.iqInstsAdded 2617422170 # Number of instructions added to the IQ (excludes non-spec)
381 system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ
382 system.cpu.iq.iqInstsIssued 2156741664 # Number of instructions issued
383 system.cpu.iq.iqSquashedInstsIssued 17943359 # Number of squashed instructions issued
384 system.cpu.iq.iqSquashedInstsExamined 794308745 # Number of squashed instructions iterated over during squash; mainly for profiling
385 system.cpu.iq.iqSquashedOperandsExamined 722892982 # Number of squashed operands that are examined and possibly removed from graph
386 system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed
387 system.cpu.iq.issued_per_cycle::samples 1242691149 # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::mean 1.735541 # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::stdev 1.803084 # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::0 447799861 36.03% 36.03% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::1 195733301 15.75% 51.79% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::2 250780419 20.18% 71.97% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::3 120973704 9.73% 81.70% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::4 105324665 8.48% 90.18% # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::5 78133504 6.29% 96.46% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::6 24822476 2.00% 98.46% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::7 17360375 1.40% 99.86% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::8 1762844 0.14% 100.00% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::total 1242691149 # Number of insts issued each cycle
404 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
405 system.cpu.iq.fu_full::IntAlu 1146236 3.14% 3.14% # attempts to use FU when none available
406 system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available
407 system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available
408 system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available
409 system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available
410 system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available
411 system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available
412 system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available
413 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
434 system.cpu.iq.fu_full::MemRead 25360136 69.42% 72.56% # attempts to use FU when none available
435 system.cpu.iq.fu_full::MemWrite 10022546 27.44% 100.00% # attempts to use FU when none available
436 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
437 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
438 system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
439 system.cpu.iq.FU_type_0::IntAlu 1232941102 57.17% 57.17% # Type of FU issued
440 system.cpu.iq.FU_type_0::IntMult 17091 0.00% 57.17% # Type of FU issued
441 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued
442 system.cpu.iq.FU_type_0::FloatAdd 27851332 1.29% 58.46% # Type of FU issued
443 system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.84% # Type of FU issued
444 system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued
445 system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued
446 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued
447 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued
468 system.cpu.iq.FU_type_0::MemRead 587650943 27.25% 86.42% # Type of FU issued
469 system.cpu.iq.FU_type_0::MemWrite 292819094 13.58% 100.00% # Type of FU issued
470 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
471 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
472 system.cpu.iq.FU_type_0::total 2156741664 # Type of FU issued
473 system.cpu.iq.rate 1.712789 # Inst issue rate
474 system.cpu.iq.fu_busy_cnt 36528918 # FU busy when requested
475 system.cpu.iq.fu_busy_rate 0.016937 # FU busy rate (busy events/executed inst)
476 system.cpu.iq.int_inst_queue_reads 5459545573 # Number of integer instruction queue reads
477 system.cpu.iq.int_inst_queue_writes 3323652243 # Number of integer instruction queue writes
478 system.cpu.iq.int_inst_queue_wakeup_accesses 1987168817 # Number of integer instruction queue wakeup accesses
479 system.cpu.iq.fp_inst_queue_reads 151101181 # Number of floating instruction queue reads
480 system.cpu.iq.fp_inst_queue_writes 88152162 # Number of floating instruction queue writes
481 system.cpu.iq.fp_inst_queue_wakeup_accesses 73609871 # Number of floating instruction queue wakeup accesses
482 system.cpu.iq.int_alu_accesses 2115818130 # Number of integer alu accesses
483 system.cpu.iq.fp_alu_accesses 77449700 # Number of floating point alu accesses
484 system.cpu.iew.lsq.thread0.forwLoads 62140575 # Number of loads that had data forwarded from stores
485 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
486 system.cpu.iew.lsq.thread0.squashedLoads 229895966 # Number of loads squashed
487 system.cpu.iew.lsq.thread0.ignoredResponses 17367 # Number of memory responses ignored because the instruction is squashed
488 system.cpu.iew.lsq.thread0.memOrderViolation 75928 # Number of memory ordering violations
489 system.cpu.iew.lsq.thread0.squashedStores 139681627 # Number of stores squashed
490 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
491 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
492 system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled
493 system.cpu.iew.lsq.thread0.cacheBlocked 2851 # Number of times an access to memory failed due to the cache being blocked
494 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
495 system.cpu.iew.iewSquashCycles 130737024 # Number of cycles IEW is squashing
496 system.cpu.iew.iewBlockCycles 13158740 # Number of cycles IEW is blocking
497 system.cpu.iew.iewUnblockCycles 531547 # Number of cycles IEW is unblocking
498 system.cpu.iew.iewDispatchedInsts 2980853453 # Number of instructions dispatched to IQ
499 system.cpu.iew.iewDispSquashedInsts 734148 # Number of squashed instructions skipped by dispatch
500 system.cpu.iew.iewDispLoadInsts 740965992 # Number of dispatched load instructions
501 system.cpu.iew.iewDispStoreInsts 350476523 # Number of dispatched store instructions
502 system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions
503 system.cpu.iew.iewIQFullEvents 133073 # Number of times the IQ has become full, causing a stall
504 system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall
505 system.cpu.iew.memOrderViolationEvents 75928 # Number of memory order violations
506 system.cpu.iew.predictedTakenIncorrect 25509079 # Number of branches that were predicted taken incorrectly
507 system.cpu.iew.predictedNotTakenIncorrect 28871 # Number of branches that were predicted not taken incorrectly
508 system.cpu.iew.branchMispredicts 25537950 # Number of branch mispredicts detected at execute
509 system.cpu.iew.iewExecutedInsts 2062960594 # Number of executed instructions
510 system.cpu.iew.iewExecLoadInsts 521127327 # Number of load instructions executed
511 system.cpu.iew.iewExecSquashedInsts 93781070 # Number of squashed instructions skipped in execute
512 system.cpu.iew.exec_swp 0 # number of swp insts executed
513 system.cpu.iew.exec_nop 363431191 # number of nop insts executed
514 system.cpu.iew.exec_refs 803913709 # number of memory reference insts executed
515 system.cpu.iew.exec_branches 277349504 # Number of branches executed
516 system.cpu.iew.exec_stores 282786382 # Number of stores executed
517 system.cpu.iew.exec_rate 1.638312 # Inst execution rate
518 system.cpu.iew.wb_sent 2062843616 # cumulative count of insts sent to commit
519 system.cpu.iew.wb_count 2060778688 # cumulative count of insts written-back
520 system.cpu.iew.wb_producers 1180081311 # num instructions producing a value
521 system.cpu.iew.wb_consumers 1751769057 # num instructions consuming a value
522 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
523 system.cpu.iew.wb_rate 1.636579 # insts written-back per cycle
524 system.cpu.iew.wb_fanout 0.673651 # average fanout of values written-back
525 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
526 system.cpu.commit.commitSquashedInsts 954910834 # The number of squashed insts skipped by commit
527 system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
528 system.cpu.commit.branchMispredicts 25503576 # The number of times a branch was mispredicted
529 system.cpu.commit.committed_per_cycle::samples 1111954125 # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::mean 1.806718 # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::stdev 2.513025 # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::0 493953799 44.42% 44.42% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::1 227598258 20.47% 64.89% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::2 120157352 10.81% 75.70% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::3 59117436 5.32% 81.01% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::4 49692095 4.47% 85.48% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::5 24169379 2.17% 87.66% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::6 18838880 1.69% 89.35% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::7 16341629 1.47% 90.82% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::8 102085297 9.18% 100.00% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::total 1111954125 # Number of insts commited each cycle
546 system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
547 system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
548 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
549 system.cpu.commit.refs 721864922 # Number of memory references committed
550 system.cpu.commit.loads 511070026 # Number of loads committed
551 system.cpu.commit.membars 0 # Number of memory barriers committed
552 system.cpu.commit.branches 266706457 # Number of branches committed
553 system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
554 system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
555 system.cpu.commit.function_calls 39955347 # Number of function calls committed.
556 system.cpu.commit.bw_lim_events 102085297 # number cycles where commit BW limit reached
557 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
558 system.cpu.rob.rob_reads 3968130856 # The number of ROB reads
559 system.cpu.rob.rob_writes 6058536012 # The number of ROB writes
560 system.cpu.timesIdled 350219 # Number of times that the entire CPU went into an idle state and unscheduled itself
561 system.cpu.idleCycles 16507599 # Total number of cycles that the CPU has spent unscheduled due to idling
562 system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
563 system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
564 system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
565 system.cpu.cpi 0.690712 # CPI: Cycles Per Instruction
566 system.cpu.cpi_total 0.690712 # CPI: Total CPI of All Threads
567 system.cpu.ipc 1.447780 # IPC: Instructions Per Cycle
568 system.cpu.ipc_total 1.447780 # IPC: Total IPC of All Threads
569 system.cpu.int_regfile_reads 2624503768 # number of integer regfile reads
570 system.cpu.int_regfile_writes 1494046892 # number of integer regfile writes
571 system.cpu.fp_regfile_reads 78811207 # number of floating regfile reads
572 system.cpu.fp_regfile_writes 52661075 # number of floating regfile writes
573 system.cpu.misc_regfile_reads 1 # number of misc regfile reads
574 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
575 system.cpu.toL2Bus.throughput 166495312 # Throughput (bytes/s)
576 system.cpu.toL2Bus.trans_dist::ReadReq 1470280 # Transaction distribution
577 system.cpu.toL2Bus.trans_dist::ReadResp 1470279 # Transaction distribution
578 system.cpu.toL2Bus.trans_dist::Writeback 95977 # Transaction distribution
579 system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution
580 system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution
581 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20109 # Packet count per connected master and slave (bytes)
582 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159707 # Packet count per connected master and slave (bytes)
583 system.cpu.toL2Bus.pkt_count::total 3179816 # Packet count per connected master and slave (bytes)
584 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643456 # Cumulative packet size per connected master and slave (bytes)
585 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104181888 # Cumulative packet size per connected master and slave (bytes)
586 system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes)
587 system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes)
588 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
589 system.cpu.toL2Bus.reqLayer0.occupancy 914925500 # Layer occupancy (ticks)
590 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
591 system.cpu.toL2Bus.respLayer0.occupancy 15572000 # Layer occupancy (ticks)
592 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
593 system.cpu.toL2Bus.respLayer1.occupancy 2358250250 # Layer occupancy (ticks)
594 system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
595 system.cpu.icache.tags.replacements 8345 # number of replacements
596 system.cpu.icache.tags.tagsinuse 1652.999012 # Cycle average of tags in use
597 system.cpu.icache.tags.total_refs 392562699 # Total number of references to valid blocks.
598 system.cpu.icache.tags.sampled_refs 10054 # Sample count of references to valid blocks.
599 system.cpu.icache.tags.avg_refs 39045.424607 # Average number of references to valid blocks.
600 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
601 system.cpu.icache.tags.occ_blocks::cpu.inst 1652.999012 # Average occupied blocks per requestor
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603 system.cpu.icache.tags.occ_percent::total 0.807128 # Average percentage of cache occupancy
604 system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id
605 system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
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607 system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
608 system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id
609 system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id
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611 system.cpu.icache.tags.data_accesses 785161352 # Number of data accesses
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613 system.cpu.icache.ReadReq_hits::total 392562699 # number of ReadReq hits
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615 system.cpu.icache.demand_hits::total 392562699 # number of demand (read+write) hits
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617 system.cpu.icache.overall_hits::total 392562699 # number of overall hits
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619 system.cpu.icache.ReadReq_misses::total 12950 # number of ReadReq misses
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621 system.cpu.icache.demand_misses::total 12950 # number of demand (read+write) misses
622 system.cpu.icache.overall_misses::cpu.inst 12950 # number of overall misses
623 system.cpu.icache.overall_misses::total 12950 # number of overall misses
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625 system.cpu.icache.ReadReq_miss_latency::total 384762999 # number of ReadReq miss cycles
626 system.cpu.icache.demand_miss_latency::cpu.inst 384762999 # number of demand (read+write) miss cycles
627 system.cpu.icache.demand_miss_latency::total 384762999 # number of demand (read+write) miss cycles
628 system.cpu.icache.overall_miss_latency::cpu.inst 384762999 # number of overall miss cycles
629 system.cpu.icache.overall_miss_latency::total 384762999 # number of overall miss cycles
630 system.cpu.icache.ReadReq_accesses::cpu.inst 392575649 # number of ReadReq accesses(hits+misses)
631 system.cpu.icache.ReadReq_accesses::total 392575649 # number of ReadReq accesses(hits+misses)
632 system.cpu.icache.demand_accesses::cpu.inst 392575649 # number of demand (read+write) accesses
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634 system.cpu.icache.overall_accesses::cpu.inst 392575649 # number of overall (read+write) accesses
635 system.cpu.icache.overall_accesses::total 392575649 # number of overall (read+write) accesses
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637 system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
638 system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
639 system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
640 system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
641 system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
642 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29711.428494 # average ReadReq miss latency
643 system.cpu.icache.ReadReq_avg_miss_latency::total 29711.428494 # average ReadReq miss latency
644 system.cpu.icache.demand_avg_miss_latency::cpu.inst 29711.428494 # average overall miss latency
645 system.cpu.icache.demand_avg_miss_latency::total 29711.428494 # average overall miss latency
646 system.cpu.icache.overall_avg_miss_latency::cpu.inst 29711.428494 # average overall miss latency
647 system.cpu.icache.overall_avg_miss_latency::total 29711.428494 # average overall miss latency
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650 system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
651 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
652 system.cpu.icache.avg_blocked_cycles::no_mshrs 47.769231 # average number of cycles each access was blocked
653 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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657 system.cpu.icache.ReadReq_mshr_hits::total 2895 # number of ReadReq MSHR hits
658 system.cpu.icache.demand_mshr_hits::cpu.inst 2895 # number of demand (read+write) MSHR hits
659 system.cpu.icache.demand_mshr_hits::total 2895 # number of demand (read+write) MSHR hits
660 system.cpu.icache.overall_mshr_hits::cpu.inst 2895 # number of overall MSHR hits
661 system.cpu.icache.overall_mshr_hits::total 2895 # number of overall MSHR hits
662 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10055 # number of ReadReq MSHR misses
663 system.cpu.icache.ReadReq_mshr_misses::total 10055 # number of ReadReq MSHR misses
664 system.cpu.icache.demand_mshr_misses::cpu.inst 10055 # number of demand (read+write) MSHR misses
665 system.cpu.icache.demand_mshr_misses::total 10055 # number of demand (read+write) MSHR misses
666 system.cpu.icache.overall_mshr_misses::cpu.inst 10055 # number of overall MSHR misses
667 system.cpu.icache.overall_mshr_misses::total 10055 # number of overall MSHR misses
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669 system.cpu.icache.ReadReq_mshr_miss_latency::total 283775749 # number of ReadReq MSHR miss cycles
670 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 283775749 # number of demand (read+write) MSHR miss cycles
671 system.cpu.icache.demand_mshr_miss_latency::total 283775749 # number of demand (read+write) MSHR miss cycles
672 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 283775749 # number of overall MSHR miss cycles
673 system.cpu.icache.overall_mshr_miss_latency::total 283775749 # number of overall MSHR miss cycles
674 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for ReadReq accesses
675 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000026 # mshr miss rate for ReadReq accesses
676 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses
677 system.cpu.icache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
678 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses
679 system.cpu.icache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
680 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28222.351964 # average ReadReq mshr miss latency
681 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28222.351964 # average ReadReq mshr miss latency
682 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency
683 system.cpu.icache.demand_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency
684 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency
685 system.cpu.icache.overall_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency
686 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
687 system.cpu.l2cache.tags.replacements 443357 # number of replacements
688 system.cpu.l2cache.tags.tagsinuse 32688.486835 # Cycle average of tags in use
689 system.cpu.l2cache.tags.total_refs 1090024 # Total number of references to valid blocks.
690 system.cpu.l2cache.tags.sampled_refs 476094 # Sample count of references to valid blocks.
691 system.cpu.l2cache.tags.avg_refs 2.289514 # Average number of references to valid blocks.
692 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
693 system.cpu.l2cache.tags.occ_blocks::writebacks 1336.366869 # Average occupied blocks per requestor
694 system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.201228 # Average occupied blocks per requestor
695 system.cpu.l2cache.tags.occ_blocks::cpu.data 31316.918737 # Average occupied blocks per requestor
696 system.cpu.l2cache.tags.occ_percent::writebacks 0.040783 # Average percentage of cache occupancy
697 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001074 # Average percentage of cache occupancy
698 system.cpu.l2cache.tags.occ_percent::cpu.data 0.955717 # Average percentage of cache occupancy
699 system.cpu.l2cache.tags.occ_percent::total 0.997573 # Average percentage of cache occupancy
700 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id
701 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id
702 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
703 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 505 # Occupied blocks per task id
704 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5022 # Occupied blocks per task id
705 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26849 # Occupied blocks per task id
706 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id
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708 system.cpu.l2cache.tags.data_accesses 13650910 # Number of data accesses
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711 system.cpu.l2cache.ReadReq_hits::total 1060997 # number of ReadReq hits
712 system.cpu.l2cache.Writeback_hits::writebacks 95977 # number of Writeback hits
713 system.cpu.l2cache.Writeback_hits::total 95977 # number of Writeback hits
714 system.cpu.l2cache.ReadExReq_hits::cpu.data 4787 # number of ReadExReq hits
715 system.cpu.l2cache.ReadExReq_hits::total 4787 # number of ReadExReq hits
716 system.cpu.l2cache.demand_hits::cpu.inst 7293 # number of demand (read+write) hits
717 system.cpu.l2cache.demand_hits::cpu.data 1058491 # number of demand (read+write) hits
718 system.cpu.l2cache.demand_hits::total 1065784 # number of demand (read+write) hits
719 system.cpu.l2cache.overall_hits::cpu.inst 7293 # number of overall hits
720 system.cpu.l2cache.overall_hits::cpu.data 1058491 # number of overall hits
721 system.cpu.l2cache.overall_hits::total 1065784 # number of overall hits
722 system.cpu.l2cache.ReadReq_misses::cpu.inst 2762 # number of ReadReq misses
723 system.cpu.l2cache.ReadReq_misses::cpu.data 406521 # number of ReadReq misses
724 system.cpu.l2cache.ReadReq_misses::total 409283 # number of ReadReq misses
725 system.cpu.l2cache.ReadExReq_misses::cpu.data 66853 # number of ReadExReq misses
726 system.cpu.l2cache.ReadExReq_misses::total 66853 # number of ReadExReq misses
727 system.cpu.l2cache.demand_misses::cpu.inst 2762 # number of demand (read+write) misses
728 system.cpu.l2cache.demand_misses::cpu.data 473374 # number of demand (read+write) misses
729 system.cpu.l2cache.demand_misses::total 476136 # number of demand (read+write) misses
730 system.cpu.l2cache.overall_misses::cpu.inst 2762 # number of overall misses
731 system.cpu.l2cache.overall_misses::cpu.data 473374 # number of overall misses
732 system.cpu.l2cache.overall_misses::total 476136 # number of overall misses
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734 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29850948750 # number of ReadReq miss cycles
735 system.cpu.l2cache.ReadReq_miss_latency::total 30051733750 # number of ReadReq miss cycles
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737 system.cpu.l2cache.ReadExReq_miss_latency::total 5675940500 # number of ReadExReq miss cycles
738 system.cpu.l2cache.demand_miss_latency::cpu.inst 200785000 # number of demand (read+write) miss cycles
739 system.cpu.l2cache.demand_miss_latency::cpu.data 35526889250 # number of demand (read+write) miss cycles
740 system.cpu.l2cache.demand_miss_latency::total 35727674250 # number of demand (read+write) miss cycles
741 system.cpu.l2cache.overall_miss_latency::cpu.inst 200785000 # number of overall miss cycles
742 system.cpu.l2cache.overall_miss_latency::cpu.data 35526889250 # number of overall miss cycles
743 system.cpu.l2cache.overall_miss_latency::total 35727674250 # number of overall miss cycles
744 system.cpu.l2cache.ReadReq_accesses::cpu.inst 10055 # number of ReadReq accesses(hits+misses)
745 system.cpu.l2cache.ReadReq_accesses::cpu.data 1460225 # number of ReadReq accesses(hits+misses)
746 system.cpu.l2cache.ReadReq_accesses::total 1470280 # number of ReadReq accesses(hits+misses)
747 system.cpu.l2cache.Writeback_accesses::writebacks 95977 # number of Writeback accesses(hits+misses)
748 system.cpu.l2cache.Writeback_accesses::total 95977 # number of Writeback accesses(hits+misses)
749 system.cpu.l2cache.ReadExReq_accesses::cpu.data 71640 # number of ReadExReq accesses(hits+misses)
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752 system.cpu.l2cache.demand_accesses::cpu.data 1531865 # number of demand (read+write) accesses
753 system.cpu.l2cache.demand_accesses::total 1541920 # number of demand (read+write) accesses
754 system.cpu.l2cache.overall_accesses::cpu.inst 10055 # number of overall (read+write) accesses
755 system.cpu.l2cache.overall_accesses::cpu.data 1531865 # number of overall (read+write) accesses
756 system.cpu.l2cache.overall_accesses::total 1541920 # number of overall (read+write) accesses
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759 system.cpu.l2cache.ReadReq_miss_rate::total 0.278371 # miss rate for ReadReq accesses
760 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933180 # miss rate for ReadExReq accesses
761 system.cpu.l2cache.ReadExReq_miss_rate::total 0.933180 # miss rate for ReadExReq accesses
762 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274689 # miss rate for demand accesses
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764 system.cpu.l2cache.demand_miss_rate::total 0.308794 # miss rate for demand accesses
765 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274689 # miss rate for overall accesses
766 system.cpu.l2cache.overall_miss_rate::cpu.data 0.309018 # miss rate for overall accesses
767 system.cpu.l2cache.overall_miss_rate::total 0.308794 # miss rate for overall accesses
768 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72695.510500 # average ReadReq miss latency
769 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73430.274820 # average ReadReq miss latency
770 system.cpu.l2cache.ReadReq_avg_miss_latency::total 73425.316346 # average ReadReq miss latency
771 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84901.806950 # average ReadExReq miss latency
772 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84901.806950 # average ReadExReq miss latency
773 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency
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776 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency
777 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75050.360286 # average overall miss latency
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780 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
781 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
782 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
783 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
784 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
785 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
786 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
787 system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
788 system.cpu.l2cache.writebacks::total 66908 # number of writebacks
789 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2762 # number of ReadReq MSHR misses
790 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406521 # number of ReadReq MSHR misses
791 system.cpu.l2cache.ReadReq_mshr_misses::total 409283 # number of ReadReq MSHR misses
792 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses
793 system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses
794 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2762 # number of demand (read+write) MSHR misses
795 system.cpu.l2cache.demand_mshr_misses::cpu.data 473374 # number of demand (read+write) MSHR misses
796 system.cpu.l2cache.demand_mshr_misses::total 476136 # number of demand (read+write) MSHR misses
797 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2762 # number of overall MSHR misses
798 system.cpu.l2cache.overall_mshr_misses::cpu.data 473374 # number of overall MSHR misses
799 system.cpu.l2cache.overall_mshr_misses::total 476136 # number of overall MSHR misses
800 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165956500 # number of ReadReq MSHR miss cycles
801 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24727472750 # number of ReadReq MSHR miss cycles
802 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24893429250 # number of ReadReq MSHR miss cycles
803 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4868551500 # number of ReadExReq MSHR miss cycles
804 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4868551500 # number of ReadExReq MSHR miss cycles
805 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165956500 # number of demand (read+write) MSHR miss cycles
806 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29596024250 # number of demand (read+write) MSHR miss cycles
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808 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165956500 # number of overall MSHR miss cycles
809 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29596024250 # number of overall MSHR miss cycles
810 system.cpu.l2cache.overall_mshr_miss_latency::total 29761980750 # number of overall MSHR miss cycles
811 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for ReadReq accesses
812 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278396 # mshr miss rate for ReadReq accesses
813 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278371 # mshr miss rate for ReadReq accesses
814 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933180 # mshr miss rate for ReadExReq accesses
815 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933180 # mshr miss rate for ReadExReq accesses
816 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for demand accesses
817 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for demand accesses
818 system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses
819 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for overall accesses
820 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for overall accesses
821 system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses
822 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358 # average ReadReq mshr miss latency
823 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910 # average ReadReq mshr miss latency
824 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504 # average ReadReq mshr miss latency
825 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387 # average ReadExReq mshr miss latency
826 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387 # average ReadExReq mshr miss latency
827 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency
828 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency
829 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency
830 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency
831 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency
832 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency
833 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
834 system.cpu.dcache.tags.replacements 1527769 # number of replacements
835 system.cpu.dcache.tags.tagsinuse 4094.584887 # Cycle average of tags in use
836 system.cpu.dcache.tags.total_refs 666211737 # Total number of references to valid blocks.
837 system.cpu.dcache.tags.sampled_refs 1531865 # Sample count of references to valid blocks.
838 system.cpu.dcache.tags.avg_refs 434.902382 # Average number of references to valid blocks.
839 system.cpu.dcache.tags.warmup_cycle 409920250 # Cycle when the warmup percentage was hit.
840 system.cpu.dcache.tags.occ_blocks::cpu.data 4094.584887 # Average occupied blocks per requestor
841 system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy
842 system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy
843 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
844 system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
845 system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
846 system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id
847 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2365 # Occupied blocks per task id
848 system.cpu.dcache.tags.age_task_id_blocks_1024::4 390 # Occupied blocks per task id
849 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
850 system.cpu.dcache.tags.tag_accesses 1339886951 # Number of tag accesses
851 system.cpu.dcache.tags.data_accesses 1339886951 # Number of data accesses
852 system.cpu.dcache.ReadReq_hits::cpu.data 456456827 # number of ReadReq hits
853 system.cpu.dcache.ReadReq_hits::total 456456827 # number of ReadReq hits
854 system.cpu.dcache.WriteReq_hits::cpu.data 209754882 # number of WriteReq hits
855 system.cpu.dcache.WriteReq_hits::total 209754882 # number of WriteReq hits
856 system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits
857 system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits
858 system.cpu.dcache.demand_hits::cpu.data 666211709 # number of demand (read+write) hits
859 system.cpu.dcache.demand_hits::total 666211709 # number of demand (read+write) hits
860 system.cpu.dcache.overall_hits::cpu.data 666211709 # number of overall hits
861 system.cpu.dcache.overall_hits::total 666211709 # number of overall hits
862 system.cpu.dcache.ReadReq_misses::cpu.data 1925791 # number of ReadReq misses
863 system.cpu.dcache.ReadReq_misses::total 1925791 # number of ReadReq misses
864 system.cpu.dcache.WriteReq_misses::cpu.data 1040014 # number of WriteReq misses
865 system.cpu.dcache.WriteReq_misses::total 1040014 # number of WriteReq misses
866 system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
867 system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
868 system.cpu.dcache.demand_misses::cpu.data 2965805 # number of demand (read+write) misses
869 system.cpu.dcache.demand_misses::total 2965805 # number of demand (read+write) misses
870 system.cpu.dcache.overall_misses::cpu.data 2965805 # number of overall misses
871 system.cpu.dcache.overall_misses::total 2965805 # number of overall misses
872 system.cpu.dcache.ReadReq_miss_latency::cpu.data 77884724250 # number of ReadReq miss cycles
873 system.cpu.dcache.ReadReq_miss_latency::total 77884724250 # number of ReadReq miss cycles
874 system.cpu.dcache.WriteReq_miss_latency::cpu.data 53548786128 # number of WriteReq miss cycles
875 system.cpu.dcache.WriteReq_miss_latency::total 53548786128 # number of WriteReq miss cycles
876 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73000 # number of LoadLockedReq miss cycles
877 system.cpu.dcache.LoadLockedReq_miss_latency::total 73000 # number of LoadLockedReq miss cycles
878 system.cpu.dcache.demand_miss_latency::cpu.data 131433510378 # number of demand (read+write) miss cycles
879 system.cpu.dcache.demand_miss_latency::total 131433510378 # number of demand (read+write) miss cycles
880 system.cpu.dcache.overall_miss_latency::cpu.data 131433510378 # number of overall miss cycles
881 system.cpu.dcache.overall_miss_latency::total 131433510378 # number of overall miss cycles
882 system.cpu.dcache.ReadReq_accesses::cpu.data 458382618 # number of ReadReq accesses(hits+misses)
883 system.cpu.dcache.ReadReq_accesses::total 458382618 # number of ReadReq accesses(hits+misses)
884 system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
885 system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
886 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses)
887 system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses)
888 system.cpu.dcache.demand_accesses::cpu.data 669177514 # number of demand (read+write) accesses
889 system.cpu.dcache.demand_accesses::total 669177514 # number of demand (read+write) accesses
890 system.cpu.dcache.overall_accesses::cpu.data 669177514 # number of overall (read+write) accesses
891 system.cpu.dcache.overall_accesses::total 669177514 # number of overall (read+write) accesses
892 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses
893 system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses
894 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004934 # miss rate for WriteReq accesses
895 system.cpu.dcache.WriteReq_miss_rate::total 0.004934 # miss rate for WriteReq accesses
896 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses
897 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses
898 system.cpu.dcache.demand_miss_rate::cpu.data 0.004432 # miss rate for demand accesses
899 system.cpu.dcache.demand_miss_rate::total 0.004432 # miss rate for demand accesses
900 system.cpu.dcache.overall_miss_rate::cpu.data 0.004432 # miss rate for overall accesses
901 system.cpu.dcache.overall_miss_rate::total 0.004432 # miss rate for overall accesses
902 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625 # average ReadReq miss latency
903 system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625 # average ReadReq miss latency
904 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316 # average WriteReq miss latency
905 system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316 # average WriteReq miss latency
906 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73000 # average LoadLockedReq miss latency
907 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73000 # average LoadLockedReq miss latency
908 system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency
909 system.cpu.dcache.demand_avg_miss_latency::total 44316.302110 # average overall miss latency
910 system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency
911 system.cpu.dcache.overall_avg_miss_latency::total 44316.302110 # average overall miss latency
912 system.cpu.dcache.blocked_cycles::no_mshrs 18203 # number of cycles access was blocked
913 system.cpu.dcache.blocked_cycles::no_targets 134 # number of cycles access was blocked
914 system.cpu.dcache.blocked::no_mshrs 374 # number of cycles access was blocked
915 system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
916 system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.671123 # average number of cycles each access was blocked
917 system.cpu.dcache.avg_blocked_cycles::no_targets 134 # average number of cycles each access was blocked
918 system.cpu.dcache.fast_writes 0 # number of fast writes performed
919 system.cpu.dcache.cache_copies 0 # number of cache copies performed
920 system.cpu.dcache.writebacks::writebacks 95977 # number of writebacks
921 system.cpu.dcache.writebacks::total 95977 # number of writebacks
922 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465566 # number of ReadReq MSHR hits
923 system.cpu.dcache.ReadReq_mshr_hits::total 465566 # number of ReadReq MSHR hits
924 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 968374 # number of WriteReq MSHR hits
925 system.cpu.dcache.WriteReq_mshr_hits::total 968374 # number of WriteReq MSHR hits
926 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
927 system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
928 system.cpu.dcache.demand_mshr_hits::cpu.data 1433940 # number of demand (read+write) MSHR hits
929 system.cpu.dcache.demand_mshr_hits::total 1433940 # number of demand (read+write) MSHR hits
930 system.cpu.dcache.overall_mshr_hits::cpu.data 1433940 # number of overall MSHR hits
931 system.cpu.dcache.overall_mshr_hits::total 1433940 # number of overall MSHR hits
932 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460225 # number of ReadReq MSHR misses
933 system.cpu.dcache.ReadReq_mshr_misses::total 1460225 # number of ReadReq MSHR misses
934 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses
935 system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses
936 system.cpu.dcache.demand_mshr_misses::cpu.data 1531865 # number of demand (read+write) MSHR misses
937 system.cpu.dcache.demand_mshr_misses::total 1531865 # number of demand (read+write) MSHR misses
938 system.cpu.dcache.overall_mshr_misses::cpu.data 1531865 # number of overall MSHR misses
939 system.cpu.dcache.overall_mshr_misses::total 1531865 # number of overall MSHR misses
940 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41848820250 # number of ReadReq MSHR miss cycles
941 system.cpu.dcache.ReadReq_mshr_miss_latency::total 41848820250 # number of ReadReq MSHR miss cycles
942 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5798224000 # number of WriteReq MSHR miss cycles
943 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5798224000 # number of WriteReq MSHR miss cycles
944 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47647044250 # number of demand (read+write) MSHR miss cycles
945 system.cpu.dcache.demand_mshr_miss_latency::total 47647044250 # number of demand (read+write) MSHR miss cycles
946 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47647044250 # number of overall MSHR miss cycles
947 system.cpu.dcache.overall_mshr_miss_latency::total 47647044250 # number of overall MSHR miss cycles
948 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses
949 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses
950 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
951 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
952 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses
953 system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses
954 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses
955 system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses
956 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863 # average ReadReq mshr miss latency
957 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863 # average ReadReq mshr miss latency
958 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723 # average WriteReq mshr miss latency
959 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723 # average WriteReq mshr miss latency
960 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency
961 system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency
962 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency
963 system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency
964 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
966 ---------- End Simulation Statistics ----------
projects / gem5.git / blob