tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 readfile=
  20 symbolfile=
  21 work_begin_ckpt_count=0
  22 work_begin_cpu_id_exit=-1
  23 work_begin_exit_count=0
  24 work_cpus_ckpt_count=0
  25 work_end_ckpt_count=0
  26 work_end_exit_count=0
  27 work_item_id=-1
  28 system_port=system.membus.slave[0]
  29
  30 [system.cpu]
  31 type=TimingSimpleCPU
  32 children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
  33 checker=Null
  34 clock=500
  35 cpu_id=0
  36 defer_registration=false
  37 do_checkpoint_insts=true
  38 do_quiesce=true
  39 do_statistics_insts=true
  40 dtb=system.cpu.dtb
  41 function_trace=false
  42 function_trace_start=0
  43 interrupts=system.cpu.interrupts
  44 itb=system.cpu.itb
  45 max_insts_all_threads=0
  46 max_insts_any_thread=0
  47 max_loads_all_threads=0
  48 max_loads_any_thread=0
  49 numThreads=1
  50 phase=0
  51 profile=0
  52 progress_interval=0
  53 system=system
  54 tracer=system.cpu.tracer
  55 workload=system.cpu.workload
  56 dcache_port=system.cpu.dcache.cpu_side
  57 icache_port=system.cpu.icache.cpu_side
  58
  59 [system.cpu.dcache]
  60 type=BaseCache
  61 addr_ranges=0:18446744073709551615
  62 assoc=2
  63 block_size=64
  64 forward_snoops=true
  65 hash_delay=1
  66 is_top_level=true
  67 latency=1000
  68 max_miss_count=0
  69 mshrs=10
  70 prefetch_on_access=false
  71 prefetcher=Null
  72 prioritizeRequests=false
  73 repl=Null
  74 size=262144
  75 subblock_size=0
  76 system=system
  77 tgts_per_mshr=5
  78 trace_addr=0
  79 two_queue=false
  80 write_buffers=8
  81 cpu_side=system.cpu.dcache_port
  82 mem_side=system.cpu.toL2Bus.slave[1]
  83
  84 [system.cpu.dtb]
  85 type=AlphaTLB
  86 size=64
  87
  88 [system.cpu.icache]
  89 type=BaseCache
  90 addr_ranges=0:18446744073709551615
  91 assoc=2
  92 block_size=64
  93 forward_snoops=true
  94 hash_delay=1
  95 is_top_level=true
  96 latency=1000
  97 max_miss_count=0
  98 mshrs=10
  99 prefetch_on_access=false
 100 prefetcher=Null
 101 prioritizeRequests=false
 102 repl=Null
 103 size=131072
 104 subblock_size=0
 105 system=system
 106 tgts_per_mshr=5
 107 trace_addr=0
 108 two_queue=false
 109 write_buffers=8
 110 cpu_side=system.cpu.icache_port
 111 mem_side=system.cpu.toL2Bus.slave[0]
 112
 113 [system.cpu.interrupts]
 114 type=AlphaInterrupts
 115
 116 [system.cpu.itb]
 117 type=AlphaTLB
 118 size=48
 119
 120 [system.cpu.l2cache]
 121 type=BaseCache
 122 addr_ranges=0:18446744073709551615
 123 assoc=2
 124 block_size=64
 125 forward_snoops=true
 126 hash_delay=1
 127 is_top_level=false
 128 latency=10000
 129 max_miss_count=0
 130 mshrs=10
 131 prefetch_on_access=false
 132 prefetcher=Null
 133 prioritizeRequests=false
 134 repl=Null
 135 size=2097152
 136 subblock_size=0
 137 system=system
 138 tgts_per_mshr=5
 139 trace_addr=0
 140 two_queue=false
 141 write_buffers=8
 142 cpu_side=system.cpu.toL2Bus.master[0]
 143 mem_side=system.membus.slave[1]
 144
 145 [system.cpu.toL2Bus]
 146 type=CoherentBus
 147 block_size=64
 148 clock=1000
 149 header_cycles=1
 150 use_default_range=false
 151 width=64
 152 master=system.cpu.l2cache.cpu_side
 153 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 154
 155 [system.cpu.tracer]
 156 type=ExeTracer
 157
 158 [system.cpu.workload]
 159 type=LiveProcess
 160 cmd=perlbmk -I. -I lib lgred.makerand.pl
 161 cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
 162 egid=100
 163 env=
 164 errout=cerr
 165 euid=100
 166 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 167 gid=100
 168 input=cin
 169 max_stack_size=67108864
 170 output=cout
 171 pid=100
 172 ppid=99
 173 simpoint=0
 174 system=system
 175 uid=100
 176
 177 [system.membus]
 178 type=CoherentBus
 179 block_size=64
 180 clock=1000
 181 header_cycles=1
 182 use_default_range=false
 183 width=64
 184 master=system.physmem.port[0]
 185 slave=system.system_port system.cpu.l2cache.mem_side
 186
 187 [system.physmem]
 188 type=SimpleMemory
 189 conf_table_reported=false
 190 file=
 191 in_addr_map=true
 192 latency=30000
 193 latency_var=0
 194 null=false
 195 range=0:134217727
 196 zero=false
 197 port=system.membus.master[0]
 198