2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.769740 # Number of seconds simulated
4 sim_ticks 2769739533000 # Number of ticks simulated
5 final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 964642 # Simulator instruction rate (inst/s)
8 host_op_rate 964642 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1329927483 # Simulator tick rate (ticks/s)
10 host_mem_usage 281524 # Number of bytes of host memory used
11 host_seconds 2082.62 # Real time elapsed on the host
12 sim_insts 2008987605 # Number of instructions simulated
13 sim_ops 2008987605 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.dtb.fetch_hits 0 # ITB hits
38 system.cpu.dtb.fetch_misses 0 # ITB misses
39 system.cpu.dtb.fetch_acv 0 # ITB acv
40 system.cpu.dtb.fetch_accesses 0 # ITB accesses
41 system.cpu.dtb.read_hits 511070026 # DTB read hits
42 system.cpu.dtb.read_misses 418884 # DTB read misses
43 system.cpu.dtb.read_acv 0 # DTB read access violations
44 system.cpu.dtb.read_accesses 511488910 # DTB read accesses
45 system.cpu.dtb.write_hits 210794896 # DTB write hits
46 system.cpu.dtb.write_misses 14581 # DTB write misses
47 system.cpu.dtb.write_acv 0 # DTB write access violations
48 system.cpu.dtb.write_accesses 210809477 # DTB write accesses
49 system.cpu.dtb.data_hits 721864922 # DTB hits
50 system.cpu.dtb.data_misses 433465 # DTB misses
51 system.cpu.dtb.data_acv 0 # DTB access violations
52 system.cpu.dtb.data_accesses 722298387 # DTB accesses
53 system.cpu.itb.fetch_hits 2009421071 # ITB hits
54 system.cpu.itb.fetch_misses 105 # ITB misses
55 system.cpu.itb.fetch_acv 0 # ITB acv
56 system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
57 system.cpu.itb.read_hits 0 # DTB read hits
58 system.cpu.itb.read_misses 0 # DTB read misses
59 system.cpu.itb.read_acv 0 # DTB read access violations
60 system.cpu.itb.read_accesses 0 # DTB read accesses
61 system.cpu.itb.write_hits 0 # DTB write hits
62 system.cpu.itb.write_misses 0 # DTB write misses
63 system.cpu.itb.write_acv 0 # DTB write access violations
64 system.cpu.itb.write_accesses 0 # DTB write accesses
65 system.cpu.itb.data_hits 0 # DTB hits
66 system.cpu.itb.data_misses 0 # DTB misses
67 system.cpu.itb.data_acv 0 # DTB access violations
68 system.cpu.itb.data_accesses 0 # DTB accesses
69 system.cpu.workload.num_syscalls 39 # Number of system calls
70 system.cpu.numCycles 5539479066 # number of cpu cycles simulated
71 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
72 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
73 system.cpu.committedInsts 2008987605 # Number of instructions committed
74 system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
75 system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
76 system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
77 system.cpu.num_func_calls 79910682 # number of times a function call or return occured
78 system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
79 system.cpu.num_int_insts 1779374816 # number of integer instructions
80 system.cpu.num_fp_insts 71831671 # number of float instructions
81 system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
82 system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
83 system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
84 system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
85 system.cpu.num_mem_refs 722298387 # number of memory refs
86 system.cpu.num_load_insts 511488910 # Number of load instructions
87 system.cpu.num_store_insts 210809477 # Number of store instructions
88 system.cpu.num_idle_cycles 0 # Number of idle cycles
89 system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
90 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
91 system.cpu.idle_fraction 0 # Percentage of idle cycles
92 system.cpu.icache.replacements 9046 # number of replacements
93 system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use
94 system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
95 system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
96 system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
97 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
98 system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
99 system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
100 system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy
101 system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
102 system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
103 system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
104 system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits
105 system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits
106 system.cpu.icache.overall_hits::total 2009410475 # number of overall hits
107 system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses
108 system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses
109 system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses
110 system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
111 system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
112 system.cpu.icache.overall_misses::total 10596 # number of overall misses
113 system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles
114 system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles
115 system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles
116 system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles
117 system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles
118 system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles
119 system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
120 system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
121 system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
122 system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses
123 system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses
124 system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses
125 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
126 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
127 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
128 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
129 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
130 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
131 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency
132 system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency
133 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
134 system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency
135 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
136 system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency
137 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
138 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
139 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
140 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
141 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
142 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
143 system.cpu.icache.fast_writes 0 # number of fast writes performed
144 system.cpu.icache.cache_copies 0 # number of cache copies performed
145 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses
146 system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses
147 system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses
148 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
149 system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
150 system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
151 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles
152 system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles
153 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles
154 system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles
155 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles
156 system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles
157 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
158 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
159 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
160 system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
161 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
162 system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
163 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency
164 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency
165 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
166 system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
167 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
168 system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
169 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
170 system.cpu.l2cache.replacements 442570 # number of replacements
171 system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use
172 system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks.
173 system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks.
174 system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks.
175 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
176 system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
177 system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
178 system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
179 system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
180 system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
181 system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
182 system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy
183 system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits
184 system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits
185 system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits
186 system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits
187 system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits
188 system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits
189 system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits
190 system.cpu.l2cache.demand_hits::cpu.inst 8443 # number of demand (read+write) hits
191 system.cpu.l2cache.demand_hits::cpu.data 1056948 # number of demand (read+write) hits
192 system.cpu.l2cache.demand_hits::total 1065391 # number of demand (read+write) hits
193 system.cpu.l2cache.overall_hits::cpu.inst 8443 # number of overall hits
194 system.cpu.l2cache.overall_hits::cpu.data 1056948 # number of overall hits
195 system.cpu.l2cache.overall_hits::total 1065391 # number of overall hits
196 system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses
197 system.cpu.l2cache.ReadReq_misses::cpu.data 406323 # number of ReadReq misses
198 system.cpu.l2cache.ReadReq_misses::total 408476 # number of ReadReq misses
199 system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses
200 system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses
201 system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses
202 system.cpu.l2cache.demand_misses::cpu.data 473196 # number of demand (read+write) misses
203 system.cpu.l2cache.demand_misses::total 475349 # number of demand (read+write) misses
204 system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
205 system.cpu.l2cache.overall_misses::cpu.data 473196 # number of overall misses
206 system.cpu.l2cache.overall_misses::total 475349 # number of overall misses
207 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles
208 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21128799000 # number of ReadReq miss cycles
209 system.cpu.l2cache.ReadReq_miss_latency::total 21240755000 # number of ReadReq miss cycles
210 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles
211 system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles
212 system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles
213 system.cpu.l2cache.demand_miss_latency::cpu.data 24606195000 # number of demand (read+write) miss cycles
214 system.cpu.l2cache.demand_miss_latency::total 24718151000 # number of demand (read+write) miss cycles
215 system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles
216 system.cpu.l2cache.overall_miss_latency::cpu.data 24606195000 # number of overall miss cycles
217 system.cpu.l2cache.overall_miss_latency::total 24718151000 # number of overall miss cycles
218 system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses)
219 system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses)
220 system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses)
221 system.cpu.l2cache.Writeback_accesses::writebacks 96129 # number of Writeback accesses(hits+misses)
222 system.cpu.l2cache.Writeback_accesses::total 96129 # number of Writeback accesses(hits+misses)
223 system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses)
224 system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses)
225 system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses
226 system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses
227 system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses
228 system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses
229 system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses
230 system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses
231 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203190 # miss rate for ReadReq accesses
232 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278648 # miss rate for ReadReq accesses
233 system.cpu.l2cache.ReadReq_miss_rate::total 0.278104 # miss rate for ReadReq accesses
234 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses
235 system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses
236 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses
237 system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses
238 system.cpu.l2cache.demand_miss_rate::total 0.308520 # miss rate for demand accesses
239 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses
240 system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses
241 system.cpu.l2cache.overall_miss_rate::total 0.308520 # miss rate for overall accesses
242 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
243 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383 # average ReadReq miss latency
244 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344 # average ReadReq miss latency
245 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
246 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
247 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
248 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency
249 system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311 # average overall miss latency
250 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
251 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency
252 system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311 # average overall miss latency
253 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
254 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
255 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
256 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
257 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
258 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
259 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
260 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
261 system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
262 system.cpu.l2cache.writebacks::total 66908 # number of writebacks
263 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses
264 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406323 # number of ReadReq MSHR misses
265 system.cpu.l2cache.ReadReq_mshr_misses::total 408476 # number of ReadReq MSHR misses
266 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses
267 system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses
268 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
269 system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses
270 system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses
271 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
272 system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses
273 system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses
274 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles
275 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles
276 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles
277 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
278 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
279 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles
280 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles
281 system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles
282 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles
283 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles
284 system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles
285 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses
286 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses
287 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses
288 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
289 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses
290 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses
291 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses
292 system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses
293 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses
294 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses
295 system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses
296 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
297 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency
298 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency
299 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
300 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
301 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
302 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
303 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
304 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
305 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
306 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
307 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
308 system.cpu.dcache.replacements 1526048 # number of replacements
309 system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
310 system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
311 system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
312 system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
313 system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
314 system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
315 system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
316 system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
317 system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
318 system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
319 system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
320 system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits
321 system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits
322 system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits
323 system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits
324 system.cpu.dcache.overall_hits::total 720334778 # number of overall hits
325 system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses
326 system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses
327 system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses
328 system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses
329 system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses
330 system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
331 system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
332 system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
333 system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles
334 system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
335 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
336 system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
337 system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles
338 system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles
339 system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles
340 system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles
341 system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
342 system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
343 system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
344 system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
345 system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses
346 system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses
347 system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses
348 system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses
349 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses
350 system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses
351 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses
352 system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses
353 system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses
354 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
355 system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
356 system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
357 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
358 system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
359 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
360 system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
361 system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
362 system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency
363 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
364 system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency
365 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
366 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
367 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
368 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
369 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
370 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
371 system.cpu.dcache.fast_writes 0 # number of fast writes performed
372 system.cpu.dcache.cache_copies 0 # number of cache copies performed
373 system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks
374 system.cpu.dcache.writebacks::total 96129 # number of writebacks
375 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses
376 system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses
377 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses
378 system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses
379 system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses
380 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
381 system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
382 system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
383 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles
384 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles
385 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
386 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
387 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles
388 system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles
389 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles
390 system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles
391 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
392 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
393 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
394 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses
395 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses
396 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
397 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
398 system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
399 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency
400 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency
401 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
402 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
403 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
404 system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
405 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
406 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
407 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
409 ---------- End Simulation Statistics ----------
projects / gem5.git / blob