2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.769740 # Number of seconds simulated
4 sim_ticks 2769739533000 # Number of ticks simulated
5 final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1559352 # Simulator instruction rate (inst/s)
8 host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2149839105 # Simulator tick rate (ticks/s)
10 host_mem_usage 233980 # Number of bytes of host memory used
11 host_seconds 1288.35 # Real time elapsed on the host
12 sim_insts 2008987605 # Number of instructions simulated
13 sim_ops 2008987605 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
37 system.membus.throughput 12529860 # Throughput (bytes/s)
38 system.membus.trans_dist::ReadReq 408476 # Transaction distribution
39 system.membus.trans_dist::ReadResp 408476 # Transaction distribution
40 system.membus.trans_dist::Writeback 66908 # Transaction distribution
41 system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
42 system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
43 system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes)
44 system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes)
45 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes)
46 system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes)
47 system.membus.data_through_bus 34704448 # Total data (bytes)
48 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
49 system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
50 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
51 system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks)
52 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
53 system.cpu.dtb.fetch_hits 0 # ITB hits
54 system.cpu.dtb.fetch_misses 0 # ITB misses
55 system.cpu.dtb.fetch_acv 0 # ITB acv
56 system.cpu.dtb.fetch_accesses 0 # ITB accesses
57 system.cpu.dtb.read_hits 511070026 # DTB read hits
58 system.cpu.dtb.read_misses 418884 # DTB read misses
59 system.cpu.dtb.read_acv 0 # DTB read access violations
60 system.cpu.dtb.read_accesses 511488910 # DTB read accesses
61 system.cpu.dtb.write_hits 210794896 # DTB write hits
62 system.cpu.dtb.write_misses 14581 # DTB write misses
63 system.cpu.dtb.write_acv 0 # DTB write access violations
64 system.cpu.dtb.write_accesses 210809477 # DTB write accesses
65 system.cpu.dtb.data_hits 721864922 # DTB hits
66 system.cpu.dtb.data_misses 433465 # DTB misses
67 system.cpu.dtb.data_acv 0 # DTB access violations
68 system.cpu.dtb.data_accesses 722298387 # DTB accesses
69 system.cpu.itb.fetch_hits 2009421071 # ITB hits
70 system.cpu.itb.fetch_misses 105 # ITB misses
71 system.cpu.itb.fetch_acv 0 # ITB acv
72 system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
73 system.cpu.itb.read_hits 0 # DTB read hits
74 system.cpu.itb.read_misses 0 # DTB read misses
75 system.cpu.itb.read_acv 0 # DTB read access violations
76 system.cpu.itb.read_accesses 0 # DTB read accesses
77 system.cpu.itb.write_hits 0 # DTB write hits
78 system.cpu.itb.write_misses 0 # DTB write misses
79 system.cpu.itb.write_acv 0 # DTB write access violations
80 system.cpu.itb.write_accesses 0 # DTB write accesses
81 system.cpu.itb.data_hits 0 # DTB hits
82 system.cpu.itb.data_misses 0 # DTB misses
83 system.cpu.itb.data_acv 0 # DTB access violations
84 system.cpu.itb.data_accesses 0 # DTB accesses
85 system.cpu.workload.num_syscalls 39 # Number of system calls
86 system.cpu.numCycles 5539479066 # number of cpu cycles simulated
87 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
88 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
89 system.cpu.committedInsts 2008987605 # Number of instructions committed
90 system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
91 system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
92 system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
93 system.cpu.num_func_calls 79910682 # number of times a function call or return occured
94 system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
95 system.cpu.num_int_insts 1779374816 # number of integer instructions
96 system.cpu.num_fp_insts 71831671 # number of float instructions
97 system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
98 system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
99 system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
100 system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
101 system.cpu.num_mem_refs 722298387 # number of memory refs
102 system.cpu.num_load_insts 511488910 # Number of load instructions
103 system.cpu.num_store_insts 210809477 # Number of store instructions
104 system.cpu.num_idle_cycles 0 # Number of idle cycles
105 system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
106 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
107 system.cpu.idle_fraction 0 # Percentage of idle cycles
108 system.cpu.icache.replacements 9046 # number of replacements
109 system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use
110 system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
111 system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
112 system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
113 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
114 system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
115 system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
116 system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy
117 system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
118 system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
119 system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
120 system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits
121 system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits
122 system.cpu.icache.overall_hits::total 2009410475 # number of overall hits
123 system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses
124 system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses
125 system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses
126 system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
127 system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
128 system.cpu.icache.overall_misses::total 10596 # number of overall misses
129 system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles
130 system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles
131 system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles
132 system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles
133 system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles
134 system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles
135 system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
136 system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
137 system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
138 system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses
139 system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses
140 system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses
141 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
142 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
143 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
144 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
145 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
146 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
147 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency
148 system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency
149 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
150 system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency
151 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
152 system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency
153 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
154 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
155 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
156 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
157 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
158 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
159 system.cpu.icache.fast_writes 0 # number of fast writes performed
160 system.cpu.icache.cache_copies 0 # number of cache copies performed
161 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses
162 system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses
163 system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses
164 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
165 system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
166 system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
167 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles
168 system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles
169 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles
170 system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles
171 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles
172 system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles
173 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
174 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
175 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
176 system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
177 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
178 system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
179 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency
180 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency
181 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
182 system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
183 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
184 system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
185 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
186 system.cpu.l2cache.replacements 442570 # number of replacements
187 system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use
188 system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks.
189 system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks.
190 system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks.
191 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
192 system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
193 system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
194 system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
195 system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
196 system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
197 system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
198 system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy
199 system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits
200 system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits
201 system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits
202 system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits
203 system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits
204 system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits
205 system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits
206 system.cpu.l2cache.demand_hits::cpu.inst 8443 # number of demand (read+write) hits
207 system.cpu.l2cache.demand_hits::cpu.data 1056948 # number of demand (read+write) hits
208 system.cpu.l2cache.demand_hits::total 1065391 # number of demand (read+write) hits
209 system.cpu.l2cache.overall_hits::cpu.inst 8443 # number of overall hits
210 system.cpu.l2cache.overall_hits::cpu.data 1056948 # number of overall hits
211 system.cpu.l2cache.overall_hits::total 1065391 # number of overall hits
212 system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses
213 system.cpu.l2cache.ReadReq_misses::cpu.data 406323 # number of ReadReq misses
214 system.cpu.l2cache.ReadReq_misses::total 408476 # number of ReadReq misses
215 system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses
216 system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses
217 system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses
218 system.cpu.l2cache.demand_misses::cpu.data 473196 # number of demand (read+write) misses
219 system.cpu.l2cache.demand_misses::total 475349 # number of demand (read+write) misses
220 system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
221 system.cpu.l2cache.overall_misses::cpu.data 473196 # number of overall misses
222 system.cpu.l2cache.overall_misses::total 475349 # number of overall misses
223 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles
224 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21128799000 # number of ReadReq miss cycles
225 system.cpu.l2cache.ReadReq_miss_latency::total 21240755000 # number of ReadReq miss cycles
226 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles
227 system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles
228 system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles
229 system.cpu.l2cache.demand_miss_latency::cpu.data 24606195000 # number of demand (read+write) miss cycles
230 system.cpu.l2cache.demand_miss_latency::total 24718151000 # number of demand (read+write) miss cycles
231 system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles
232 system.cpu.l2cache.overall_miss_latency::cpu.data 24606195000 # number of overall miss cycles
233 system.cpu.l2cache.overall_miss_latency::total 24718151000 # number of overall miss cycles
234 system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses)
235 system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses)
236 system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses)
237 system.cpu.l2cache.Writeback_accesses::writebacks 96129 # number of Writeback accesses(hits+misses)
238 system.cpu.l2cache.Writeback_accesses::total 96129 # number of Writeback accesses(hits+misses)
239 system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses)
240 system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses)
241 system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses
242 system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses
243 system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses
244 system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses
245 system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses
246 system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses
247 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203190 # miss rate for ReadReq accesses
248 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278648 # miss rate for ReadReq accesses
249 system.cpu.l2cache.ReadReq_miss_rate::total 0.278104 # miss rate for ReadReq accesses
250 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses
251 system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses
252 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses
253 system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses
254 system.cpu.l2cache.demand_miss_rate::total 0.308520 # miss rate for demand accesses
255 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses
256 system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses
257 system.cpu.l2cache.overall_miss_rate::total 0.308520 # miss rate for overall accesses
258 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
259 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383 # average ReadReq miss latency
260 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344 # average ReadReq miss latency
261 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
262 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
263 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
264 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency
265 system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311 # average overall miss latency
266 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
267 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency
268 system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311 # average overall miss latency
269 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
270 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
271 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
272 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
273 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
274 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
275 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
276 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
277 system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
278 system.cpu.l2cache.writebacks::total 66908 # number of writebacks
279 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses
280 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406323 # number of ReadReq MSHR misses
281 system.cpu.l2cache.ReadReq_mshr_misses::total 408476 # number of ReadReq MSHR misses
282 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses
283 system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses
284 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
285 system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses
286 system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses
287 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
288 system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses
289 system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses
290 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles
291 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles
292 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles
293 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
294 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
295 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles
296 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles
297 system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles
298 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles
299 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles
300 system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles
301 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses
302 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses
303 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses
304 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
305 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses
306 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses
307 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses
308 system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses
309 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses
310 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses
311 system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses
312 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
313 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency
314 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency
315 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
316 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
317 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
318 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
319 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
320 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
321 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
322 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
323 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
324 system.cpu.dcache.replacements 1526048 # number of replacements
325 system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
326 system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
327 system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
328 system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
329 system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
330 system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
331 system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
332 system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
333 system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
334 system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
335 system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
336 system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits
337 system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits
338 system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits
339 system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits
340 system.cpu.dcache.overall_hits::total 720334778 # number of overall hits
341 system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses
342 system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses
343 system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses
344 system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses
345 system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses
346 system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
347 system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
348 system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
349 system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles
350 system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
351 system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
352 system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
353 system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles
354 system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles
355 system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles
356 system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles
357 system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
358 system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
359 system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
360 system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
361 system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses
362 system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses
363 system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses
364 system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses
365 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses
366 system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses
367 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses
368 system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses
369 system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses
370 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
371 system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
372 system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
373 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
374 system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
375 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
376 system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
377 system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
378 system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency
379 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
380 system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency
381 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
382 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
383 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
384 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
385 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
386 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
387 system.cpu.dcache.fast_writes 0 # number of fast writes performed
388 system.cpu.dcache.cache_copies 0 # number of cache copies performed
389 system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks
390 system.cpu.dcache.writebacks::total 96129 # number of writebacks
391 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses
392 system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses
393 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses
394 system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses
395 system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses
396 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
397 system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
398 system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
399 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles
400 system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles
401 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
402 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
403 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles
404 system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles
405 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles
406 system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles
407 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
408 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
409 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
410 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses
411 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses
412 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
413 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
414 system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
415 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency
416 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency
417 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
418 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
419 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
420 system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
421 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
422 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
423 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
424 system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s)
425 system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution
426 system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution
427 system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
428 system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
429 system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
430 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes)
431 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes)
432 system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes)
433 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes)
434 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes)
435 system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes)
436 system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
437 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
438 system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
439 system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
440 system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks)
441 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
442 system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks)
443 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
445 ---------- End Simulation Statistics ----------
projects / gem5.git / blob