tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 num_work_ids=16
  27 readfile=
  28 symbolfile=
  29 work_begin_ckpt_count=0
  30 work_begin_cpu_id_exit=-1
  31 work_begin_exit_count=0
  32 work_cpus_ckpt_count=0
  33 work_end_ckpt_count=0
  34 work_end_exit_count=0
  35 work_item_id=-1
  36 system_port=system.membus.slave[0]
  37
  38 [system.clk_domain]
  39 type=SrcClockDomain
  40 clock=1000
  41 domain_id=-1
  42 eventq_index=0
  43 init_perf_level=0
  44 voltage_domain=system.voltage_domain
  45
  46 [system.cpu]
  47 type=MinorCPU
  48 children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  49 branchPred=system.cpu.branchPred
  50 checker=Null
  51 clk_domain=system.cpu_clk_domain
  52 cpu_id=0
  53 decodeCycleInput=true
  54 decodeInputBufferSize=3
  55 decodeInputWidth=2
  56 decodeToExecuteForwardDelay=1
  57 do_checkpoint_insts=true
  58 do_quiesce=true
  59 do_statistics_insts=true
  60 dstage2_mmu=system.cpu.dstage2_mmu
  61 dtb=system.cpu.dtb
  62 enableIdling=true
  63 eventq_index=0
  64 executeAllowEarlyMemoryIssue=true
  65 executeBranchDelay=1
  66 executeCommitLimit=2
  67 executeCycleInput=true
  68 executeFuncUnits=system.cpu.executeFuncUnits
  69 executeInputBufferSize=7
  70 executeInputWidth=2
  71 executeIssueLimit=2
  72 executeLSQMaxStoreBufferStoresPerCycle=2
  73 executeLSQRequestsQueueSize=1
  74 executeLSQStoreBufferSize=5
  75 executeLSQTransfersQueueSize=2
  76 executeMaxAccessesInMemory=2
  77 executeMemoryCommitLimit=1
  78 executeMemoryIssueLimit=1
  79 executeMemoryWidth=0
  80 executeSetTraceTimeOnCommit=true
  81 executeSetTraceTimeOnIssue=false
  82 fetch1FetchLimit=1
  83 fetch1LineSnapWidth=0
  84 fetch1LineWidth=0
  85 fetch1ToFetch2BackwardDelay=1
  86 fetch1ToFetch2ForwardDelay=1
  87 fetch2CycleInput=true
  88 fetch2InputBufferSize=2
  89 fetch2ToDecodeForwardDelay=1
  90 function_trace=false
  91 function_trace_start=0
  92 interrupts=system.cpu.interrupts
  93 isa=system.cpu.isa
  94 istage2_mmu=system.cpu.istage2_mmu
  95 itb=system.cpu.itb
  96 max_insts_all_threads=0
  97 max_insts_any_thread=0
  98 max_loads_all_threads=0
  99 max_loads_any_thread=0
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 simpoint_start_insts=
 104 socket_id=0
 105 switched_out=false
 106 system=system
 107 tracer=system.cpu.tracer
 108 workload=system.cpu.workload
 109 dcache_port=system.cpu.dcache.cpu_side
 110 icache_port=system.cpu.icache.cpu_side
 111
 112 [system.cpu.branchPred]
 113 type=BranchPredictor
 114 BTBEntries=4096
 115 BTBTagSize=16
 116 RASSize=16
 117 choiceCtrBits=2
 118 choicePredictorSize=8192
 119 eventq_index=0
 120 globalCtrBits=2
 121 globalPredictorSize=8192
 122 instShiftAmt=2
 123 localCtrBits=2
 124 localHistoryTableSize=2048
 125 localPredictorSize=2048
 126 numThreads=1
 127 predType=tournament
 128
 129 [system.cpu.dcache]
 130 type=BaseCache
 131 children=tags
 132 addr_ranges=0:18446744073709551615
 133 assoc=2
 134 clk_domain=system.cpu_clk_domain
 135 eventq_index=0
 136 forward_snoops=true
 137 hit_latency=2
 138 is_top_level=true
 139 max_miss_count=0
 140 mshrs=4
 141 prefetch_on_access=false
 142 prefetcher=Null
 143 response_latency=2
 144 sequential_access=false
 145 size=262144
 146 system=system
 147 tags=system.cpu.dcache.tags
 148 tgts_per_mshr=20
 149 two_queue=false
 150 write_buffers=8
 151 cpu_side=system.cpu.dcache_port
 152 mem_side=system.cpu.toL2Bus.slave[1]
 153
 154 [system.cpu.dcache.tags]
 155 type=LRU
 156 assoc=2
 157 block_size=64
 158 clk_domain=system.cpu_clk_domain
 159 eventq_index=0
 160 hit_latency=2
 161 sequential_access=false
 162 size=262144
 163
 164 [system.cpu.dstage2_mmu]
 165 type=ArmStage2MMU
 166 children=stage2_tlb
 167 eventq_index=0
 168 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 169 tlb=system.cpu.dtb
 170
 171 [system.cpu.dstage2_mmu.stage2_tlb]
 172 type=ArmTLB
 173 children=walker
 174 eventq_index=0
 175 is_stage2=true
 176 size=32
 177 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 178
 179 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 180 type=ArmTableWalker
 181 clk_domain=system.cpu_clk_domain
 182 eventq_index=0
 183 is_stage2=true
 184 num_squash_per_cycle=2
 185 sys=system
 186 port=system.cpu.toL2Bus.slave[5]
 187
 188 [system.cpu.dtb]
 189 type=ArmTLB
 190 children=walker
 191 eventq_index=0
 192 is_stage2=false
 193 size=64
 194 walker=system.cpu.dtb.walker
 195
 196 [system.cpu.dtb.walker]
 197 type=ArmTableWalker
 198 clk_domain=system.cpu_clk_domain
 199 eventq_index=0
 200 is_stage2=false
 201 num_squash_per_cycle=2
 202 sys=system
 203 port=system.cpu.toL2Bus.slave[3]
 204
 205 [system.cpu.executeFuncUnits]
 206 type=MinorFUPool
 207 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 208 eventq_index=0
 209 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 210
 211 [system.cpu.executeFuncUnits.funcUnits0]
 212 type=MinorFU
 213 children=opClasses timings
 214 cantForwardFromFUIndices=
 215 eventq_index=0
 216 issueLat=1
 217 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 218 opLat=3
 219 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 220
 221 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 222 type=MinorOpClassSet
 223 children=opClasses
 224 eventq_index=0
 225 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 226
 227 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 228 type=MinorOpClass
 229 eventq_index=0
 230 opClass=IntAlu
 231
 232 [system.cpu.executeFuncUnits.funcUnits0.timings]
 233 type=MinorFUTiming
 234 children=opClasses
 235 description=Int
 236 eventq_index=0
 237 extraAssumedLat=0
 238 extraCommitLat=0
 239 extraCommitLatExpr=Null
 240 mask=0
 241 match=0
 242 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 243 srcRegsRelativeLats=2
 244 suppress=false
 245
 246 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 247 type=MinorOpClassSet
 248 eventq_index=0
 249 opClasses=
 250
 251 [system.cpu.executeFuncUnits.funcUnits1]
 252 type=MinorFU
 253 children=opClasses timings
 254 cantForwardFromFUIndices=
 255 eventq_index=0
 256 issueLat=1
 257 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 258 opLat=3
 259 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 260
 261 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 262 type=MinorOpClassSet
 263 children=opClasses
 264 eventq_index=0
 265 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 266
 267 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 268 type=MinorOpClass
 269 eventq_index=0
 270 opClass=IntAlu
 271
 272 [system.cpu.executeFuncUnits.funcUnits1.timings]
 273 type=MinorFUTiming
 274 children=opClasses
 275 description=Int
 276 eventq_index=0
 277 extraAssumedLat=0
 278 extraCommitLat=0
 279 extraCommitLatExpr=Null
 280 mask=0
 281 match=0
 282 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 283 srcRegsRelativeLats=2
 284 suppress=false
 285
 286 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 287 type=MinorOpClassSet
 288 eventq_index=0
 289 opClasses=
 290
 291 [system.cpu.executeFuncUnits.funcUnits2]
 292 type=MinorFU
 293 children=opClasses timings
 294 cantForwardFromFUIndices=
 295 eventq_index=0
 296 issueLat=1
 297 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 298 opLat=3
 299 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 300
 301 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 302 type=MinorOpClassSet
 303 children=opClasses
 304 eventq_index=0
 305 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 306
 307 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 308 type=MinorOpClass
 309 eventq_index=0
 310 opClass=IntMult
 311
 312 [system.cpu.executeFuncUnits.funcUnits2.timings]
 313 type=MinorFUTiming
 314 children=opClasses
 315 description=Mul
 316 eventq_index=0
 317 extraAssumedLat=0
 318 extraCommitLat=0
 319 extraCommitLatExpr=Null
 320 mask=0
 321 match=0
 322 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 323 srcRegsRelativeLats=0
 324 suppress=false
 325
 326 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 327 type=MinorOpClassSet
 328 eventq_index=0
 329 opClasses=
 330
 331 [system.cpu.executeFuncUnits.funcUnits3]
 332 type=MinorFU
 333 children=opClasses
 334 cantForwardFromFUIndices=
 335 eventq_index=0
 336 issueLat=9
 337 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 338 opLat=9
 339 timings=
 340
 341 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 342 type=MinorOpClassSet
 343 children=opClasses
 344 eventq_index=0
 345 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 346
 347 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 348 type=MinorOpClass
 349 eventq_index=0
 350 opClass=IntDiv
 351
 352 [system.cpu.executeFuncUnits.funcUnits4]
 353 type=MinorFU
 354 children=opClasses timings
 355 cantForwardFromFUIndices=
 356 eventq_index=0
 357 issueLat=1
 358 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 359 opLat=6
 360 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 361
 362 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 363 type=MinorOpClassSet
 364 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 365 eventq_index=0
 366 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 367
 368 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 369 type=MinorOpClass
 370 eventq_index=0
 371 opClass=FloatAdd
 372
 373 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 374 type=MinorOpClass
 375 eventq_index=0
 376 opClass=FloatCmp
 377
 378 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 379 type=MinorOpClass
 380 eventq_index=0
 381 opClass=FloatCvt
 382
 383 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 384 type=MinorOpClass
 385 eventq_index=0
 386 opClass=FloatMult
 387
 388 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 389 type=MinorOpClass
 390 eventq_index=0
 391 opClass=FloatDiv
 392
 393 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 394 type=MinorOpClass
 395 eventq_index=0
 396 opClass=FloatSqrt
 397
 398 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 399 type=MinorOpClass
 400 eventq_index=0
 401 opClass=SimdAdd
 402
 403 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 404 type=MinorOpClass
 405 eventq_index=0
 406 opClass=SimdAddAcc
 407
 408 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 409 type=MinorOpClass
 410 eventq_index=0
 411 opClass=SimdAlu
 412
 413 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 414 type=MinorOpClass
 415 eventq_index=0
 416 opClass=SimdCmp
 417
 418 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 419 type=MinorOpClass
 420 eventq_index=0
 421 opClass=SimdCvt
 422
 423 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 424 type=MinorOpClass
 425 eventq_index=0
 426 opClass=SimdMisc
 427
 428 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 429 type=MinorOpClass
 430 eventq_index=0
 431 opClass=SimdMult
 432
 433 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 434 type=MinorOpClass
 435 eventq_index=0
 436 opClass=SimdMultAcc
 437
 438 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 439 type=MinorOpClass
 440 eventq_index=0
 441 opClass=SimdShift
 442
 443 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 444 type=MinorOpClass
 445 eventq_index=0
 446 opClass=SimdShiftAcc
 447
 448 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 449 type=MinorOpClass
 450 eventq_index=0
 451 opClass=SimdSqrt
 452
 453 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 454 type=MinorOpClass
 455 eventq_index=0
 456 opClass=SimdFloatAdd
 457
 458 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 459 type=MinorOpClass
 460 eventq_index=0
 461 opClass=SimdFloatAlu
 462
 463 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 464 type=MinorOpClass
 465 eventq_index=0
 466 opClass=SimdFloatCmp
 467
 468 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 469 type=MinorOpClass
 470 eventq_index=0
 471 opClass=SimdFloatCvt
 472
 473 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 474 type=MinorOpClass
 475 eventq_index=0
 476 opClass=SimdFloatDiv
 477
 478 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 479 type=MinorOpClass
 480 eventq_index=0
 481 opClass=SimdFloatMisc
 482
 483 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 484 type=MinorOpClass
 485 eventq_index=0
 486 opClass=SimdFloatMult
 487
 488 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 489 type=MinorOpClass
 490 eventq_index=0
 491 opClass=SimdFloatMultAcc
 492
 493 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 494 type=MinorOpClass
 495 eventq_index=0
 496 opClass=SimdFloatSqrt
 497
 498 [system.cpu.executeFuncUnits.funcUnits4.timings]
 499 type=MinorFUTiming
 500 children=opClasses
 501 description=FloatSimd
 502 eventq_index=0
 503 extraAssumedLat=0
 504 extraCommitLat=0
 505 extraCommitLatExpr=Null
 506 mask=0
 507 match=0
 508 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 509 srcRegsRelativeLats=2
 510 suppress=false
 511
 512 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 513 type=MinorOpClassSet
 514 eventq_index=0
 515 opClasses=
 516
 517 [system.cpu.executeFuncUnits.funcUnits5]
 518 type=MinorFU
 519 children=opClasses timings
 520 cantForwardFromFUIndices=
 521 eventq_index=0
 522 issueLat=1
 523 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 524 opLat=1
 525 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 526
 527 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 528 type=MinorOpClassSet
 529 children=opClasses0 opClasses1
 530 eventq_index=0
 531 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 532
 533 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 534 type=MinorOpClass
 535 eventq_index=0
 536 opClass=MemRead
 537
 538 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 539 type=MinorOpClass
 540 eventq_index=0
 541 opClass=MemWrite
 542
 543 [system.cpu.executeFuncUnits.funcUnits5.timings]
 544 type=MinorFUTiming
 545 children=opClasses
 546 description=Mem
 547 eventq_index=0
 548 extraAssumedLat=2
 549 extraCommitLat=0
 550 extraCommitLatExpr=Null
 551 mask=0
 552 match=0
 553 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 554 srcRegsRelativeLats=1
 555 suppress=false
 556
 557 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 558 type=MinorOpClassSet
 559 eventq_index=0
 560 opClasses=
 561
 562 [system.cpu.executeFuncUnits.funcUnits6]
 563 type=MinorFU
 564 children=opClasses
 565 cantForwardFromFUIndices=
 566 eventq_index=0
 567 issueLat=1
 568 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 569 opLat=1
 570 timings=
 571
 572 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 573 type=MinorOpClassSet
 574 children=opClasses0 opClasses1
 575 eventq_index=0
 576 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 577
 578 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 579 type=MinorOpClass
 580 eventq_index=0
 581 opClass=IprAccess
 582
 583 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 584 type=MinorOpClass
 585 eventq_index=0
 586 opClass=InstPrefetch
 587
 588 [system.cpu.icache]
 589 type=BaseCache
 590 children=tags
 591 addr_ranges=0:18446744073709551615
 592 assoc=2
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_snoops=true
 596 hit_latency=2
 597 is_top_level=true
 598 max_miss_count=0
 599 mshrs=4
 600 prefetch_on_access=false
 601 prefetcher=Null
 602 response_latency=2
 603 sequential_access=false
 604 size=131072
 605 system=system
 606 tags=system.cpu.icache.tags
 607 tgts_per_mshr=20
 608 two_queue=false
 609 write_buffers=8
 610 cpu_side=system.cpu.icache_port
 611 mem_side=system.cpu.toL2Bus.slave[0]
 612
 613 [system.cpu.icache.tags]
 614 type=LRU
 615 assoc=2
 616 block_size=64
 617 clk_domain=system.cpu_clk_domain
 618 eventq_index=0
 619 hit_latency=2
 620 sequential_access=false
 621 size=131072
 622
 623 [system.cpu.interrupts]
 624 type=ArmInterrupts
 625 eventq_index=0
 626
 627 [system.cpu.isa]
 628 type=ArmISA
 629 eventq_index=0
 630 fpsid=1090793632
 631 id_aa64afr0_el1=0
 632 id_aa64afr1_el1=0
 633 id_aa64dfr0_el1=1052678
 634 id_aa64dfr1_el1=0
 635 id_aa64isar0_el1=0
 636 id_aa64isar1_el1=0
 637 id_aa64mmfr0_el1=15728642
 638 id_aa64mmfr1_el1=0
 639 id_aa64pfr0_el1=17
 640 id_aa64pfr1_el1=0
 641 id_isar0=34607377
 642 id_isar1=34677009
 643 id_isar2=555950401
 644 id_isar3=17899825
 645 id_isar4=268501314
 646 id_isar5=0
 647 id_mmfr0=270536963
 648 id_mmfr1=0
 649 id_mmfr2=19070976
 650 id_mmfr3=34611729
 651 id_pfr0=49
 652 id_pfr1=4113
 653 midr=1091551472
 654 system=system
 655
 656 [system.cpu.istage2_mmu]
 657 type=ArmStage2MMU
 658 children=stage2_tlb
 659 eventq_index=0
 660 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 661 tlb=system.cpu.itb
 662
 663 [system.cpu.istage2_mmu.stage2_tlb]
 664 type=ArmTLB
 665 children=walker
 666 eventq_index=0
 667 is_stage2=true
 668 size=32
 669 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 670
 671 [system.cpu.istage2_mmu.stage2_tlb.walker]
 672 type=ArmTableWalker
 673 clk_domain=system.cpu_clk_domain
 674 eventq_index=0
 675 is_stage2=true
 676 num_squash_per_cycle=2
 677 sys=system
 678 port=system.cpu.toL2Bus.slave[4]
 679
 680 [system.cpu.itb]
 681 type=ArmTLB
 682 children=walker
 683 eventq_index=0
 684 is_stage2=false
 685 size=64
 686 walker=system.cpu.itb.walker
 687
 688 [system.cpu.itb.walker]
 689 type=ArmTableWalker
 690 clk_domain=system.cpu_clk_domain
 691 eventq_index=0
 692 is_stage2=false
 693 num_squash_per_cycle=2
 694 sys=system
 695 port=system.cpu.toL2Bus.slave[2]
 696
 697 [system.cpu.l2cache]
 698 type=BaseCache
 699 children=tags
 700 addr_ranges=0:18446744073709551615
 701 assoc=8
 702 clk_domain=system.cpu_clk_domain
 703 eventq_index=0
 704 forward_snoops=true
 705 hit_latency=20
 706 is_top_level=false
 707 max_miss_count=0
 708 mshrs=20
 709 prefetch_on_access=false
 710 prefetcher=Null
 711 response_latency=20
 712 sequential_access=false
 713 size=2097152
 714 system=system
 715 tags=system.cpu.l2cache.tags
 716 tgts_per_mshr=12
 717 two_queue=false
 718 write_buffers=8
 719 cpu_side=system.cpu.toL2Bus.master[0]
 720 mem_side=system.membus.slave[1]
 721
 722 [system.cpu.l2cache.tags]
 723 type=LRU
 724 assoc=8
 725 block_size=64
 726 clk_domain=system.cpu_clk_domain
 727 eventq_index=0
 728 hit_latency=20
 729 sequential_access=false
 730 size=2097152
 731
 732 [system.cpu.toL2Bus]
 733 type=CoherentBus
 734 clk_domain=system.cpu_clk_domain
 735 eventq_index=0
 736 header_cycles=1
 737 system=system
 738 use_default_range=false
 739 width=32
 740 master=system.cpu.l2cache.cpu_side
 741 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 742
 743 [system.cpu.tracer]
 744 type=ExeTracer
 745 eventq_index=0
 746
 747 [system.cpu.workload]
 748 type=LiveProcess
 749 cmd=perlbmk -I. -I lib lgred.makerand.pl
 750 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
 751 egid=100
 752 env=
 753 errout=cerr
 754 euid=100
 755 eventq_index=0
 756 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 757 gid=100
 758 input=cin
 759 max_stack_size=67108864
 760 output=cout
 761 pid=100
 762 ppid=99
 763 simpoint=0
 764 system=system
 765 uid=100
 766
 767 [system.cpu_clk_domain]
 768 type=SrcClockDomain
 769 clock=500
 770 domain_id=-1
 771 eventq_index=0
 772 init_perf_level=0
 773 voltage_domain=system.voltage_domain
 774
 775 [system.dvfs_handler]
 776 type=DVFSHandler
 777 domains=
 778 enable=false
 779 eventq_index=0
 780 sys_clk_domain=system.clk_domain
 781 transition_latency=100000000
 782
 783 [system.membus]
 784 type=CoherentBus
 785 clk_domain=system.clk_domain
 786 eventq_index=0
 787 header_cycles=1
 788 system=system
 789 use_default_range=false
 790 width=8
 791 master=system.physmem.port
 792 slave=system.system_port system.cpu.l2cache.mem_side
 793
 794 [system.physmem]
 795 type=DRAMCtrl
 796 activation_limit=4
 797 addr_mapping=RoRaBaChCo
 798 banks_per_rank=8
 799 burst_length=8
 800 channels=1
 801 clk_domain=system.clk_domain
 802 conf_table_reported=true
 803 device_bus_width=8
 804 device_rowbuffer_size=1024
 805 devices_per_rank=8
 806 eventq_index=0
 807 in_addr_map=true
 808 max_accesses_per_row=16
 809 mem_sched_policy=frfcfs
 810 min_writes_per_switch=16
 811 null=false
 812 page_policy=open_adaptive
 813 range=0:134217727
 814 ranks_per_channel=2
 815 read_buffer_size=32
 816 static_backend_latency=10000
 817 static_frontend_latency=10000
 818 tBURST=5000
 819 tCK=1250
 820 tCL=13750
 821 tRAS=35000
 822 tRCD=13750
 823 tREFI=7800000
 824 tRFC=260000
 825 tRP=13750
 826 tRRD=6000
 827 tRTP=7500
 828 tRTW=2500
 829 tWR=15000
 830 tWTR=7500
 831 tXAW=30000
 832 write_buffer_size=64
 833 write_high_thresh_perc=85
 834 write_low_thresh_perc=50
 835 port=system.membus.master[0]
 836
 837 [system.voltage_domain]
 838 type=VoltageDomain
 839 eventq_index=0
 840 voltage=1.000000
 841