tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 num_work_ids=16
  28 readfile=
  29 symbolfile=
  30 work_begin_ckpt_count=0
  31 work_begin_cpu_id_exit=-1
  32 work_begin_exit_count=0
  33 work_cpus_ckpt_count=0
  34 work_end_ckpt_count=0
  35 work_end_exit_count=0
  36 work_item_id=-1
  37 system_port=system.membus.slave[0]
  38
  39 [system.clk_domain]
  40 type=SrcClockDomain
  41 clock=1000
  42 domain_id=-1
  43 eventq_index=0
  44 init_perf_level=0
  45 voltage_domain=system.voltage_domain
  46
  47 [system.cpu]
  48 type=DerivO3CPU
  49 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  50 LFSTSize=1024
  51 LQEntries=16
  52 LSQCheckLoads=true
  53 LSQDepCheckShift=0
  54 SQEntries=16
  55 SSITSize=1024
  56 activity=0
  57 backComSize=5
  58 branchPred=system.cpu.branchPred
  59 cachePorts=200
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 commitToDecodeDelay=1
  63 commitToFetchDelay=1
  64 commitToIEWDelay=1
  65 commitToRenameDelay=1
  66 commitWidth=8
  67 cpu_id=0
  68 decodeToFetchDelay=1
  69 decodeToRenameDelay=2
  70 decodeWidth=3
  71 dispatchWidth=6
  72 do_checkpoint_insts=true
  73 do_quiesce=true
  74 do_statistics_insts=true
  75 dstage2_mmu=system.cpu.dstage2_mmu
  76 dtb=system.cpu.dtb
  77 eventq_index=0
  78 fetchBufferSize=16
  79 fetchQueueSize=32
  80 fetchToDecodeDelay=3
  81 fetchTrapLatency=1
  82 fetchWidth=3
  83 forwardComSize=5
  84 fuPool=system.cpu.fuPool
  85 function_trace=false
  86 function_trace_start=0
  87 iewToCommitDelay=1
  88 iewToDecodeDelay=1
  89 iewToFetchDelay=1
  90 iewToRenameDelay=1
  91 interrupts=system.cpu.interrupts
  92 isa=system.cpu.isa
  93 issueToExecuteDelay=1
  94 issueWidth=8
  95 istage2_mmu=system.cpu.istage2_mmu
  96 itb=system.cpu.itb
  97 max_insts_all_threads=0
  98 max_insts_any_thread=0
  99 max_loads_all_threads=0
 100 max_loads_any_thread=0
 101 needsTSO=false
 102 numIQEntries=32
 103 numPhysCCRegs=640
 104 numPhysFloatRegs=192
 105 numPhysIntRegs=128
 106 numROBEntries=40
 107 numRobs=1
 108 numThreads=1
 109 profile=0
 110 progress_interval=0
 111 renameToDecodeDelay=1
 112 renameToFetchDelay=1
 113 renameToIEWDelay=1
 114 renameToROBDelay=1
 115 renameWidth=3
 116 simpoint_start_insts=
 117 smtCommitPolicy=RoundRobin
 118 smtFetchPolicy=SingleThread
 119 smtIQPolicy=Partitioned
 120 smtIQThreshold=100
 121 smtLSQPolicy=Partitioned
 122 smtLSQThreshold=100
 123 smtNumFetchingThreads=1
 124 smtROBPolicy=Partitioned
 125 smtROBThreshold=100
 126 socket_id=0
 127 squashWidth=8
 128 store_set_clear_period=250000
 129 switched_out=false
 130 system=system
 131 tracer=system.cpu.tracer
 132 trapLatency=13
 133 wbWidth=8
 134 workload=system.cpu.workload
 135 dcache_port=system.cpu.dcache.cpu_side
 136 icache_port=system.cpu.icache.cpu_side
 137
 138 [system.cpu.branchPred]
 139 type=BiModeBP
 140 BTBEntries=2048
 141 BTBTagSize=18
 142 RASSize=16
 143 choiceCtrBits=2
 144 choicePredictorSize=8192
 145 eventq_index=0
 146 globalCtrBits=2
 147 globalPredictorSize=8192
 148 instShiftAmt=2
 149 numThreads=1
 150
 151 [system.cpu.dcache]
 152 type=BaseCache
 153 children=tags
 154 addr_ranges=0:18446744073709551615
 155 assoc=2
 156 clk_domain=system.cpu_clk_domain
 157 demand_mshr_reserve=1
 158 eventq_index=0
 159 forward_snoops=true
 160 hit_latency=2
 161 is_top_level=true
 162 max_miss_count=0
 163 mshrs=6
 164 prefetch_on_access=false
 165 prefetcher=Null
 166 response_latency=2
 167 sequential_access=false
 168 size=32768
 169 system=system
 170 tags=system.cpu.dcache.tags
 171 tgts_per_mshr=8
 172 two_queue=false
 173 write_buffers=16
 174 cpu_side=system.cpu.dcache_port
 175 mem_side=system.cpu.toL2Bus.slave[1]
 176
 177 [system.cpu.dcache.tags]
 178 type=LRU
 179 assoc=2
 180 block_size=64
 181 clk_domain=system.cpu_clk_domain
 182 eventq_index=0
 183 hit_latency=2
 184 sequential_access=false
 185 size=32768
 186
 187 [system.cpu.dstage2_mmu]
 188 type=ArmStage2MMU
 189 children=stage2_tlb
 190 eventq_index=0
 191 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 192 sys=system
 193 tlb=system.cpu.dtb
 194
 195 [system.cpu.dstage2_mmu.stage2_tlb]
 196 type=ArmTLB
 197 children=walker
 198 eventq_index=0
 199 is_stage2=true
 200 size=32
 201 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 202
 203 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 204 type=ArmTableWalker
 205 clk_domain=system.cpu_clk_domain
 206 eventq_index=0
 207 is_stage2=true
 208 num_squash_per_cycle=2
 209 sys=system
 210
 211 [system.cpu.dtb]
 212 type=ArmTLB
 213 children=walker
 214 eventq_index=0
 215 is_stage2=false
 216 size=64
 217 walker=system.cpu.dtb.walker
 218
 219 [system.cpu.dtb.walker]
 220 type=ArmTableWalker
 221 clk_domain=system.cpu_clk_domain
 222 eventq_index=0
 223 is_stage2=false
 224 num_squash_per_cycle=2
 225 sys=system
 226 port=system.cpu.toL2Bus.slave[3]
 227
 228 [system.cpu.fuPool]
 229 type=FUPool
 230 children=FUList0 FUList1 FUList2 FUList3 FUList4
 231 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
 232 eventq_index=0
 233
 234 [system.cpu.fuPool.FUList0]
 235 type=FUDesc
 236 children=opList
 237 count=2
 238 eventq_index=0
 239 opList=system.cpu.fuPool.FUList0.opList
 240
 241 [system.cpu.fuPool.FUList0.opList]
 242 type=OpDesc
 243 eventq_index=0
 244 issueLat=1
 245 opClass=IntAlu
 246 opLat=1
 247
 248 [system.cpu.fuPool.FUList1]
 249 type=FUDesc
 250 children=opList0 opList1 opList2
 251 count=1
 252 eventq_index=0
 253 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
 254
 255 [system.cpu.fuPool.FUList1.opList0]
 256 type=OpDesc
 257 eventq_index=0
 258 issueLat=1
 259 opClass=IntMult
 260 opLat=3
 261
 262 [system.cpu.fuPool.FUList1.opList1]
 263 type=OpDesc
 264 eventq_index=0
 265 issueLat=12
 266 opClass=IntDiv
 267 opLat=12
 268
 269 [system.cpu.fuPool.FUList1.opList2]
 270 type=OpDesc
 271 eventq_index=0
 272 issueLat=1
 273 opClass=IprAccess
 274 opLat=3
 275
 276 [system.cpu.fuPool.FUList2]
 277 type=FUDesc
 278 children=opList
 279 count=1
 280 eventq_index=0
 281 opList=system.cpu.fuPool.FUList2.opList
 282
 283 [system.cpu.fuPool.FUList2.opList]
 284 type=OpDesc
 285 eventq_index=0
 286 issueLat=1
 287 opClass=MemRead
 288 opLat=2
 289
 290 [system.cpu.fuPool.FUList3]
 291 type=FUDesc
 292 children=opList
 293 count=1
 294 eventq_index=0
 295 opList=system.cpu.fuPool.FUList3.opList
 296
 297 [system.cpu.fuPool.FUList3.opList]
 298 type=OpDesc
 299 eventq_index=0
 300 issueLat=1
 301 opClass=MemWrite
 302 opLat=2
 303
 304 [system.cpu.fuPool.FUList4]
 305 type=FUDesc
 306 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
 307 count=2
 308 eventq_index=0
 309 opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
 310
 311 [system.cpu.fuPool.FUList4.opList00]
 312 type=OpDesc
 313 eventq_index=0
 314 issueLat=1
 315 opClass=SimdAdd
 316 opLat=4
 317
 318 [system.cpu.fuPool.FUList4.opList01]
 319 type=OpDesc
 320 eventq_index=0
 321 issueLat=1
 322 opClass=SimdAddAcc
 323 opLat=4
 324
 325 [system.cpu.fuPool.FUList4.opList02]
 326 type=OpDesc
 327 eventq_index=0
 328 issueLat=1
 329 opClass=SimdAlu
 330 opLat=4
 331
 332 [system.cpu.fuPool.FUList4.opList03]
 333 type=OpDesc
 334 eventq_index=0
 335 issueLat=1
 336 opClass=SimdCmp
 337 opLat=4
 338
 339 [system.cpu.fuPool.FUList4.opList04]
 340 type=OpDesc
 341 eventq_index=0
 342 issueLat=1
 343 opClass=SimdCvt
 344 opLat=3
 345
 346 [system.cpu.fuPool.FUList4.opList05]
 347 type=OpDesc
 348 eventq_index=0
 349 issueLat=1
 350 opClass=SimdMisc
 351 opLat=3
 352
 353 [system.cpu.fuPool.FUList4.opList06]
 354 type=OpDesc
 355 eventq_index=0
 356 issueLat=1
 357 opClass=SimdMult
 358 opLat=5
 359
 360 [system.cpu.fuPool.FUList4.opList07]
 361 type=OpDesc
 362 eventq_index=0
 363 issueLat=1
 364 opClass=SimdMultAcc
 365 opLat=5
 366
 367 [system.cpu.fuPool.FUList4.opList08]
 368 type=OpDesc
 369 eventq_index=0
 370 issueLat=1
 371 opClass=SimdShift
 372 opLat=3
 373
 374 [system.cpu.fuPool.FUList4.opList09]
 375 type=OpDesc
 376 eventq_index=0
 377 issueLat=1
 378 opClass=SimdShiftAcc
 379 opLat=3
 380
 381 [system.cpu.fuPool.FUList4.opList10]
 382 type=OpDesc
 383 eventq_index=0
 384 issueLat=1
 385 opClass=SimdSqrt
 386 opLat=9
 387
 388 [system.cpu.fuPool.FUList4.opList11]
 389 type=OpDesc
 390 eventq_index=0
 391 issueLat=1
 392 opClass=SimdFloatAdd
 393 opLat=5
 394
 395 [system.cpu.fuPool.FUList4.opList12]
 396 type=OpDesc
 397 eventq_index=0
 398 issueLat=1
 399 opClass=SimdFloatAlu
 400 opLat=5
 401
 402 [system.cpu.fuPool.FUList4.opList13]
 403 type=OpDesc
 404 eventq_index=0
 405 issueLat=1
 406 opClass=SimdFloatCmp
 407 opLat=3
 408
 409 [system.cpu.fuPool.FUList4.opList14]
 410 type=OpDesc
 411 eventq_index=0
 412 issueLat=1
 413 opClass=SimdFloatCvt
 414 opLat=3
 415
 416 [system.cpu.fuPool.FUList4.opList15]
 417 type=OpDesc
 418 eventq_index=0
 419 issueLat=1
 420 opClass=SimdFloatDiv
 421 opLat=3
 422
 423 [system.cpu.fuPool.FUList4.opList16]
 424 type=OpDesc
 425 eventq_index=0
 426 issueLat=1
 427 opClass=SimdFloatMisc
 428 opLat=3
 429
 430 [system.cpu.fuPool.FUList4.opList17]
 431 type=OpDesc
 432 eventq_index=0
 433 issueLat=1
 434 opClass=SimdFloatMult
 435 opLat=3
 436
 437 [system.cpu.fuPool.FUList4.opList18]
 438 type=OpDesc
 439 eventq_index=0
 440 issueLat=1
 441 opClass=SimdFloatMultAcc
 442 opLat=1
 443
 444 [system.cpu.fuPool.FUList4.opList19]
 445 type=OpDesc
 446 eventq_index=0
 447 issueLat=1
 448 opClass=SimdFloatSqrt
 449 opLat=9
 450
 451 [system.cpu.fuPool.FUList4.opList20]
 452 type=OpDesc
 453 eventq_index=0
 454 issueLat=1
 455 opClass=FloatAdd
 456 opLat=5
 457
 458 [system.cpu.fuPool.FUList4.opList21]
 459 type=OpDesc
 460 eventq_index=0
 461 issueLat=1
 462 opClass=FloatCmp
 463 opLat=5
 464
 465 [system.cpu.fuPool.FUList4.opList22]
 466 type=OpDesc
 467 eventq_index=0
 468 issueLat=1
 469 opClass=FloatCvt
 470 opLat=5
 471
 472 [system.cpu.fuPool.FUList4.opList23]
 473 type=OpDesc
 474 eventq_index=0
 475 issueLat=9
 476 opClass=FloatDiv
 477 opLat=9
 478
 479 [system.cpu.fuPool.FUList4.opList24]
 480 type=OpDesc
 481 eventq_index=0
 482 issueLat=33
 483 opClass=FloatSqrt
 484 opLat=33
 485
 486 [system.cpu.fuPool.FUList4.opList25]
 487 type=OpDesc
 488 eventq_index=0
 489 issueLat=1
 490 opClass=FloatMult
 491 opLat=4
 492
 493 [system.cpu.icache]
 494 type=BaseCache
 495 children=tags
 496 addr_ranges=0:18446744073709551615
 497 assoc=2
 498 clk_domain=system.cpu_clk_domain
 499 demand_mshr_reserve=1
 500 eventq_index=0
 501 forward_snoops=false
 502 hit_latency=1
 503 is_top_level=true
 504 max_miss_count=0
 505 mshrs=2
 506 prefetch_on_access=false
 507 prefetcher=Null
 508 response_latency=1
 509 sequential_access=false
 510 size=32768
 511 system=system
 512 tags=system.cpu.icache.tags
 513 tgts_per_mshr=8
 514 two_queue=false
 515 write_buffers=8
 516 cpu_side=system.cpu.icache_port
 517 mem_side=system.cpu.toL2Bus.slave[0]
 518
 519 [system.cpu.icache.tags]
 520 type=LRU
 521 assoc=2
 522 block_size=64
 523 clk_domain=system.cpu_clk_domain
 524 eventq_index=0
 525 hit_latency=1
 526 sequential_access=false
 527 size=32768
 528
 529 [system.cpu.interrupts]
 530 type=ArmInterrupts
 531 eventq_index=0
 532
 533 [system.cpu.isa]
 534 type=ArmISA
 535 eventq_index=0
 536 fpsid=1090793632
 537 id_aa64afr0_el1=0
 538 id_aa64afr1_el1=0
 539 id_aa64dfr0_el1=1052678
 540 id_aa64dfr1_el1=0
 541 id_aa64isar0_el1=0
 542 id_aa64isar1_el1=0
 543 id_aa64mmfr0_el1=15728642
 544 id_aa64mmfr1_el1=0
 545 id_aa64pfr0_el1=17
 546 id_aa64pfr1_el1=0
 547 id_isar0=34607377
 548 id_isar1=34677009
 549 id_isar2=555950401
 550 id_isar3=17899825
 551 id_isar4=268501314
 552 id_isar5=0
 553 id_mmfr0=270536963
 554 id_mmfr1=0
 555 id_mmfr2=19070976
 556 id_mmfr3=34611729
 557 id_pfr0=49
 558 id_pfr1=4113
 559 midr=1091551472
 560 pmu=Null
 561 system=system
 562
 563 [system.cpu.istage2_mmu]
 564 type=ArmStage2MMU
 565 children=stage2_tlb
 566 eventq_index=0
 567 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 568 sys=system
 569 tlb=system.cpu.itb
 570
 571 [system.cpu.istage2_mmu.stage2_tlb]
 572 type=ArmTLB
 573 children=walker
 574 eventq_index=0
 575 is_stage2=true
 576 size=32
 577 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 578
 579 [system.cpu.istage2_mmu.stage2_tlb.walker]
 580 type=ArmTableWalker
 581 clk_domain=system.cpu_clk_domain
 582 eventq_index=0
 583 is_stage2=true
 584 num_squash_per_cycle=2
 585 sys=system
 586
 587 [system.cpu.itb]
 588 type=ArmTLB
 589 children=walker
 590 eventq_index=0
 591 is_stage2=false
 592 size=64
 593 walker=system.cpu.itb.walker
 594
 595 [system.cpu.itb.walker]
 596 type=ArmTableWalker
 597 clk_domain=system.cpu_clk_domain
 598 eventq_index=0
 599 is_stage2=false
 600 num_squash_per_cycle=2
 601 sys=system
 602 port=system.cpu.toL2Bus.slave[2]
 603
 604 [system.cpu.l2cache]
 605 type=BaseCache
 606 children=prefetcher tags
 607 addr_ranges=0:18446744073709551615
 608 assoc=16
 609 clk_domain=system.cpu_clk_domain
 610 demand_mshr_reserve=1
 611 eventq_index=0
 612 forward_snoops=true
 613 hit_latency=12
 614 is_top_level=false
 615 max_miss_count=0
 616 mshrs=16
 617 prefetch_on_access=true
 618 prefetcher=system.cpu.l2cache.prefetcher
 619 response_latency=12
 620 sequential_access=false
 621 size=1048576
 622 system=system
 623 tags=system.cpu.l2cache.tags
 624 tgts_per_mshr=8
 625 two_queue=false
 626 write_buffers=8
 627 cpu_side=system.cpu.toL2Bus.master[0]
 628 mem_side=system.membus.slave[1]
 629
 630 [system.cpu.l2cache.prefetcher]
 631 type=StridePrefetcher
 632 cache_snoop=false
 633 clk_domain=system.cpu_clk_domain
 634 degree=8
 635 eventq_index=0
 636 latency=1
 637 max_conf=7
 638 min_conf=0
 639 on_data=true
 640 on_inst=true
 641 on_miss=false
 642 on_read=true
 643 on_write=true
 644 queue_filter=true
 645 queue_size=32
 646 queue_squash=true
 647 start_conf=4
 648 sys=system
 649 table_assoc=4
 650 table_sets=16
 651 tag_prefetch=true
 652 thresh_conf=4
 653 use_master_id=true
 654
 655 [system.cpu.l2cache.tags]
 656 type=RandomRepl
 657 assoc=16
 658 block_size=64
 659 clk_domain=system.cpu_clk_domain
 660 eventq_index=0
 661 hit_latency=12
 662 sequential_access=false
 663 size=1048576
 664
 665 [system.cpu.toL2Bus]
 666 type=CoherentXBar
 667 clk_domain=system.cpu_clk_domain
 668 eventq_index=0
 669 forward_latency=0
 670 frontend_latency=1
 671 response_latency=1
 672 snoop_filter=Null
 673 snoop_response_latency=1
 674 system=system
 675 use_default_range=false
 676 width=32
 677 master=system.cpu.l2cache.cpu_side
 678 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 679
 680 [system.cpu.tracer]
 681 type=ExeTracer
 682 eventq_index=0
 683
 684 [system.cpu.workload]
 685 type=LiveProcess
 686 cmd=perlbmk -I. -I lib mdred.makerand.pl
 687 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 688 drivers=
 689 egid=100
 690 env=
 691 errout=cerr
 692 euid=100
 693 eventq_index=0
 694 executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
 695 gid=100
 696 input=cin
 697 kvmInSE=false
 698 max_stack_size=67108864
 699 output=cout
 700 pid=100
 701 ppid=99
 702 simpoint=0
 703 system=system
 704 uid=100
 705 useArchPT=false
 706
 707 [system.cpu_clk_domain]
 708 type=SrcClockDomain
 709 clock=500
 710 domain_id=-1
 711 eventq_index=0
 712 init_perf_level=0
 713 voltage_domain=system.voltage_domain
 714
 715 [system.dvfs_handler]
 716 type=DVFSHandler
 717 domains=
 718 enable=false
 719 eventq_index=0
 720 sys_clk_domain=system.clk_domain
 721 transition_latency=100000000
 722
 723 [system.membus]
 724 type=CoherentXBar
 725 clk_domain=system.clk_domain
 726 eventq_index=0
 727 forward_latency=4
 728 frontend_latency=3
 729 response_latency=2
 730 snoop_filter=Null
 731 snoop_response_latency=4
 732 system=system
 733 use_default_range=false
 734 width=16
 735 master=system.physmem.port
 736 slave=system.system_port system.cpu.l2cache.mem_side
 737
 738 [system.physmem]
 739 type=DRAMCtrl
 740 IDD0=0.075000
 741 IDD02=0.000000
 742 IDD2N=0.050000
 743 IDD2N2=0.000000
 744 IDD2P0=0.000000
 745 IDD2P02=0.000000
 746 IDD2P1=0.000000
 747 IDD2P12=0.000000
 748 IDD3N=0.057000
 749 IDD3N2=0.000000
 750 IDD3P0=0.000000
 751 IDD3P02=0.000000
 752 IDD3P1=0.000000
 753 IDD3P12=0.000000
 754 IDD4R=0.187000
 755 IDD4R2=0.000000
 756 IDD4W=0.165000
 757 IDD4W2=0.000000
 758 IDD5=0.220000
 759 IDD52=0.000000
 760 IDD6=0.000000
 761 IDD62=0.000000
 762 VDD=1.500000
 763 VDD2=0.000000
 764 activation_limit=4
 765 addr_mapping=RoRaBaCoCh
 766 bank_groups_per_rank=0
 767 banks_per_rank=8
 768 burst_length=8
 769 channels=1
 770 clk_domain=system.clk_domain
 771 conf_table_reported=true
 772 device_bus_width=8
 773 device_rowbuffer_size=1024
 774 device_size=536870912
 775 devices_per_rank=8
 776 dll=true
 777 eventq_index=0
 778 in_addr_map=true
 779 max_accesses_per_row=16
 780 mem_sched_policy=frfcfs
 781 min_writes_per_switch=16
 782 null=false
 783 page_policy=open_adaptive
 784 range=0:134217727
 785 ranks_per_channel=2
 786 read_buffer_size=32
 787 static_backend_latency=10000
 788 static_frontend_latency=10000
 789 tBURST=5000
 790 tCCD_L=0
 791 tCK=1250
 792 tCL=13750
 793 tCS=2500
 794 tRAS=35000
 795 tRCD=13750
 796 tREFI=7800000
 797 tRFC=260000
 798 tRP=13750
 799 tRRD=6000
 800 tRRD_L=0
 801 tRTP=7500
 802 tRTW=2500
 803 tWR=15000
 804 tWTR=7500
 805 tXAW=30000
 806 tXP=0
 807 tXPDLL=0
 808 tXS=0
 809 tXSDLL=0
 810 write_buffer_size=64
 811 write_high_thresh_perc=85
 812 write_low_thresh_perc=50
 813 port=system.membus.master[0]
 814
 815 [system.voltage_domain]
 816 type=VoltageDomain
 817 eventq_index=0
 818 voltage=1.000000
 819