tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 readfile=
  20 symbolfile=
  21 work_begin_ckpt_count=0
  22 work_begin_cpu_id_exit=-1
  23 work_begin_exit_count=0
  24 work_cpus_ckpt_count=0
  25 work_end_ckpt_count=0
  26 work_end_exit_count=0
  27 work_item_id=-1
  28 system_port=system.membus.slave[0]
  29
  30 [system.cpu]
  31 type=DerivO3CPU
  32 children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
  33 BTBEntries=4096
  34 BTBTagSize=16
  35 LFSTSize=1024
  36 LQEntries=32
  37 LSQCheckLoads=true
  38 LSQDepCheckShift=4
  39 RASSize=16
  40 SQEntries=32
  41 SSITSize=1024
  42 activity=0
  43 backComSize=5
  44 cachePorts=200
  45 checker=Null
  46 choiceCtrBits=2
  47 choicePredictorSize=8192
  48 clock=500
  49 commitToDecodeDelay=1
  50 commitToFetchDelay=1
  51 commitToIEWDelay=1
  52 commitToRenameDelay=1
  53 commitWidth=8
  54 cpu_id=0
  55 decodeToFetchDelay=1
  56 decodeToRenameDelay=1
  57 decodeWidth=8
  58 defer_registration=false
  59 dispatchWidth=8
  60 do_checkpoint_insts=true
  61 do_quiesce=true
  62 do_statistics_insts=true
  63 dtb=system.cpu.dtb
  64 fetchToDecodeDelay=1
  65 fetchTrapLatency=1
  66 fetchWidth=8
  67 forwardComSize=5
  68 fuPool=system.cpu.fuPool
  69 function_trace=false
  70 function_trace_start=0
  71 globalCtrBits=2
  72 globalHistoryBits=13
  73 globalPredictorSize=8192
  74 iewToCommitDelay=1
  75 iewToDecodeDelay=1
  76 iewToFetchDelay=1
  77 iewToRenameDelay=1
  78 instShiftAmt=2
  79 interrupts=system.cpu.interrupts
  80 issueToExecuteDelay=1
  81 issueWidth=8
  82 itb=system.cpu.itb
  83 localCtrBits=2
  84 localHistoryBits=11
  85 localHistoryTableSize=2048
  86 localPredictorSize=2048
  87 max_insts_all_threads=0
  88 max_insts_any_thread=0
  89 max_loads_all_threads=0
  90 max_loads_any_thread=0
  91 needsTSO=false
  92 numIQEntries=64
  93 numPhysFloatRegs=256
  94 numPhysIntRegs=256
  95 numROBEntries=192
  96 numRobs=1
  97 numThreads=1
  98 phase=0
  99 predType=tournament
 100 profile=0
 101 progress_interval=0
 102 renameToDecodeDelay=1
 103 renameToFetchDelay=1
 104 renameToIEWDelay=2
 105 renameToROBDelay=1
 106 renameWidth=8
 107 smtCommitPolicy=RoundRobin
 108 smtFetchPolicy=SingleThread
 109 smtIQPolicy=Partitioned
 110 smtIQThreshold=100
 111 smtLSQPolicy=Partitioned
 112 smtLSQThreshold=100
 113 smtNumFetchingThreads=1
 114 smtROBPolicy=Partitioned
 115 smtROBThreshold=100
 116 squashWidth=8
 117 store_set_clear_period=250000
 118 system=system
 119 tracer=system.cpu.tracer
 120 trapLatency=13
 121 wbDepth=1
 122 wbWidth=8
 123 workload=system.cpu.workload
 124 dcache_port=system.cpu.dcache.cpu_side
 125 icache_port=system.cpu.icache.cpu_side
 126
 127 [system.cpu.dcache]
 128 type=BaseCache
 129 addr_ranges=0:18446744073709551615
 130 assoc=2
 131 block_size=64
 132 forward_snoops=true
 133 hash_delay=1
 134 is_top_level=true
 135 latency=1000
 136 max_miss_count=0
 137 mshrs=10
 138 prefetch_on_access=false
 139 prefetcher=Null
 140 prioritizeRequests=false
 141 repl=Null
 142 size=262144
 143 subblock_size=0
 144 system=system
 145 tgts_per_mshr=20
 146 trace_addr=0
 147 two_queue=false
 148 write_buffers=8
 149 cpu_side=system.cpu.dcache_port
 150 mem_side=system.cpu.toL2Bus.slave[1]
 151
 152 [system.cpu.dtb]
 153 type=ArmTLB
 154 children=walker
 155 size=64
 156 walker=system.cpu.dtb.walker
 157
 158 [system.cpu.dtb.walker]
 159 type=ArmTableWalker
 160 max_backoff=100000
 161 min_backoff=0
 162 sys=system
 163 port=system.cpu.toL2Bus.slave[3]
 164
 165 [system.cpu.fuPool]
 166 type=FUPool
 167 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 168 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 169
 170 [system.cpu.fuPool.FUList0]
 171 type=FUDesc
 172 children=opList
 173 count=6
 174 opList=system.cpu.fuPool.FUList0.opList
 175
 176 [system.cpu.fuPool.FUList0.opList]
 177 type=OpDesc
 178 issueLat=1
 179 opClass=IntAlu
 180 opLat=1
 181
 182 [system.cpu.fuPool.FUList1]
 183 type=FUDesc
 184 children=opList0 opList1
 185 count=2
 186 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 187
 188 [system.cpu.fuPool.FUList1.opList0]
 189 type=OpDesc
 190 issueLat=1
 191 opClass=IntMult
 192 opLat=3
 193
 194 [system.cpu.fuPool.FUList1.opList1]
 195 type=OpDesc
 196 issueLat=19
 197 opClass=IntDiv
 198 opLat=20
 199
 200 [system.cpu.fuPool.FUList2]
 201 type=FUDesc
 202 children=opList0 opList1 opList2
 203 count=4
 204 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 205
 206 [system.cpu.fuPool.FUList2.opList0]
 207 type=OpDesc
 208 issueLat=1
 209 opClass=FloatAdd
 210 opLat=2
 211
 212 [system.cpu.fuPool.FUList2.opList1]
 213 type=OpDesc
 214 issueLat=1
 215 opClass=FloatCmp
 216 opLat=2
 217
 218 [system.cpu.fuPool.FUList2.opList2]
 219 type=OpDesc
 220 issueLat=1
 221 opClass=FloatCvt
 222 opLat=2
 223
 224 [system.cpu.fuPool.FUList3]
 225 type=FUDesc
 226 children=opList0 opList1 opList2
 227 count=2
 228 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 229
 230 [system.cpu.fuPool.FUList3.opList0]
 231 type=OpDesc
 232 issueLat=1
 233 opClass=FloatMult
 234 opLat=4
 235
 236 [system.cpu.fuPool.FUList3.opList1]
 237 type=OpDesc
 238 issueLat=12
 239 opClass=FloatDiv
 240 opLat=12
 241
 242 [system.cpu.fuPool.FUList3.opList2]
 243 type=OpDesc
 244 issueLat=24
 245 opClass=FloatSqrt
 246 opLat=24
 247
 248 [system.cpu.fuPool.FUList4]
 249 type=FUDesc
 250 children=opList
 251 count=0
 252 opList=system.cpu.fuPool.FUList4.opList
 253
 254 [system.cpu.fuPool.FUList4.opList]
 255 type=OpDesc
 256 issueLat=1
 257 opClass=MemRead
 258 opLat=1
 259
 260 [system.cpu.fuPool.FUList5]
 261 type=FUDesc
 262 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 263 count=4
 264 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 265
 266 [system.cpu.fuPool.FUList5.opList00]
 267 type=OpDesc
 268 issueLat=1
 269 opClass=SimdAdd
 270 opLat=1
 271
 272 [system.cpu.fuPool.FUList5.opList01]
 273 type=OpDesc
 274 issueLat=1
 275 opClass=SimdAddAcc
 276 opLat=1
 277
 278 [system.cpu.fuPool.FUList5.opList02]
 279 type=OpDesc
 280 issueLat=1
 281 opClass=SimdAlu
 282 opLat=1
 283
 284 [system.cpu.fuPool.FUList5.opList03]
 285 type=OpDesc
 286 issueLat=1
 287 opClass=SimdCmp
 288 opLat=1
 289
 290 [system.cpu.fuPool.FUList5.opList04]
 291 type=OpDesc
 292 issueLat=1
 293 opClass=SimdCvt
 294 opLat=1
 295
 296 [system.cpu.fuPool.FUList5.opList05]
 297 type=OpDesc
 298 issueLat=1
 299 opClass=SimdMisc
 300 opLat=1
 301
 302 [system.cpu.fuPool.FUList5.opList06]
 303 type=OpDesc
 304 issueLat=1
 305 opClass=SimdMult
 306 opLat=1
 307
 308 [system.cpu.fuPool.FUList5.opList07]
 309 type=OpDesc
 310 issueLat=1
 311 opClass=SimdMultAcc
 312 opLat=1
 313
 314 [system.cpu.fuPool.FUList5.opList08]
 315 type=OpDesc
 316 issueLat=1
 317 opClass=SimdShift
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList09]
 321 type=OpDesc
 322 issueLat=1
 323 opClass=SimdShiftAcc
 324 opLat=1
 325
 326 [system.cpu.fuPool.FUList5.opList10]
 327 type=OpDesc
 328 issueLat=1
 329 opClass=SimdSqrt
 330 opLat=1
 331
 332 [system.cpu.fuPool.FUList5.opList11]
 333 type=OpDesc
 334 issueLat=1
 335 opClass=SimdFloatAdd
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList12]
 339 type=OpDesc
 340 issueLat=1
 341 opClass=SimdFloatAlu
 342 opLat=1
 343
 344 [system.cpu.fuPool.FUList5.opList13]
 345 type=OpDesc
 346 issueLat=1
 347 opClass=SimdFloatCmp
 348 opLat=1
 349
 350 [system.cpu.fuPool.FUList5.opList14]
 351 type=OpDesc
 352 issueLat=1
 353 opClass=SimdFloatCvt
 354 opLat=1
 355
 356 [system.cpu.fuPool.FUList5.opList15]
 357 type=OpDesc
 358 issueLat=1
 359 opClass=SimdFloatDiv
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList16]
 363 type=OpDesc
 364 issueLat=1
 365 opClass=SimdFloatMisc
 366 opLat=1
 367
 368 [system.cpu.fuPool.FUList5.opList17]
 369 type=OpDesc
 370 issueLat=1
 371 opClass=SimdFloatMult
 372 opLat=1
 373
 374 [system.cpu.fuPool.FUList5.opList18]
 375 type=OpDesc
 376 issueLat=1
 377 opClass=SimdFloatMultAcc
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList19]
 381 type=OpDesc
 382 issueLat=1
 383 opClass=SimdFloatSqrt
 384 opLat=1
 385
 386 [system.cpu.fuPool.FUList6]
 387 type=FUDesc
 388 children=opList
 389 count=0
 390 opList=system.cpu.fuPool.FUList6.opList
 391
 392 [system.cpu.fuPool.FUList6.opList]
 393 type=OpDesc
 394 issueLat=1
 395 opClass=MemWrite
 396 opLat=1
 397
 398 [system.cpu.fuPool.FUList7]
 399 type=FUDesc
 400 children=opList0 opList1
 401 count=4
 402 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 403
 404 [system.cpu.fuPool.FUList7.opList0]
 405 type=OpDesc
 406 issueLat=1
 407 opClass=MemRead
 408 opLat=1
 409
 410 [system.cpu.fuPool.FUList7.opList1]
 411 type=OpDesc
 412 issueLat=1
 413 opClass=MemWrite
 414 opLat=1
 415
 416 [system.cpu.fuPool.FUList8]
 417 type=FUDesc
 418 children=opList
 419 count=1
 420 opList=system.cpu.fuPool.FUList8.opList
 421
 422 [system.cpu.fuPool.FUList8.opList]
 423 type=OpDesc
 424 issueLat=3
 425 opClass=IprAccess
 426 opLat=3
 427
 428 [system.cpu.icache]
 429 type=BaseCache
 430 addr_ranges=0:18446744073709551615
 431 assoc=2
 432 block_size=64
 433 forward_snoops=true
 434 hash_delay=1
 435 is_top_level=true
 436 latency=1000
 437 max_miss_count=0
 438 mshrs=10
 439 prefetch_on_access=false
 440 prefetcher=Null
 441 prioritizeRequests=false
 442 repl=Null
 443 size=131072
 444 subblock_size=0
 445 system=system
 446 tgts_per_mshr=20
 447 trace_addr=0
 448 two_queue=false
 449 write_buffers=8
 450 cpu_side=system.cpu.icache_port
 451 mem_side=system.cpu.toL2Bus.slave[0]
 452
 453 [system.cpu.interrupts]
 454 type=ArmInterrupts
 455
 456 [system.cpu.itb]
 457 type=ArmTLB
 458 children=walker
 459 size=64
 460 walker=system.cpu.itb.walker
 461
 462 [system.cpu.itb.walker]
 463 type=ArmTableWalker
 464 max_backoff=100000
 465 min_backoff=0
 466 sys=system
 467 port=system.cpu.toL2Bus.slave[2]
 468
 469 [system.cpu.l2cache]
 470 type=BaseCache
 471 addr_ranges=0:18446744073709551615
 472 assoc=2
 473 block_size=64
 474 forward_snoops=true
 475 hash_delay=1
 476 is_top_level=false
 477 latency=1000
 478 max_miss_count=0
 479 mshrs=10
 480 prefetch_on_access=false
 481 prefetcher=Null
 482 prioritizeRequests=false
 483 repl=Null
 484 size=2097152
 485 subblock_size=0
 486 system=system
 487 tgts_per_mshr=5
 488 trace_addr=0
 489 two_queue=false
 490 write_buffers=8
 491 cpu_side=system.cpu.toL2Bus.master[0]
 492 mem_side=system.membus.slave[1]
 493
 494 [system.cpu.toL2Bus]
 495 type=CoherentBus
 496 block_size=64
 497 clock=1000
 498 header_cycles=1
 499 use_default_range=false
 500 width=64
 501 master=system.cpu.l2cache.cpu_side
 502 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 503
 504 [system.cpu.tracer]
 505 type=ExeTracer
 506
 507 [system.cpu.workload]
 508 type=LiveProcess
 509 cmd=perlbmk -I. -I lib lgred.makerand.pl
 510 cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
 511 egid=100
 512 env=
 513 errout=cerr
 514 euid=100
 515 executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 516 gid=100
 517 input=cin
 518 max_stack_size=67108864
 519 output=cout
 520 pid=100
 521 ppid=99
 522 simpoint=0
 523 system=system
 524 uid=100
 525
 526 [system.membus]
 527 type=CoherentBus
 528 block_size=64
 529 clock=1000
 530 header_cycles=1
 531 use_default_range=false
 532 width=64
 533 master=system.physmem.port[0]
 534 slave=system.system_port system.cpu.l2cache.mem_side
 535
 536 [system.physmem]
 537 type=SimpleMemory
 538 conf_table_reported=false
 539 file=
 540 in_addr_map=true
 541 latency=30000
 542 latency_var=0
 543 null=false
 544 range=0:134217727
 545 zero=false
 546 port=system.membus.master[0]
 547