tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 LFSTSize=1024
  36 LQEntries=32
  37 LSQCheckLoads=true
  38 LSQDepCheckShift=4
  39 SQEntries=32
  40 SSITSize=1024
  41 activity=0
  42 backComSize=5
  43 branchPred=system.cpu.branchPred
  44 cachePorts=200
  45 checker=Null
  46 clock=500
  47 commitToDecodeDelay=1
  48 commitToFetchDelay=1
  49 commitToIEWDelay=1
  50 commitToRenameDelay=1
  51 commitWidth=8
  52 cpu_id=0
  53 decodeToFetchDelay=1
  54 decodeToRenameDelay=1
  55 decodeWidth=8
  56 dispatchWidth=8
  57 do_checkpoint_insts=true
  58 do_quiesce=true
  59 do_statistics_insts=true
  60 dtb=system.cpu.dtb
  61 fetchToDecodeDelay=1
  62 fetchTrapLatency=1
  63 fetchWidth=8
  64 forwardComSize=5
  65 fuPool=system.cpu.fuPool
  66 function_trace=false
  67 function_trace_start=0
  68 iewToCommitDelay=1
  69 iewToDecodeDelay=1
  70 iewToFetchDelay=1
  71 iewToRenameDelay=1
  72 interrupts=system.cpu.interrupts
  73 isa=system.cpu.isa
  74 issueToExecuteDelay=1
  75 issueWidth=8
  76 itb=system.cpu.itb
  77 max_insts_all_threads=0
  78 max_insts_any_thread=0
  79 max_loads_all_threads=0
  80 max_loads_any_thread=0
  81 needsTSO=false
  82 numIQEntries=64
  83 numPhysFloatRegs=256
  84 numPhysIntRegs=256
  85 numROBEntries=192
  86 numRobs=1
  87 numThreads=1
  88 profile=0
  89 progress_interval=0
  90 renameToDecodeDelay=1
  91 renameToFetchDelay=1
  92 renameToIEWDelay=2
  93 renameToROBDelay=1
  94 renameWidth=8
  95 smtCommitPolicy=RoundRobin
  96 smtFetchPolicy=SingleThread
  97 smtIQPolicy=Partitioned
  98 smtIQThreshold=100
  99 smtLSQPolicy=Partitioned
 100 smtLSQThreshold=100
 101 smtNumFetchingThreads=1
 102 smtROBPolicy=Partitioned
 103 smtROBThreshold=100
 104 squashWidth=8
 105 store_set_clear_period=250000
 106 switched_out=false
 107 system=system
 108 tracer=system.cpu.tracer
 109 trapLatency=13
 110 wbDepth=1
 111 wbWidth=8
 112 workload=system.cpu.workload
 113 dcache_port=system.cpu.dcache.cpu_side
 114 icache_port=system.cpu.icache.cpu_side
 115
 116 [system.cpu.branchPred]
 117 type=BranchPredictor
 118 BTBEntries=4096
 119 BTBTagSize=16
 120 RASSize=16
 121 choiceCtrBits=2
 122 choicePredictorSize=8192
 123 globalCtrBits=2
 124 globalHistoryBits=13
 125 globalPredictorSize=8192
 126 instShiftAmt=2
 127 localCtrBits=2
 128 localHistoryBits=11
 129 localHistoryTableSize=2048
 130 localPredictorSize=2048
 131 numThreads=1
 132 predType=tournament
 133
 134 [system.cpu.dcache]
 135 type=BaseCache
 136 addr_ranges=0:18446744073709551615
 137 assoc=2
 138 block_size=64
 139 clock=500
 140 forward_snoops=true
 141 hit_latency=2
 142 is_top_level=true
 143 max_miss_count=0
 144 mshrs=4
 145 prefetch_on_access=false
 146 prefetcher=Null
 147 response_latency=2
 148 size=262144
 149 system=system
 150 tgts_per_mshr=20
 151 two_queue=false
 152 write_buffers=8
 153 cpu_side=system.cpu.dcache_port
 154 mem_side=system.cpu.toL2Bus.slave[1]
 155
 156 [system.cpu.dtb]
 157 type=ArmTLB
 158 children=walker
 159 size=64
 160 walker=system.cpu.dtb.walker
 161
 162 [system.cpu.dtb.walker]
 163 type=ArmTableWalker
 164 clock=500
 165 num_squash_per_cycle=2
 166 sys=system
 167 port=system.cpu.toL2Bus.slave[3]
 168
 169 [system.cpu.fuPool]
 170 type=FUPool
 171 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 172 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 173
 174 [system.cpu.fuPool.FUList0]
 175 type=FUDesc
 176 children=opList
 177 count=6
 178 opList=system.cpu.fuPool.FUList0.opList
 179
 180 [system.cpu.fuPool.FUList0.opList]
 181 type=OpDesc
 182 issueLat=1
 183 opClass=IntAlu
 184 opLat=1
 185
 186 [system.cpu.fuPool.FUList1]
 187 type=FUDesc
 188 children=opList0 opList1
 189 count=2
 190 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 191
 192 [system.cpu.fuPool.FUList1.opList0]
 193 type=OpDesc
 194 issueLat=1
 195 opClass=IntMult
 196 opLat=3
 197
 198 [system.cpu.fuPool.FUList1.opList1]
 199 type=OpDesc
 200 issueLat=19
 201 opClass=IntDiv
 202 opLat=20
 203
 204 [system.cpu.fuPool.FUList2]
 205 type=FUDesc
 206 children=opList0 opList1 opList2
 207 count=4
 208 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 209
 210 [system.cpu.fuPool.FUList2.opList0]
 211 type=OpDesc
 212 issueLat=1
 213 opClass=FloatAdd
 214 opLat=2
 215
 216 [system.cpu.fuPool.FUList2.opList1]
 217 type=OpDesc
 218 issueLat=1
 219 opClass=FloatCmp
 220 opLat=2
 221
 222 [system.cpu.fuPool.FUList2.opList2]
 223 type=OpDesc
 224 issueLat=1
 225 opClass=FloatCvt
 226 opLat=2
 227
 228 [system.cpu.fuPool.FUList3]
 229 type=FUDesc
 230 children=opList0 opList1 opList2
 231 count=2
 232 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 233
 234 [system.cpu.fuPool.FUList3.opList0]
 235 type=OpDesc
 236 issueLat=1
 237 opClass=FloatMult
 238 opLat=4
 239
 240 [system.cpu.fuPool.FUList3.opList1]
 241 type=OpDesc
 242 issueLat=12
 243 opClass=FloatDiv
 244 opLat=12
 245
 246 [system.cpu.fuPool.FUList3.opList2]
 247 type=OpDesc
 248 issueLat=24
 249 opClass=FloatSqrt
 250 opLat=24
 251
 252 [system.cpu.fuPool.FUList4]
 253 type=FUDesc
 254 children=opList
 255 count=0
 256 opList=system.cpu.fuPool.FUList4.opList
 257
 258 [system.cpu.fuPool.FUList4.opList]
 259 type=OpDesc
 260 issueLat=1
 261 opClass=MemRead
 262 opLat=1
 263
 264 [system.cpu.fuPool.FUList5]
 265 type=FUDesc
 266 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 267 count=4
 268 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 269
 270 [system.cpu.fuPool.FUList5.opList00]
 271 type=OpDesc
 272 issueLat=1
 273 opClass=SimdAdd
 274 opLat=1
 275
 276 [system.cpu.fuPool.FUList5.opList01]
 277 type=OpDesc
 278 issueLat=1
 279 opClass=SimdAddAcc
 280 opLat=1
 281
 282 [system.cpu.fuPool.FUList5.opList02]
 283 type=OpDesc
 284 issueLat=1
 285 opClass=SimdAlu
 286 opLat=1
 287
 288 [system.cpu.fuPool.FUList5.opList03]
 289 type=OpDesc
 290 issueLat=1
 291 opClass=SimdCmp
 292 opLat=1
 293
 294 [system.cpu.fuPool.FUList5.opList04]
 295 type=OpDesc
 296 issueLat=1
 297 opClass=SimdCvt
 298 opLat=1
 299
 300 [system.cpu.fuPool.FUList5.opList05]
 301 type=OpDesc
 302 issueLat=1
 303 opClass=SimdMisc
 304 opLat=1
 305
 306 [system.cpu.fuPool.FUList5.opList06]
 307 type=OpDesc
 308 issueLat=1
 309 opClass=SimdMult
 310 opLat=1
 311
 312 [system.cpu.fuPool.FUList5.opList07]
 313 type=OpDesc
 314 issueLat=1
 315 opClass=SimdMultAcc
 316 opLat=1
 317
 318 [system.cpu.fuPool.FUList5.opList08]
 319 type=OpDesc
 320 issueLat=1
 321 opClass=SimdShift
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList09]
 325 type=OpDesc
 326 issueLat=1
 327 opClass=SimdShiftAcc
 328 opLat=1
 329
 330 [system.cpu.fuPool.FUList5.opList10]
 331 type=OpDesc
 332 issueLat=1
 333 opClass=SimdSqrt
 334 opLat=1
 335
 336 [system.cpu.fuPool.FUList5.opList11]
 337 type=OpDesc
 338 issueLat=1
 339 opClass=SimdFloatAdd
 340 opLat=1
 341
 342 [system.cpu.fuPool.FUList5.opList12]
 343 type=OpDesc
 344 issueLat=1
 345 opClass=SimdFloatAlu
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList13]
 349 type=OpDesc
 350 issueLat=1
 351 opClass=SimdFloatCmp
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList14]
 355 type=OpDesc
 356 issueLat=1
 357 opClass=SimdFloatCvt
 358 opLat=1
 359
 360 [system.cpu.fuPool.FUList5.opList15]
 361 type=OpDesc
 362 issueLat=1
 363 opClass=SimdFloatDiv
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList16]
 367 type=OpDesc
 368 issueLat=1
 369 opClass=SimdFloatMisc
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList5.opList17]
 373 type=OpDesc
 374 issueLat=1
 375 opClass=SimdFloatMult
 376 opLat=1
 377
 378 [system.cpu.fuPool.FUList5.opList18]
 379 type=OpDesc
 380 issueLat=1
 381 opClass=SimdFloatMultAcc
 382 opLat=1
 383
 384 [system.cpu.fuPool.FUList5.opList19]
 385 type=OpDesc
 386 issueLat=1
 387 opClass=SimdFloatSqrt
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList6]
 391 type=FUDesc
 392 children=opList
 393 count=0
 394 opList=system.cpu.fuPool.FUList6.opList
 395
 396 [system.cpu.fuPool.FUList6.opList]
 397 type=OpDesc
 398 issueLat=1
 399 opClass=MemWrite
 400 opLat=1
 401
 402 [system.cpu.fuPool.FUList7]
 403 type=FUDesc
 404 children=opList0 opList1
 405 count=4
 406 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 407
 408 [system.cpu.fuPool.FUList7.opList0]
 409 type=OpDesc
 410 issueLat=1
 411 opClass=MemRead
 412 opLat=1
 413
 414 [system.cpu.fuPool.FUList7.opList1]
 415 type=OpDesc
 416 issueLat=1
 417 opClass=MemWrite
 418 opLat=1
 419
 420 [system.cpu.fuPool.FUList8]
 421 type=FUDesc
 422 children=opList
 423 count=1
 424 opList=system.cpu.fuPool.FUList8.opList
 425
 426 [system.cpu.fuPool.FUList8.opList]
 427 type=OpDesc
 428 issueLat=3
 429 opClass=IprAccess
 430 opLat=3
 431
 432 [system.cpu.icache]
 433 type=BaseCache
 434 addr_ranges=0:18446744073709551615
 435 assoc=2
 436 block_size=64
 437 clock=500
 438 forward_snoops=true
 439 hit_latency=2
 440 is_top_level=true
 441 max_miss_count=0
 442 mshrs=4
 443 prefetch_on_access=false
 444 prefetcher=Null
 445 response_latency=2
 446 size=131072
 447 system=system
 448 tgts_per_mshr=20
 449 two_queue=false
 450 write_buffers=8
 451 cpu_side=system.cpu.icache_port
 452 mem_side=system.cpu.toL2Bus.slave[0]
 453
 454 [system.cpu.interrupts]
 455 type=ArmInterrupts
 456
 457 [system.cpu.isa]
 458 type=ArmISA
 459 fpsid=1090793632
 460 id_isar0=34607377
 461 id_isar1=34677009
 462 id_isar2=555950401
 463 id_isar3=17899825
 464 id_isar4=268501314
 465 id_isar5=0
 466 id_mmfr0=3
 467 id_mmfr1=0
 468 id_mmfr2=19070976
 469 id_mmfr3=4027589137
 470 id_pfr0=49
 471 id_pfr1=1
 472 midr=890224640
 473
 474 [system.cpu.itb]
 475 type=ArmTLB
 476 children=walker
 477 size=64
 478 walker=system.cpu.itb.walker
 479
 480 [system.cpu.itb.walker]
 481 type=ArmTableWalker
 482 clock=500
 483 num_squash_per_cycle=2
 484 sys=system
 485 port=system.cpu.toL2Bus.slave[2]
 486
 487 [system.cpu.l2cache]
 488 type=BaseCache
 489 addr_ranges=0:18446744073709551615
 490 assoc=8
 491 block_size=64
 492 clock=500
 493 forward_snoops=true
 494 hit_latency=20
 495 is_top_level=false
 496 max_miss_count=0
 497 mshrs=20
 498 prefetch_on_access=false
 499 prefetcher=Null
 500 response_latency=20
 501 size=2097152
 502 system=system
 503 tgts_per_mshr=12
 504 two_queue=false
 505 write_buffers=8
 506 cpu_side=system.cpu.toL2Bus.master[0]
 507 mem_side=system.membus.slave[1]
 508
 509 [system.cpu.toL2Bus]
 510 type=CoherentBus
 511 block_size=64
 512 clock=500
 513 header_cycles=1
 514 system=system
 515 use_default_range=false
 516 width=32
 517 master=system.cpu.l2cache.cpu_side
 518 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 519
 520 [system.cpu.tracer]
 521 type=ExeTracer
 522
 523 [system.cpu.workload]
 524 type=LiveProcess
 525 cmd=perlbmk -I. -I lib lgred.makerand.pl
 526 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 527 egid=100
 528 env=
 529 errout=cerr
 530 euid=100
 531 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 532 gid=100
 533 input=cin
 534 max_stack_size=67108864
 535 output=cout
 536 pid=100
 537 ppid=99
 538 simpoint=0
 539 system=system
 540 uid=100
 541
 542 [system.membus]
 543 type=CoherentBus
 544 block_size=64
 545 clock=1000
 546 header_cycles=1
 547 system=system
 548 use_default_range=false
 549 width=8
 550 master=system.physmem.port
 551 slave=system.system_port system.cpu.l2cache.mem_side
 552
 553 [system.physmem]
 554 type=SimpleDRAM
 555 activation_limit=4
 556 addr_mapping=openmap
 557 banks_per_rank=8
 558 channels=1
 559 clock=1000
 560 conf_table_reported=false
 561 in_addr_map=true
 562 lines_per_rowbuffer=32
 563 mem_sched_policy=frfcfs
 564 null=false
 565 page_policy=open
 566 range=0:134217727
 567 ranks_per_channel=2
 568 read_buffer_size=32
 569 tBURST=5000
 570 tCL=13750
 571 tRCD=13750
 572 tREFI=7800000
 573 tRFC=300000
 574 tRP=13750
 575 tWTR=7500
 576 tXAW=40000
 577 write_buffer_size=32
 578 write_thresh_perc=70
 579 zero=false
 580 port=system.membus.master[0]
 581