tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 clock=1000
  14 init_param=0
  15 kernel=
  16 load_addr_mask=1099511627775
  17 mem_mode=timing
  18 mem_ranges=
  19 memories=system.physmem
  20 num_work_ids=16
  21 readfile=
  22 symbolfile=
  23 work_begin_ckpt_count=0
  24 work_begin_cpu_id_exit=-1
  25 work_begin_exit_count=0
  26 work_cpus_ckpt_count=0
  27 work_end_ckpt_count=0
  28 work_end_exit_count=0
  29 work_item_id=-1
  30 system_port=system.membus.slave[0]
  31
  32 [system.cpu]
  33 type=DerivO3CPU
  34 children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  35 BTBEntries=4096
  36 BTBTagSize=16
  37 LFSTSize=1024
  38 LQEntries=32
  39 LSQCheckLoads=true
  40 LSQDepCheckShift=4
  41 RASSize=16
  42 SQEntries=32
  43 SSITSize=1024
  44 activity=0
  45 backComSize=5
  46 cachePorts=200
  47 checker=Null
  48 choiceCtrBits=2
  49 choicePredictorSize=8192
  50 clock=500
  51 commitToDecodeDelay=1
  52 commitToFetchDelay=1
  53 commitToIEWDelay=1
  54 commitToRenameDelay=1
  55 commitWidth=8
  56 cpu_id=0
  57 decodeToFetchDelay=1
  58 decodeToRenameDelay=1
  59 decodeWidth=8
  60 dispatchWidth=8
  61 do_checkpoint_insts=true
  62 do_quiesce=true
  63 do_statistics_insts=true
  64 dtb=system.cpu.dtb
  65 fetchToDecodeDelay=1
  66 fetchTrapLatency=1
  67 fetchWidth=8
  68 forwardComSize=5
  69 fuPool=system.cpu.fuPool
  70 function_trace=false
  71 function_trace_start=0
  72 globalCtrBits=2
  73 globalHistoryBits=13
  74 globalPredictorSize=8192
  75 iewToCommitDelay=1
  76 iewToDecodeDelay=1
  77 iewToFetchDelay=1
  78 iewToRenameDelay=1
  79 instShiftAmt=2
  80 interrupts=system.cpu.interrupts
  81 isa=system.cpu.isa
  82 issueToExecuteDelay=1
  83 issueWidth=8
  84 itb=system.cpu.itb
  85 localCtrBits=2
  86 localHistoryBits=11
  87 localHistoryTableSize=2048
  88 localPredictorSize=2048
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=false
  94 numIQEntries=64
  95 numPhysFloatRegs=256
  96 numPhysIntRegs=256
  97 numROBEntries=192
  98 numRobs=1
  99 numThreads=1
 100 predType=tournament
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 smtCommitPolicy=RoundRobin
 109 smtFetchPolicy=SingleThread
 110 smtIQPolicy=Partitioned
 111 smtIQThreshold=100
 112 smtLSQPolicy=Partitioned
 113 smtLSQThreshold=100
 114 smtNumFetchingThreads=1
 115 smtROBPolicy=Partitioned
 116 smtROBThreshold=100
 117 squashWidth=8
 118 store_set_clear_period=250000
 119 switched_out=false
 120 system=system
 121 tracer=system.cpu.tracer
 122 trapLatency=13
 123 wbDepth=1
 124 wbWidth=8
 125 workload=system.cpu.workload
 126 dcache_port=system.cpu.dcache.cpu_side
 127 icache_port=system.cpu.icache.cpu_side
 128
 129 [system.cpu.dcache]
 130 type=BaseCache
 131 addr_ranges=0:18446744073709551615
 132 assoc=2
 133 block_size=64
 134 clock=500
 135 forward_snoops=true
 136 hit_latency=2
 137 is_top_level=true
 138 max_miss_count=0
 139 mshrs=4
 140 prefetch_on_access=false
 141 prefetcher=Null
 142 response_latency=2
 143 size=262144
 144 system=system
 145 tgts_per_mshr=20
 146 two_queue=false
 147 write_buffers=8
 148 cpu_side=system.cpu.dcache_port
 149 mem_side=system.cpu.toL2Bus.slave[1]
 150
 151 [system.cpu.dtb]
 152 type=ArmTLB
 153 children=walker
 154 size=64
 155 walker=system.cpu.dtb.walker
 156
 157 [system.cpu.dtb.walker]
 158 type=ArmTableWalker
 159 clock=500
 160 num_squash_per_cycle=2
 161 sys=system
 162 port=system.cpu.toL2Bus.slave[3]
 163
 164 [system.cpu.fuPool]
 165 type=FUPool
 166 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 167 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 168
 169 [system.cpu.fuPool.FUList0]
 170 type=FUDesc
 171 children=opList
 172 count=6
 173 opList=system.cpu.fuPool.FUList0.opList
 174
 175 [system.cpu.fuPool.FUList0.opList]
 176 type=OpDesc
 177 issueLat=1
 178 opClass=IntAlu
 179 opLat=1
 180
 181 [system.cpu.fuPool.FUList1]
 182 type=FUDesc
 183 children=opList0 opList1
 184 count=2
 185 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 186
 187 [system.cpu.fuPool.FUList1.opList0]
 188 type=OpDesc
 189 issueLat=1
 190 opClass=IntMult
 191 opLat=3
 192
 193 [system.cpu.fuPool.FUList1.opList1]
 194 type=OpDesc
 195 issueLat=19
 196 opClass=IntDiv
 197 opLat=20
 198
 199 [system.cpu.fuPool.FUList2]
 200 type=FUDesc
 201 children=opList0 opList1 opList2
 202 count=4
 203 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 204
 205 [system.cpu.fuPool.FUList2.opList0]
 206 type=OpDesc
 207 issueLat=1
 208 opClass=FloatAdd
 209 opLat=2
 210
 211 [system.cpu.fuPool.FUList2.opList1]
 212 type=OpDesc
 213 issueLat=1
 214 opClass=FloatCmp
 215 opLat=2
 216
 217 [system.cpu.fuPool.FUList2.opList2]
 218 type=OpDesc
 219 issueLat=1
 220 opClass=FloatCvt
 221 opLat=2
 222
 223 [system.cpu.fuPool.FUList3]
 224 type=FUDesc
 225 children=opList0 opList1 opList2
 226 count=2
 227 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 228
 229 [system.cpu.fuPool.FUList3.opList0]
 230 type=OpDesc
 231 issueLat=1
 232 opClass=FloatMult
 233 opLat=4
 234
 235 [system.cpu.fuPool.FUList3.opList1]
 236 type=OpDesc
 237 issueLat=12
 238 opClass=FloatDiv
 239 opLat=12
 240
 241 [system.cpu.fuPool.FUList3.opList2]
 242 type=OpDesc
 243 issueLat=24
 244 opClass=FloatSqrt
 245 opLat=24
 246
 247 [system.cpu.fuPool.FUList4]
 248 type=FUDesc
 249 children=opList
 250 count=0
 251 opList=system.cpu.fuPool.FUList4.opList
 252
 253 [system.cpu.fuPool.FUList4.opList]
 254 type=OpDesc
 255 issueLat=1
 256 opClass=MemRead
 257 opLat=1
 258
 259 [system.cpu.fuPool.FUList5]
 260 type=FUDesc
 261 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 262 count=4
 263 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 264
 265 [system.cpu.fuPool.FUList5.opList00]
 266 type=OpDesc
 267 issueLat=1
 268 opClass=SimdAdd
 269 opLat=1
 270
 271 [system.cpu.fuPool.FUList5.opList01]
 272 type=OpDesc
 273 issueLat=1
 274 opClass=SimdAddAcc
 275 opLat=1
 276
 277 [system.cpu.fuPool.FUList5.opList02]
 278 type=OpDesc
 279 issueLat=1
 280 opClass=SimdAlu
 281 opLat=1
 282
 283 [system.cpu.fuPool.FUList5.opList03]
 284 type=OpDesc
 285 issueLat=1
 286 opClass=SimdCmp
 287 opLat=1
 288
 289 [system.cpu.fuPool.FUList5.opList04]
 290 type=OpDesc
 291 issueLat=1
 292 opClass=SimdCvt
 293 opLat=1
 294
 295 [system.cpu.fuPool.FUList5.opList05]
 296 type=OpDesc
 297 issueLat=1
 298 opClass=SimdMisc
 299 opLat=1
 300
 301 [system.cpu.fuPool.FUList5.opList06]
 302 type=OpDesc
 303 issueLat=1
 304 opClass=SimdMult
 305 opLat=1
 306
 307 [system.cpu.fuPool.FUList5.opList07]
 308 type=OpDesc
 309 issueLat=1
 310 opClass=SimdMultAcc
 311 opLat=1
 312
 313 [system.cpu.fuPool.FUList5.opList08]
 314 type=OpDesc
 315 issueLat=1
 316 opClass=SimdShift
 317 opLat=1
 318
 319 [system.cpu.fuPool.FUList5.opList09]
 320 type=OpDesc
 321 issueLat=1
 322 opClass=SimdShiftAcc
 323 opLat=1
 324
 325 [system.cpu.fuPool.FUList5.opList10]
 326 type=OpDesc
 327 issueLat=1
 328 opClass=SimdSqrt
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList11]
 332 type=OpDesc
 333 issueLat=1
 334 opClass=SimdFloatAdd
 335 opLat=1
 336
 337 [system.cpu.fuPool.FUList5.opList12]
 338 type=OpDesc
 339 issueLat=1
 340 opClass=SimdFloatAlu
 341 opLat=1
 342
 343 [system.cpu.fuPool.FUList5.opList13]
 344 type=OpDesc
 345 issueLat=1
 346 opClass=SimdFloatCmp
 347 opLat=1
 348
 349 [system.cpu.fuPool.FUList5.opList14]
 350 type=OpDesc
 351 issueLat=1
 352 opClass=SimdFloatCvt
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList15]
 356 type=OpDesc
 357 issueLat=1
 358 opClass=SimdFloatDiv
 359 opLat=1
 360
 361 [system.cpu.fuPool.FUList5.opList16]
 362 type=OpDesc
 363 issueLat=1
 364 opClass=SimdFloatMisc
 365 opLat=1
 366
 367 [system.cpu.fuPool.FUList5.opList17]
 368 type=OpDesc
 369 issueLat=1
 370 opClass=SimdFloatMult
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList18]
 374 type=OpDesc
 375 issueLat=1
 376 opClass=SimdFloatMultAcc
 377 opLat=1
 378
 379 [system.cpu.fuPool.FUList5.opList19]
 380 type=OpDesc
 381 issueLat=1
 382 opClass=SimdFloatSqrt
 383 opLat=1
 384
 385 [system.cpu.fuPool.FUList6]
 386 type=FUDesc
 387 children=opList
 388 count=0
 389 opList=system.cpu.fuPool.FUList6.opList
 390
 391 [system.cpu.fuPool.FUList6.opList]
 392 type=OpDesc
 393 issueLat=1
 394 opClass=MemWrite
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList7]
 398 type=FUDesc
 399 children=opList0 opList1
 400 count=4
 401 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 402
 403 [system.cpu.fuPool.FUList7.opList0]
 404 type=OpDesc
 405 issueLat=1
 406 opClass=MemRead
 407 opLat=1
 408
 409 [system.cpu.fuPool.FUList7.opList1]
 410 type=OpDesc
 411 issueLat=1
 412 opClass=MemWrite
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList8]
 416 type=FUDesc
 417 children=opList
 418 count=1
 419 opList=system.cpu.fuPool.FUList8.opList
 420
 421 [system.cpu.fuPool.FUList8.opList]
 422 type=OpDesc
 423 issueLat=3
 424 opClass=IprAccess
 425 opLat=3
 426
 427 [system.cpu.icache]
 428 type=BaseCache
 429 addr_ranges=0:18446744073709551615
 430 assoc=2
 431 block_size=64
 432 clock=500
 433 forward_snoops=true
 434 hit_latency=2
 435 is_top_level=true
 436 max_miss_count=0
 437 mshrs=4
 438 prefetch_on_access=false
 439 prefetcher=Null
 440 response_latency=2
 441 size=131072
 442 system=system
 443 tgts_per_mshr=20
 444 two_queue=false
 445 write_buffers=8
 446 cpu_side=system.cpu.icache_port
 447 mem_side=system.cpu.toL2Bus.slave[0]
 448
 449 [system.cpu.interrupts]
 450 type=ArmInterrupts
 451
 452 [system.cpu.isa]
 453 type=ArmISA
 454 fpsid=1090793632
 455 id_isar0=34607377
 456 id_isar1=34677009
 457 id_isar2=555950401
 458 id_isar3=17899825
 459 id_isar4=268501314
 460 id_isar5=0
 461 id_mmfr0=3
 462 id_mmfr1=0
 463 id_mmfr2=19070976
 464 id_mmfr3=4027589137
 465 id_pfr0=49
 466 id_pfr1=1
 467 midr=890224640
 468
 469 [system.cpu.itb]
 470 type=ArmTLB
 471 children=walker
 472 size=64
 473 walker=system.cpu.itb.walker
 474
 475 [system.cpu.itb.walker]
 476 type=ArmTableWalker
 477 clock=500
 478 num_squash_per_cycle=2
 479 sys=system
 480 port=system.cpu.toL2Bus.slave[2]
 481
 482 [system.cpu.l2cache]
 483 type=BaseCache
 484 addr_ranges=0:18446744073709551615
 485 assoc=8
 486 block_size=64
 487 clock=500
 488 forward_snoops=true
 489 hit_latency=20
 490 is_top_level=false
 491 max_miss_count=0
 492 mshrs=20
 493 prefetch_on_access=false
 494 prefetcher=Null
 495 response_latency=20
 496 size=2097152
 497 system=system
 498 tgts_per_mshr=12
 499 two_queue=false
 500 write_buffers=8
 501 cpu_side=system.cpu.toL2Bus.master[0]
 502 mem_side=system.membus.slave[1]
 503
 504 [system.cpu.toL2Bus]
 505 type=CoherentBus
 506 block_size=64
 507 clock=500
 508 header_cycles=1
 509 use_default_range=false
 510 width=32
 511 master=system.cpu.l2cache.cpu_side
 512 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 513
 514 [system.cpu.tracer]
 515 type=ExeTracer
 516
 517 [system.cpu.workload]
 518 type=LiveProcess
 519 cmd=perlbmk -I. -I lib lgred.makerand.pl
 520 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 521 egid=100
 522 env=
 523 errout=cerr
 524 euid=100
 525 executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk
 526 gid=100
 527 input=cin
 528 max_stack_size=67108864
 529 output=cout
 530 pid=100
 531 ppid=99
 532 simpoint=0
 533 system=system
 534 uid=100
 535
 536 [system.membus]
 537 type=CoherentBus
 538 block_size=64
 539 clock=1000
 540 header_cycles=1
 541 use_default_range=false
 542 width=8
 543 master=system.physmem.port
 544 slave=system.system_port system.cpu.l2cache.mem_side
 545
 546 [system.physmem]
 547 type=SimpleDRAM
 548 addr_mapping=openmap
 549 banks_per_rank=8
 550 clock=1000
 551 conf_table_reported=false
 552 in_addr_map=true
 553 lines_per_rowbuffer=64
 554 mem_sched_policy=fcfs
 555 null=false
 556 page_policy=open
 557 range=0:134217727
 558 ranks_per_channel=2
 559 read_buffer_size=32
 560 tBURST=4000
 561 tCL=14000
 562 tRCD=14000
 563 tREFI=7800000
 564 tRFC=300000
 565 tRP=14000
 566 tWTR=1000
 567 write_buffer_size=32
 568 write_thresh_perc=70
 569 zero=false
 570 port=system.membus.master[0]
 571