2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.627426 # Number of seconds simulated
4 sim_ticks 627426486000 # Number of ticks simulated
5 final_tick 627426486000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 65805 # Simulator instruction rate (inst/s)
8 host_op_rate 89618 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 29824381 # Simulator tick rate (ticks/s)
10 host_mem_usage 297136 # Number of bytes of host memory used
11 host_seconds 21037.37 # Real time elapsed on the host
12 sim_insts 1384370590 # Number of instructions simulated
13 sim_ops 1885325342 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 154240 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 30242112 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30396352 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 154240 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 154240 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 2410 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 472533 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 474943 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 245830 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 48200248 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 48446077 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 245830 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 245830 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 6742259 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 6742259 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 6742259 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 245830 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 48200248 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 55188336 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 474944 # Total number of read requests seen
38 system.physmem.writeReqs 66098 # Total number of write requests seen
39 system.physmem.cpureqs 545373 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 30396352 # Total number of bytes read from memory
41 system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 30396352 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 4331 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 29709 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 29700 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 29689 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 29719 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 29749 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 29652 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 29638 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 29679 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 29599 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 29613 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 29623 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 29684 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 29651 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 627426443000 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 474944 # Categorize read packet sizes
88 system.physmem.writePktSize::0 0 # Categorize write packet sizes
89 system.physmem.writePktSize::1 0 # Categorize write packet sizes
90 system.physmem.writePktSize::2 0 # Categorize write packet sizes
91 system.physmem.writePktSize::3 0 # Categorize write packet sizes
92 system.physmem.writePktSize::4 0 # Categorize write packet sizes
93 system.physmem.writePktSize::5 0 # Categorize write packet sizes
94 system.physmem.writePktSize::6 66098 # Categorize write packet sizes
95 system.physmem.rdQLenPdf::0 405886 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::1 66680 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
127 system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
159 system.physmem.totQLat 3439648250 # Total cycles spent in queuing delays
160 system.physmem.totMemAccLat 21418222000 # Sum of mem lat for all requests
161 system.physmem.totBusLat 2373960000 # Total cycles spent in databus access
162 system.physmem.totBankLat 15604613750 # Total cycles spent in bank access
163 system.physmem.avgQLat 7244.54 # Average queueing delay per request
164 system.physmem.avgBankLat 32866.21 # Average bank access latency per request
165 system.physmem.avgBusLat 5000.00 # Average bus latency per request
166 system.physmem.avgMemAccLat 45110.75 # Average memory access latency
167 system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s
168 system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
169 system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s
170 system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s
171 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172 system.physmem.busUtil 0.43 # Data bus utilization in percentage
173 system.physmem.avgRdQLen 0.03 # Average read queue length over time
174 system.physmem.avgWrQLen 17.42 # Average write queue length over time
175 system.physmem.readRowHits 143318 # Number of row buffer hits during reads
176 system.physmem.writeRowHits 45505 # Number of row buffer hits during writes
177 system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
178 system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes
179 system.physmem.avgGap 1159663.10 # Average gap between requests
180 system.cpu.branchPred.lookups 441070019 # Number of BP lookups
181 system.cpu.branchPred.condPredicted 353935839 # Number of conditional branches predicted
182 system.cpu.branchPred.condIncorrect 30635394 # Number of conditional branches incorrect
183 system.cpu.branchPred.BTBLookups 253577570 # Number of BTB lookups
184 system.cpu.branchPred.BTBHits 230740155 # Number of BTB hits
185 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
186 system.cpu.branchPred.BTBHitPct 90.993914 # BTB Hit Percentage
187 system.cpu.branchPred.usedRAS 51827244 # Number of times the RAS was used to get a target.
188 system.cpu.branchPred.RASInCorrect 2806499 # Number of incorrect RAS predictions.
189 system.cpu.dtb.inst_hits 0 # ITB inst hits
190 system.cpu.dtb.inst_misses 0 # ITB inst misses
191 system.cpu.dtb.read_hits 0 # DTB read hits
192 system.cpu.dtb.read_misses 0 # DTB read misses
193 system.cpu.dtb.write_hits 0 # DTB write hits
194 system.cpu.dtb.write_misses 0 # DTB write misses
195 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
196 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
197 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
198 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
199 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
200 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
201 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
202 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
203 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
204 system.cpu.dtb.read_accesses 0 # DTB read accesses
205 system.cpu.dtb.write_accesses 0 # DTB write accesses
206 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
207 system.cpu.dtb.hits 0 # DTB hits
208 system.cpu.dtb.misses 0 # DTB misses
209 system.cpu.dtb.accesses 0 # DTB accesses
210 system.cpu.itb.inst_hits 0 # ITB inst hits
211 system.cpu.itb.inst_misses 0 # ITB inst misses
212 system.cpu.itb.read_hits 0 # DTB read hits
213 system.cpu.itb.read_misses 0 # DTB read misses
214 system.cpu.itb.write_hits 0 # DTB write hits
215 system.cpu.itb.write_misses 0 # DTB write misses
216 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
217 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
218 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
219 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
220 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
221 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
222 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
223 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
224 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
225 system.cpu.itb.read_accesses 0 # DTB read accesses
226 system.cpu.itb.write_accesses 0 # DTB write accesses
227 system.cpu.itb.inst_accesses 0 # ITB inst accesses
228 system.cpu.itb.hits 0 # DTB hits
229 system.cpu.itb.misses 0 # DTB misses
230 system.cpu.itb.accesses 0 # DTB accesses
231 system.cpu.workload.num_syscalls 1411 # Number of system calls
232 system.cpu.numCycles 1254852973 # number of cpu cycles simulated
233 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
234 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
235 system.cpu.fetch.icacheStallCycles 354891147 # Number of cycles fetch is stalled on an Icache miss
236 system.cpu.fetch.Insts 2286425176 # Number of instructions fetch has processed
237 system.cpu.fetch.Branches 441070019 # Number of branches that fetch encountered
238 system.cpu.fetch.predictedBranches 282567399 # Number of branches that fetch has predicted taken
239 system.cpu.fetch.Cycles 601918215 # Number of cycles fetch has run and was not squashing or blocked
240 system.cpu.fetch.SquashCycles 156601137 # Number of cycles fetch has spent squashing
241 system.cpu.fetch.BlockedCycles 130017521 # Number of cycles fetch has spent blocked
242 system.cpu.fetch.MiscStallCycles 563 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243 system.cpu.fetch.PendingTrapStallCycles 11246 # Number of stall cycles due to pending traps
244 system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
245 system.cpu.fetch.CacheLines 335797832 # Number of cache lines fetched
246 system.cpu.fetch.IcacheSquashes 11972922 # Number of outstanding Icache misses that were squashed
247 system.cpu.fetch.rateDist::samples 1212752602 # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::mean 2.588148 # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::stdev 3.180737 # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::0 610879185 50.37% 50.37% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::1 42915841 3.54% 53.91% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::2 96172627 7.93% 61.84% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::3 57091199 4.71% 66.55% # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::4 71993232 5.94% 72.48% # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::5 43518781 3.59% 76.07% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::6 30912276 2.55% 78.62% # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::7 32947513 2.72% 81.34% # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::8 226321948 18.66% 100.00% # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::total 1212752602 # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.branchRate 0.351491 # Number of branch fetches per cycle
265 system.cpu.fetch.rate 1.822066 # Number of inst fetches per cycle
266 system.cpu.decode.IdleCycles 405845320 # Number of cycles decode is idle
267 system.cpu.decode.BlockedCycles 102427093 # Number of cycles decode is blocked
268 system.cpu.decode.RunCycles 561818768 # Number of cycles decode is running
269 system.cpu.decode.UnblockCycles 16761536 # Number of cycles decode is unblocking
270 system.cpu.decode.SquashCycles 125899885 # Number of cycles decode is squashing
271 system.cpu.decode.BranchResolved 44789430 # Number of times decode resolved a branch
272 system.cpu.decode.BranchMispred 14217 # Number of times decode detected a branch misprediction
273 system.cpu.decode.DecodedInsts 3028082478 # Number of instructions handled by decode
274 system.cpu.decode.SquashedInsts 30107 # Number of squashed instructions handled by decode
275 system.cpu.rename.SquashCycles 125899885 # Number of cycles rename is squashing
276 system.cpu.rename.IdleCycles 441818256 # Number of cycles rename is idle
277 system.cpu.rename.BlockCycles 34409054 # Number of cycles rename is blocking
278 system.cpu.rename.serializeStallCycles 439229 # count of cycles rename stalled for serializing inst
279 system.cpu.rename.RunCycles 540562916 # Number of cycles rename is running
280 system.cpu.rename.UnblockCycles 69623262 # Number of cycles rename is unblocking
281 system.cpu.rename.RenamedInsts 2944183318 # Number of instructions processed by rename
282 system.cpu.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
283 system.cpu.rename.IQFullEvents 4821524 # Number of times rename has blocked due to IQ full
284 system.cpu.rename.LSQFullEvents 54501316 # Number of times rename has blocked due to LSQ full
285 system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
286 system.cpu.rename.RenamedOperands 2929324563 # Number of destination operands rename has renamed
287 system.cpu.rename.RenameLookups 14012451828 # Number of register rename lookups that rename has made
288 system.cpu.rename.int_rename_lookups 13441344414 # Number of integer rename lookups
289 system.cpu.rename.fp_rename_lookups 571107414 # Number of floating rename lookups
290 system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
291 system.cpu.rename.UndoneMaps 936184473 # Number of HB maps that are undone due to squashing
292 system.cpu.rename.serializingInsts 21713 # count of serializing insts renamed
293 system.cpu.rename.tempSerializingInsts 19183 # count of temporary serializing insts renamed
294 system.cpu.rename.skidInsts 177423093 # count of insts added to the skid buffer
295 system.cpu.memDep0.insertedLoads 969808911 # Number of loads inserted to the mem dependence unit.
296 system.cpu.memDep0.insertedStores 487407647 # Number of stores inserted to the mem dependence unit.
297 system.cpu.memDep0.conflictingLoads 36223294 # Number of conflicting loads.
298 system.cpu.memDep0.conflictingStores 40155637 # Number of conflicting stores.
299 system.cpu.iq.iqInstsAdded 2791556624 # Number of instructions added to the IQ (excludes non-spec)
300 system.cpu.iq.iqNonSpecInstsAdded 29091 # Number of non-speculative instructions added to the IQ
301 system.cpu.iq.iqInstsIssued 2432817301 # Number of instructions issued
302 system.cpu.iq.iqSquashedInstsIssued 13264046 # Number of squashed instructions issued
303 system.cpu.iq.iqSquashedInstsExamined 893693392 # Number of squashed instructions iterated over during squash; mainly for profiling
304 system.cpu.iq.iqSquashedOperandsExamined 2309057295 # Number of squashed operands that are examined and possibly removed from graph
305 system.cpu.iq.iqSquashedNonSpecRemoved 7707 # Number of squashed non-spec instructions that were removed
306 system.cpu.iq.issued_per_cycle::samples 1212752602 # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::mean 2.006029 # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::stdev 1.872054 # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::0 376736827 31.06% 31.06% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::1 183745627 15.15% 46.22% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::2 204018800 16.82% 63.04% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::3 169675350 13.99% 77.03% # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::4 132825359 10.95% 87.98% # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::5 92323584 7.61% 95.59% # Number of insts issued each cycle
316 system.cpu.iq.issued_per_cycle::6 37944626 3.13% 98.72% # Number of insts issued each cycle
317 system.cpu.iq.issued_per_cycle::7 12438520 1.03% 99.75% # Number of insts issued each cycle
318 system.cpu.iq.issued_per_cycle::8 3043909 0.25% 100.00% # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::total 1212752602 # Number of insts issued each cycle
323 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
324 system.cpu.iq.fu_full::IntAlu 715136 0.82% 0.82% # attempts to use FU when none available
325 system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
326 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
327 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
328 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
329 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
330 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
331 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
332 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
353 system.cpu.iq.fu_full::MemRead 55109735 62.90% 63.74% # attempts to use FU when none available
354 system.cpu.iq.fu_full::MemWrite 31764891 36.26% 100.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
356 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
357 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
358 system.cpu.iq.FU_type_0::IntAlu 1103878887 45.37% 45.37% # Type of FU issued
359 system.cpu.iq.FU_type_0::IntMult 11223380 0.46% 45.84% # Type of FU issued
360 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
361 system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued
362 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
363 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
364 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
365 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
366 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.89% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.89% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.18% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdFloatCvt 5503230 0.23% 46.40% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdFloatMisc 23422628 0.96% 47.36% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.36% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.36% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.36% # Type of FU issued
387 system.cpu.iq.FU_type_0::MemRead 838195655 34.45% 81.82% # Type of FU issued
388 system.cpu.iq.FU_type_0::MemWrite 442341757 18.18% 100.00% # Type of FU issued
389 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
390 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
391 system.cpu.iq.FU_type_0::total 2432817301 # Type of FU issued
392 system.cpu.iq.rate 1.938727 # Inst issue rate
393 system.cpu.iq.fu_busy_cnt 87614143 # FU busy when requested
394 system.cpu.iq.fu_busy_rate 0.036013 # FU busy rate (busy events/executed inst)
395 system.cpu.iq.int_inst_queue_reads 6056711081 # Number of integer instruction queue reads
396 system.cpu.iq.int_inst_queue_writes 3602481479 # Number of integer instruction queue writes
397 system.cpu.iq.int_inst_queue_wakeup_accesses 2248827251 # Number of integer instruction queue wakeup accesses
398 system.cpu.iq.fp_inst_queue_reads 122554312 # Number of floating instruction queue reads
399 system.cpu.iq.fp_inst_queue_writes 82864717 # Number of floating instruction queue writes
400 system.cpu.iq.fp_inst_queue_wakeup_accesses 56458852 # Number of floating instruction queue wakeup accesses
401 system.cpu.iq.int_alu_accesses 2457090579 # Number of integer alu accesses
402 system.cpu.iq.fp_alu_accesses 63340865 # Number of floating point alu accesses
403 system.cpu.iew.lsq.thread0.forwLoads 84315452 # Number of loads that had data forwarded from stores
404 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
405 system.cpu.iew.lsq.thread0.squashedLoads 338421730 # Number of loads squashed
406 system.cpu.iew.lsq.thread0.ignoredResponses 8530 # Number of memory responses ignored because the instruction is squashed
407 system.cpu.iew.lsq.thread0.memOrderViolation 1429952 # Number of memory ordering violations
408 system.cpu.iew.lsq.thread0.squashedStores 210412350 # Number of stores squashed
409 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
410 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
411 system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
412 system.cpu.iew.lsq.thread0.cacheBlocked 257 # Number of times an access to memory failed due to the cache being blocked
413 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
414 system.cpu.iew.iewSquashCycles 125899885 # Number of cycles IEW is squashing
415 system.cpu.iew.iewBlockCycles 12642453 # Number of cycles IEW is blocking
416 system.cpu.iew.iewUnblockCycles 1559188 # Number of cycles IEW is unblocking
417 system.cpu.iew.iewDispatchedInsts 2791598235 # Number of instructions dispatched to IQ
418 system.cpu.iew.iewDispSquashedInsts 1393439 # Number of squashed instructions skipped by dispatch
419 system.cpu.iew.iewDispLoadInsts 969808911 # Number of dispatched load instructions
420 system.cpu.iew.iewDispStoreInsts 487407647 # Number of dispatched store instructions
421 system.cpu.iew.iewDispNonSpecInsts 19105 # Number of dispatched non-speculative instructions
422 system.cpu.iew.iewIQFullEvents 1555218 # Number of times the IQ has become full, causing a stall
423 system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall
424 system.cpu.iew.memOrderViolationEvents 1429952 # Number of memory order violations
425 system.cpu.iew.predictedTakenIncorrect 32462166 # Number of branches that were predicted taken incorrectly
426 system.cpu.iew.predictedNotTakenIncorrect 1535020 # Number of branches that were predicted not taken incorrectly
427 system.cpu.iew.branchMispredicts 33997186 # Number of branch mispredicts detected at execute
428 system.cpu.iew.iewExecutedInsts 2358042615 # Number of executed instructions
429 system.cpu.iew.iewExecLoadInsts 792538170 # Number of load instructions executed
430 system.cpu.iew.iewExecSquashedInsts 74774686 # Number of squashed instructions skipped in execute
431 system.cpu.iew.exec_swp 0 # number of swp insts executed
432 system.cpu.iew.exec_nop 12520 # number of nop insts executed
433 system.cpu.iew.exec_refs 1216339727 # number of memory reference insts executed
434 system.cpu.iew.exec_branches 319851158 # Number of branches executed
435 system.cpu.iew.exec_stores 423801557 # Number of stores executed
436 system.cpu.iew.exec_rate 1.879139 # Inst execution rate
437 system.cpu.iew.wb_sent 2331014082 # cumulative count of insts sent to commit
438 system.cpu.iew.wb_count 2305286103 # cumulative count of insts written-back
439 system.cpu.iew.wb_producers 1347320139 # num instructions producing a value
440 system.cpu.iew.wb_consumers 2523004414 # num instructions consuming a value
441 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
442 system.cpu.iew.wb_rate 1.837097 # insts written-back per cycle
443 system.cpu.iew.wb_fanout 0.534014 # average fanout of values written-back
444 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
445 system.cpu.commit.commitSquashedInsts 906262003 # The number of squashed insts skipped by commit
446 system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
447 system.cpu.commit.branchMispredicts 30621444 # The number of times a branch was mispredicted
448 system.cpu.commit.committed_per_cycle::samples 1086852717 # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::mean 1.734675 # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::stdev 2.398797 # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::0 446522418 41.08% 41.08% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::1 288653852 26.56% 67.64% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::2 95098505 8.75% 76.39% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::3 70200543 6.46% 82.85% # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::4 46464549 4.28% 87.13% # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::5 22199454 2.04% 89.17% # Number of insts commited each cycle
458 system.cpu.commit.committed_per_cycle::6 15846996 1.46% 90.63% # Number of insts commited each cycle
459 system.cpu.commit.committed_per_cycle::7 10984775 1.01% 91.64% # Number of insts commited each cycle
460 system.cpu.commit.committed_per_cycle::8 90881625 8.36% 100.00% # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::total 1086852717 # Number of insts commited each cycle
465 system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
466 system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
467 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
468 system.cpu.commit.refs 908382478 # Number of memory references committed
469 system.cpu.commit.loads 631387181 # Number of loads committed
470 system.cpu.commit.membars 9986 # Number of memory barriers committed
471 system.cpu.commit.branches 298259106 # Number of branches committed
472 system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
473 system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
474 system.cpu.commit.function_calls 41577833 # Number of function calls committed.
475 system.cpu.commit.bw_lim_events 90881625 # number cycles where commit BW limit reached
476 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
477 system.cpu.rob.rob_reads 3787551108 # The number of ROB reads
478 system.cpu.rob.rob_writes 5709107671 # The number of ROB writes
479 system.cpu.timesIdled 353124 # Number of times that the entire CPU went into an idle state and unscheduled itself
480 system.cpu.idleCycles 42100371 # Total number of cycles that the CPU has spent unscheduled due to idling
481 system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
482 system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
483 system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
484 system.cpu.cpi 0.906443 # CPI: Cycles Per Instruction
485 system.cpu.cpi_total 0.906443 # CPI: Total CPI of All Threads
486 system.cpu.ipc 1.103213 # IPC: Instructions Per Cycle
487 system.cpu.ipc_total 1.103213 # IPC: Total IPC of All Threads
488 system.cpu.int_regfile_reads 11756785732 # number of integer regfile reads
489 system.cpu.int_regfile_writes 2218462767 # number of integer regfile writes
490 system.cpu.fp_regfile_reads 68799116 # number of floating regfile reads
491 system.cpu.fp_regfile_writes 49570496 # number of floating regfile writes
492 system.cpu.misc_regfile_reads 1364149303 # number of misc regfile reads
493 system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
494 system.cpu.icache.replacements 22544 # number of replacements
495 system.cpu.icache.tagsinuse 1643.593682 # Cycle average of tags in use
496 system.cpu.icache.total_refs 335759855 # Total number of references to valid blocks.
497 system.cpu.icache.sampled_refs 24228 # Sample count of references to valid blocks.
498 system.cpu.icache.avg_refs 13858.339731 # Average number of references to valid blocks.
499 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
500 system.cpu.icache.occ_blocks::cpu.inst 1643.593682 # Average occupied blocks per requestor
501 system.cpu.icache.occ_percent::cpu.inst 0.802536 # Average percentage of cache occupancy
502 system.cpu.icache.occ_percent::total 0.802536 # Average percentage of cache occupancy
503 system.cpu.icache.ReadReq_hits::cpu.inst 335766423 # number of ReadReq hits
504 system.cpu.icache.ReadReq_hits::total 335766423 # number of ReadReq hits
505 system.cpu.icache.demand_hits::cpu.inst 335766423 # number of demand (read+write) hits
506 system.cpu.icache.demand_hits::total 335766423 # number of demand (read+write) hits
507 system.cpu.icache.overall_hits::cpu.inst 335766423 # number of overall hits
508 system.cpu.icache.overall_hits::total 335766423 # number of overall hits
509 system.cpu.icache.ReadReq_misses::cpu.inst 31408 # number of ReadReq misses
510 system.cpu.icache.ReadReq_misses::total 31408 # number of ReadReq misses
511 system.cpu.icache.demand_misses::cpu.inst 31408 # number of demand (read+write) misses
512 system.cpu.icache.demand_misses::total 31408 # number of demand (read+write) misses
513 system.cpu.icache.overall_misses::cpu.inst 31408 # number of overall misses
514 system.cpu.icache.overall_misses::total 31408 # number of overall misses
515 system.cpu.icache.ReadReq_miss_latency::cpu.inst 477378999 # number of ReadReq miss cycles
516 system.cpu.icache.ReadReq_miss_latency::total 477378999 # number of ReadReq miss cycles
517 system.cpu.icache.demand_miss_latency::cpu.inst 477378999 # number of demand (read+write) miss cycles
518 system.cpu.icache.demand_miss_latency::total 477378999 # number of demand (read+write) miss cycles
519 system.cpu.icache.overall_miss_latency::cpu.inst 477378999 # number of overall miss cycles
520 system.cpu.icache.overall_miss_latency::total 477378999 # number of overall miss cycles
521 system.cpu.icache.ReadReq_accesses::cpu.inst 335797831 # number of ReadReq accesses(hits+misses)
522 system.cpu.icache.ReadReq_accesses::total 335797831 # number of ReadReq accesses(hits+misses)
523 system.cpu.icache.demand_accesses::cpu.inst 335797831 # number of demand (read+write) accesses
524 system.cpu.icache.demand_accesses::total 335797831 # number of demand (read+write) accesses
525 system.cpu.icache.overall_accesses::cpu.inst 335797831 # number of overall (read+write) accesses
526 system.cpu.icache.overall_accesses::total 335797831 # number of overall (read+write) accesses
527 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses
528 system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses
529 system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses
530 system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses
531 system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses
532 system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses
533 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15199.280406 # average ReadReq miss latency
534 system.cpu.icache.ReadReq_avg_miss_latency::total 15199.280406 # average ReadReq miss latency
535 system.cpu.icache.demand_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency
536 system.cpu.icache.demand_avg_miss_latency::total 15199.280406 # average overall miss latency
537 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency
538 system.cpu.icache.overall_avg_miss_latency::total 15199.280406 # average overall miss latency
539 system.cpu.icache.blocked_cycles::no_mshrs 872 # number of cycles access was blocked
540 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541 system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
542 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
543 system.cpu.icache.avg_blocked_cycles::no_mshrs 33.538462 # average number of cycles each access was blocked
544 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545 system.cpu.icache.fast_writes 0 # number of fast writes performed
546 system.cpu.icache.cache_copies 0 # number of cache copies performed
547 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2844 # number of ReadReq MSHR hits
548 system.cpu.icache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits
549 system.cpu.icache.demand_mshr_hits::cpu.inst 2844 # number of demand (read+write) MSHR hits
550 system.cpu.icache.demand_mshr_hits::total 2844 # number of demand (read+write) MSHR hits
551 system.cpu.icache.overall_mshr_hits::cpu.inst 2844 # number of overall MSHR hits
552 system.cpu.icache.overall_mshr_hits::total 2844 # number of overall MSHR hits
553 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses
554 system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
555 system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses
556 system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
557 system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
558 system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
559 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 383349499 # number of ReadReq MSHR miss cycles
560 system.cpu.icache.ReadReq_mshr_miss_latency::total 383349499 # number of ReadReq MSHR miss cycles
561 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 383349499 # number of demand (read+write) MSHR miss cycles
562 system.cpu.icache.demand_mshr_miss_latency::total 383349499 # number of demand (read+write) MSHR miss cycles
563 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 383349499 # number of overall MSHR miss cycles
564 system.cpu.icache.overall_mshr_miss_latency::total 383349499 # number of overall MSHR miss cycles
565 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses
566 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses
567 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses
568 system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses
569 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses
570 system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses
571 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13420.721853 # average ReadReq mshr miss latency
572 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13420.721853 # average ReadReq mshr miss latency
573 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13420.721853 # average overall mshr miss latency
574 system.cpu.icache.demand_avg_mshr_miss_latency::total 13420.721853 # average overall mshr miss latency
575 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13420.721853 # average overall mshr miss latency
576 system.cpu.icache.overall_avg_mshr_miss_latency::total 13420.721853 # average overall mshr miss latency
577 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
578 system.cpu.l2cache.replacements 442161 # number of replacements
579 system.cpu.l2cache.tagsinuse 32692.602580 # Cycle average of tags in use
580 system.cpu.l2cache.total_refs 1109878 # Total number of references to valid blocks.
581 system.cpu.l2cache.sampled_refs 474908 # Sample count of references to valid blocks.
582 system.cpu.l2cache.avg_refs 2.337038 # Average number of references to valid blocks.
583 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
584 system.cpu.l2cache.occ_blocks::writebacks 1286.251763 # Average occupied blocks per requestor
585 system.cpu.l2cache.occ_blocks::cpu.inst 48.224535 # Average occupied blocks per requestor
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593 system.cpu.l2cache.ReadReq_hits::total 1080046 # number of ReadReq hits
594 system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits
595 system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits
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599 system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
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603 system.cpu.l2cache.overall_hits::cpu.inst 21816 # number of overall hits
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605 system.cpu.l2cache.overall_hits::total 1086487 # number of overall hits
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608 system.cpu.l2cache.ReadReq_misses::total 408890 # number of ReadReq misses
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610 system.cpu.l2cache.UpgradeReq_misses::total 4331 # number of UpgradeReq misses
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612 system.cpu.l2cache.ReadExReq_misses::total 66078 # number of ReadExReq misses
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617 system.cpu.l2cache.overall_misses::cpu.data 472553 # number of overall misses
618 system.cpu.l2cache.overall_misses::total 474968 # number of overall misses
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620 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29040737500 # number of ReadReq miss cycles
621 system.cpu.l2cache.ReadReq_miss_latency::total 29172773500 # number of ReadReq miss cycles
622 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174388500 # number of ReadExReq miss cycles
623 system.cpu.l2cache.ReadExReq_miss_latency::total 3174388500 # number of ReadExReq miss cycles
624 system.cpu.l2cache.demand_miss_latency::cpu.inst 132036000 # number of demand (read+write) miss cycles
625 system.cpu.l2cache.demand_miss_latency::cpu.data 32215126000 # number of demand (read+write) miss cycles
626 system.cpu.l2cache.demand_miss_latency::total 32347162000 # number of demand (read+write) miss cycles
627 system.cpu.l2cache.overall_miss_latency::cpu.inst 132036000 # number of overall miss cycles
628 system.cpu.l2cache.overall_miss_latency::cpu.data 32215126000 # number of overall miss cycles
629 system.cpu.l2cache.overall_miss_latency::total 32347162000 # number of overall miss cycles
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631 system.cpu.l2cache.ReadReq_accesses::cpu.data 1464705 # number of ReadReq accesses(hits+misses)
632 system.cpu.l2cache.ReadReq_accesses::total 1488936 # number of ReadReq accesses(hits+misses)
633 system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses)
634 system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses)
635 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4334 # number of UpgradeReq accesses(hits+misses)
636 system.cpu.l2cache.UpgradeReq_accesses::total 4334 # number of UpgradeReq accesses(hits+misses)
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638 system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
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643 system.cpu.l2cache.overall_accesses::cpu.data 1537224 # number of overall (read+write) accesses
644 system.cpu.l2cache.overall_accesses::total 1561455 # number of overall (read+write) accesses
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646 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277513 # miss rate for ReadReq accesses
647 system.cpu.l2cache.ReadReq_miss_rate::total 0.274619 # miss rate for ReadReq accesses
648 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999308 # miss rate for UpgradeReq accesses
649 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999308 # miss rate for UpgradeReq accesses
650 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911182 # miss rate for ReadExReq accesses
651 system.cpu.l2cache.ReadExReq_miss_rate::total 0.911182 # miss rate for ReadExReq accesses
652 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099666 # miss rate for demand accesses
653 system.cpu.l2cache.demand_miss_rate::cpu.data 0.307407 # miss rate for demand accesses
654 system.cpu.l2cache.demand_miss_rate::total 0.304183 # miss rate for demand accesses
655 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099666 # miss rate for overall accesses
656 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307407 # miss rate for overall accesses
657 system.cpu.l2cache.overall_miss_rate::total 0.304183 # miss rate for overall accesses
658 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54673.291925 # average ReadReq miss latency
659 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71445.322591 # average ReadReq miss latency
660 system.cpu.l2cache.ReadReq_avg_miss_latency::total 71346.263054 # average ReadReq miss latency
661 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.020884 # average ReadExReq miss latency
662 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.020884 # average ReadExReq miss latency
663 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54673.291925 # average overall miss latency
664 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68172.513983 # average overall miss latency
665 system.cpu.l2cache.demand_avg_miss_latency::total 68103.876472 # average overall miss latency
666 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54673.291925 # average overall miss latency
667 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68172.513983 # average overall miss latency
668 system.cpu.l2cache.overall_avg_miss_latency::total 68103.876472 # average overall miss latency
669 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
670 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
671 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
672 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
673 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
674 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
675 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
676 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
677 system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
678 system.cpu.l2cache.writebacks::total 66098 # number of writebacks
679 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
680 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits
681 system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
682 system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
683 system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits
684 system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
685 system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
686 system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits
687 system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
688 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2411 # number of ReadReq MSHR misses
689 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406455 # number of ReadReq MSHR misses
690 system.cpu.l2cache.ReadReq_mshr_misses::total 408866 # number of ReadReq MSHR misses
691 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4331 # number of UpgradeReq MSHR misses
692 system.cpu.l2cache.UpgradeReq_mshr_misses::total 4331 # number of UpgradeReq MSHR misses
693 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses
694 system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses
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696 system.cpu.l2cache.demand_mshr_misses::cpu.data 472533 # number of demand (read+write) MSHR misses
697 system.cpu.l2cache.demand_mshr_misses::total 474944 # number of demand (read+write) MSHR misses
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699 system.cpu.l2cache.overall_mshr_misses::cpu.data 472533 # number of overall MSHR misses
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702 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23985260933 # number of ReadReq MSHR miss cycles
703 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24087240603 # number of ReadReq MSHR miss cycles
704 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43314331 # number of UpgradeReq MSHR miss cycles
705 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43314331 # number of UpgradeReq MSHR miss cycles
706 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357175037 # number of ReadExReq MSHR miss cycles
707 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357175037 # number of ReadExReq MSHR miss cycles
708 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101979670 # number of demand (read+write) MSHR miss cycles
709 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26342435970 # number of demand (read+write) MSHR miss cycles
710 system.cpu.l2cache.demand_mshr_miss_latency::total 26444415640 # number of demand (read+write) MSHR miss cycles
711 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101979670 # number of overall MSHR miss cycles
712 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26342435970 # number of overall MSHR miss cycles
713 system.cpu.l2cache.overall_mshr_miss_latency::total 26444415640 # number of overall MSHR miss cycles
714 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for ReadReq accesses
715 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277500 # mshr miss rate for ReadReq accesses
716 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274603 # mshr miss rate for ReadReq accesses
717 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses
718 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses
719 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911182 # mshr miss rate for ReadExReq accesses
720 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911182 # mshr miss rate for ReadExReq accesses
721 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for demand accesses
722 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307394 # mshr miss rate for demand accesses
723 system.cpu.l2cache.demand_mshr_miss_rate::total 0.304168 # mshr miss rate for demand accesses
724 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099501 # mshr miss rate for overall accesses
725 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307394 # mshr miss rate for overall accesses
726 system.cpu.l2cache.overall_mshr_miss_rate::total 0.304168 # mshr miss rate for overall accesses
727 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42297.664869 # average ReadReq mshr miss latency
728 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59010.864507 # average ReadReq mshr miss latency
729 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58912.310153 # average ReadReq mshr miss latency
730 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
731 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
732 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.614743 # average ReadExReq mshr miss latency
733 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.614743 # average ReadExReq mshr miss latency
734 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42297.664869 # average overall mshr miss latency
735 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55747.293776 # average overall mshr miss latency
736 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55679.018242 # average overall mshr miss latency
737 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42297.664869 # average overall mshr miss latency
738 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55747.293776 # average overall mshr miss latency
739 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55679.018242 # average overall mshr miss latency
740 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
741 system.cpu.dcache.replacements 1533127 # number of replacements
742 system.cpu.dcache.tagsinuse 4094.655328 # Cycle average of tags in use
743 system.cpu.dcache.total_refs 969949757 # Total number of references to valid blocks.
744 system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks.
745 system.cpu.dcache.avg_refs 630.975309 # Average number of references to valid blocks.
746 system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit.
747 system.cpu.dcache.occ_blocks::cpu.data 4094.655328 # Average occupied blocks per requestor
748 system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy
749 system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy
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751 system.cpu.dcache.ReadReq_hits::total 693823143 # number of ReadReq hits
752 system.cpu.dcache.WriteReq_hits::cpu.data 276093651 # number of WriteReq hits
753 system.cpu.dcache.WriteReq_hits::total 276093651 # number of WriteReq hits
754 system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
755 system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
756 system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
757 system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
758 system.cpu.dcache.demand_hits::cpu.data 969916794 # number of demand (read+write) hits
759 system.cpu.dcache.demand_hits::total 969916794 # number of demand (read+write) hits
760 system.cpu.dcache.overall_hits::cpu.data 969916794 # number of overall hits
761 system.cpu.dcache.overall_hits::total 969916794 # number of overall hits
762 system.cpu.dcache.ReadReq_misses::cpu.data 1953499 # number of ReadReq misses
763 system.cpu.dcache.ReadReq_misses::total 1953499 # number of ReadReq misses
764 system.cpu.dcache.WriteReq_misses::cpu.data 842027 # number of WriteReq misses
765 system.cpu.dcache.WriteReq_misses::total 842027 # number of WriteReq misses
766 system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
767 system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
768 system.cpu.dcache.demand_misses::cpu.data 2795526 # number of demand (read+write) misses
769 system.cpu.dcache.demand_misses::total 2795526 # number of demand (read+write) misses
770 system.cpu.dcache.overall_misses::cpu.data 2795526 # number of overall misses
771 system.cpu.dcache.overall_misses::total 2795526 # number of overall misses
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773 system.cpu.dcache.ReadReq_miss_latency::total 66742188500 # number of ReadReq miss cycles
774 system.cpu.dcache.WriteReq_miss_latency::cpu.data 39429860969 # number of WriteReq miss cycles
775 system.cpu.dcache.WriteReq_miss_latency::total 39429860969 # number of WriteReq miss cycles
776 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles
777 system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles
778 system.cpu.dcache.demand_miss_latency::cpu.data 106172049469 # number of demand (read+write) miss cycles
779 system.cpu.dcache.demand_miss_latency::total 106172049469 # number of demand (read+write) miss cycles
780 system.cpu.dcache.overall_miss_latency::cpu.data 106172049469 # number of overall miss cycles
781 system.cpu.dcache.overall_miss_latency::total 106172049469 # number of overall miss cycles
782 system.cpu.dcache.ReadReq_accesses::cpu.data 695776642 # number of ReadReq accesses(hits+misses)
783 system.cpu.dcache.ReadReq_accesses::total 695776642 # number of ReadReq accesses(hits+misses)
784 system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
785 system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
786 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
787 system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
788 system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
789 system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
790 system.cpu.dcache.demand_accesses::cpu.data 972712320 # number of demand (read+write) accesses
791 system.cpu.dcache.demand_accesses::total 972712320 # number of demand (read+write) accesses
792 system.cpu.dcache.overall_accesses::cpu.data 972712320 # number of overall (read+write) accesses
793 system.cpu.dcache.overall_accesses::total 972712320 # number of overall (read+write) accesses
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795 system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
796 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003041 # miss rate for WriteReq accesses
797 system.cpu.dcache.WriteReq_miss_rate::total 0.003041 # miss rate for WriteReq accesses
798 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
799 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
800 system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses
801 system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses
802 system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses
803 system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses
804 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34165.458237 # average ReadReq miss latency
805 system.cpu.dcache.ReadReq_avg_miss_latency::total 34165.458237 # average ReadReq miss latency
806 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46827.311914 # average WriteReq miss latency
807 system.cpu.dcache.WriteReq_avg_miss_latency::total 46827.311914 # average WriteReq miss latency
808 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
809 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
810 system.cpu.dcache.demand_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency
811 system.cpu.dcache.demand_avg_miss_latency::total 37979.274551 # average overall miss latency
812 system.cpu.dcache.overall_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency
813 system.cpu.dcache.overall_avg_miss_latency::total 37979.274551 # average overall miss latency
814 system.cpu.dcache.blocked_cycles::no_mshrs 1535 # number of cycles access was blocked
815 system.cpu.dcache.blocked_cycles::no_targets 741 # number of cycles access was blocked
816 system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked
817 system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
818 system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.425926 # average number of cycles each access was blocked
819 system.cpu.dcache.avg_blocked_cycles::no_targets 8.325843 # average number of cycles each access was blocked
820 system.cpu.dcache.fast_writes 0 # number of fast writes performed
821 system.cpu.dcache.cache_copies 0 # number of cache copies performed
822 system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
823 system.cpu.dcache.writebacks::total 96322 # number of writebacks
824 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488793 # number of ReadReq MSHR hits
825 system.cpu.dcache.ReadReq_mshr_hits::total 488793 # number of ReadReq MSHR hits
826 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765175 # number of WriteReq MSHR hits
827 system.cpu.dcache.WriteReq_mshr_hits::total 765175 # number of WriteReq MSHR hits
828 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
829 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
830 system.cpu.dcache.demand_mshr_hits::cpu.data 1253968 # number of demand (read+write) MSHR hits
831 system.cpu.dcache.demand_mshr_hits::total 1253968 # number of demand (read+write) MSHR hits
832 system.cpu.dcache.overall_mshr_hits::cpu.data 1253968 # number of overall MSHR hits
833 system.cpu.dcache.overall_mshr_hits::total 1253968 # number of overall MSHR hits
834 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464706 # number of ReadReq MSHR misses
835 system.cpu.dcache.ReadReq_mshr_misses::total 1464706 # number of ReadReq MSHR misses
836 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76852 # number of WriteReq MSHR misses
837 system.cpu.dcache.WriteReq_mshr_misses::total 76852 # number of WriteReq MSHR misses
838 system.cpu.dcache.demand_mshr_misses::cpu.data 1541558 # number of demand (read+write) MSHR misses
839 system.cpu.dcache.demand_mshr_misses::total 1541558 # number of demand (read+write) MSHR misses
840 system.cpu.dcache.overall_mshr_misses::cpu.data 1541558 # number of overall MSHR misses
841 system.cpu.dcache.overall_mshr_misses::total 1541558 # number of overall MSHR misses
842 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41088591000 # number of ReadReq MSHR miss cycles
843 system.cpu.dcache.ReadReq_mshr_miss_latency::total 41088591000 # number of ReadReq MSHR miss cycles
844 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3410048000 # number of WriteReq MSHR miss cycles
845 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3410048000 # number of WriteReq MSHR miss cycles
846 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44498639000 # number of demand (read+write) MSHR miss cycles
847 system.cpu.dcache.demand_mshr_miss_latency::total 44498639000 # number of demand (read+write) MSHR miss cycles
848 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44498639000 # number of overall MSHR miss cycles
849 system.cpu.dcache.overall_mshr_miss_latency::total 44498639000 # number of overall MSHR miss cycles
850 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
851 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
852 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
853 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
854 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
855 system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
856 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
857 system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
858 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28052.449434 # average ReadReq mshr miss latency
859 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28052.449434 # average ReadReq mshr miss latency
860 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44371.623380 # average WriteReq mshr miss latency
861 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44371.623380 # average WriteReq mshr miss latency
862 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
863 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
864 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
865 system.cpu.dcache.overall_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
866 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
868 ---------- End Simulation Statistics ----------
projects / gem5.git / blob