2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.640648 # Number of seconds simulated
4 sim_ticks 640648369500 # Number of ticks simulated
5 final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 107808 # Simulator instruction rate (inst/s)
8 host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49890421 # Simulator tick rate (ticks/s)
10 host_mem_usage 251704 # Number of bytes of host memory used
11 host_seconds 12841.11 # Real time elapsed on the host
12 sim_insts 1384370590 # Number of instructions simulated
13 sim_ops 1885325342 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
38 system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
39 system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40 system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41 system.physmem.bytesRead 30399488 # Total number of bytes read from memory
42 system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
43 system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
44 system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
45 system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
46 system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
47 system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis
63 system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
79 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
81 system.physmem.totGap 640648293500 # Total gap between requests
82 system.physmem.readPktSize::0 0 # Categorize read packet sizes
83 system.physmem.readPktSize::1 0 # Categorize read packet sizes
84 system.physmem.readPktSize::2 0 # Categorize read packet sizes
85 system.physmem.readPktSize::3 0 # Categorize read packet sizes
86 system.physmem.readPktSize::4 0 # Categorize read packet sizes
87 system.physmem.readPktSize::5 0 # Categorize read packet sizes
88 system.physmem.readPktSize::6 474992 # Categorize read packet sizes
89 system.physmem.writePktSize::0 0 # Categorize write packet sizes
90 system.physmem.writePktSize::1 0 # Categorize write packet sizes
91 system.physmem.writePktSize::2 0 # Categorize write packet sizes
92 system.physmem.writePktSize::3 0 # Categorize write packet sizes
93 system.physmem.writePktSize::4 0 # Categorize write packet sizes
94 system.physmem.writePktSize::5 0 # Categorize write packet sizes
95 system.physmem.writePktSize::6 66098 # Categorize write packet sizes
96 system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128 system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
160 system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation
219 system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays
220 system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests
221 system.physmem.totBusLat 2374200000 # Total cycles spent in databus access
222 system.physmem.totBankLat 10704210000 # Total cycles spent in bank access
223 system.physmem.avgQLat 3976.96 # Average queueing delay per request
224 system.physmem.avgBankLat 22542.77 # Average bank access latency per request
225 system.physmem.avgBusLat 5000.00 # Average bus latency per request
226 system.physmem.avgMemAccLat 31519.74 # Average memory access latency
227 system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s
228 system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s
229 system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s
230 system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s
231 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
232 system.physmem.busUtil 0.42 # Data bus utilization in percentage
233 system.physmem.avgRdQLen 0.02 # Average read queue length over time
234 system.physmem.avgWrQLen 17.45 # Average write queue length over time
235 system.physmem.readRowHits 318007 # Number of row buffer hits during reads
236 system.physmem.writeRowHits 49644 # Number of row buffer hits during writes
237 system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads
238 system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
239 system.physmem.avgGap 1183995.81 # Average gap between requests
240 system.membus.throughput 54054139 # Throughput (bytes/s)
241 system.membus.trans_dist::ReadReq 408917 # Transaction distribution
242 system.membus.trans_dist::ReadResp 408916 # Transaction distribution
243 system.membus.trans_dist::Writeback 66098 # Transaction distribution
244 system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution
245 system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
246 system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
247 system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
248 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
249 system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
250 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
251 system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
252 system.membus.data_through_bus 34629696 # Total data (bytes)
253 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
254 system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
255 system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
256 system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks)
257 system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
258 system.cpu.branchPred.lookups 451070712 # Number of BP lookups
259 system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted
260 system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect
261 system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups
262 system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits
263 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
264 system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage
265 system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target.
266 system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions.
267 system.cpu.dtb.inst_hits 0 # ITB inst hits
268 system.cpu.dtb.inst_misses 0 # ITB inst misses
269 system.cpu.dtb.read_hits 0 # DTB read hits
270 system.cpu.dtb.read_misses 0 # DTB read misses
271 system.cpu.dtb.write_hits 0 # DTB write hits
272 system.cpu.dtb.write_misses 0 # DTB write misses
273 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
274 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
275 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
276 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
277 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
278 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
279 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
280 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
281 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
282 system.cpu.dtb.read_accesses 0 # DTB read accesses
283 system.cpu.dtb.write_accesses 0 # DTB write accesses
284 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
285 system.cpu.dtb.hits 0 # DTB hits
286 system.cpu.dtb.misses 0 # DTB misses
287 system.cpu.dtb.accesses 0 # DTB accesses
288 system.cpu.itb.inst_hits 0 # ITB inst hits
289 system.cpu.itb.inst_misses 0 # ITB inst misses
290 system.cpu.itb.read_hits 0 # DTB read hits
291 system.cpu.itb.read_misses 0 # DTB read misses
292 system.cpu.itb.write_hits 0 # DTB write hits
293 system.cpu.itb.write_misses 0 # DTB write misses
294 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
295 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
296 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
297 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
298 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
299 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
300 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
301 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
302 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
303 system.cpu.itb.read_accesses 0 # DTB read accesses
304 system.cpu.itb.write_accesses 0 # DTB write accesses
305 system.cpu.itb.inst_accesses 0 # ITB inst accesses
306 system.cpu.itb.hits 0 # DTB hits
307 system.cpu.itb.misses 0 # DTB misses
308 system.cpu.itb.accesses 0 # DTB accesses
309 system.cpu.workload.num_syscalls 1411 # Number of system calls
310 system.cpu.numCycles 1281296740 # number of cpu cycles simulated
311 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
312 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
313 system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss
314 system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed
315 system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered
316 system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken
317 system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked
318 system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing
319 system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked
320 system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
321 system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps
322 system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
323 system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched
324 system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed
325 system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle
343 system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle
344 system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle
345 system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked
346 system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running
347 system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking
348 system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing
349 system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch
350 system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction
351 system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode
352 system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode
353 system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing
354 system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle
355 system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking
356 system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst
357 system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running
358 system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking
359 system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename
360 system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full
361 system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full
362 system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full
363 system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
364 system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
365 system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
366 system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups
367 system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups
368 system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
369 system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
370 system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed
371 system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed
372 system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer
373 system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit.
374 system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit.
375 system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads.
376 system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores.
377 system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec)
378 system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ
379 system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued
380 system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued
381 system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling
382 system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph
383 system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed
384 system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle
401 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
402 system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available
403 system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available
404 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
405 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
406 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
407 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
408 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
409 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
410 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
431 system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available
432 system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available
433 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
434 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
435 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
436 system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued
437 system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued
438 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
439 system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
440 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
441 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
442 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
443 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
444 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued
465 system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued
466 system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued
467 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
468 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
469 system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued
470 system.cpu.iq.rate 1.917842 # Inst issue rate
471 system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested
472 system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst)
473 system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads
474 system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes
475 system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses
476 system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads
477 system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes
478 system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses
479 system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses
480 system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses
481 system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores
482 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
483 system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed
484 system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed
485 system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations
486 system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed
487 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
488 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
489 system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
490 system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked
491 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
492 system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing
493 system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking
494 system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking
495 system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ
496 system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch
497 system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions
498 system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions
499 system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions
500 system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall
501 system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
502 system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations
503 system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly
504 system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly
505 system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute
506 system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions
507 system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed
508 system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute
509 system.cpu.iew.exec_swp 0 # number of swp insts executed
510 system.cpu.iew.exec_nop 12463 # number of nop insts executed
511 system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed
512 system.cpu.iew.exec_branches 324680497 # Number of branches executed
513 system.cpu.iew.exec_stores 426903851 # Number of stores executed
514 system.cpu.iew.exec_rate 1.856653 # Inst execution rate
515 system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit
516 system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back
517 system.cpu.iew.wb_producers 1354756756 # num instructions producing a value
518 system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value
519 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
520 system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle
521 system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back
522 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
523 system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit
524 system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
525 system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted
526 system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle
543 system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
544 system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
545 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
546 system.cpu.commit.refs 908382478 # Number of memory references committed
547 system.cpu.commit.loads 631387181 # Number of loads committed
548 system.cpu.commit.membars 9986 # Number of memory barriers committed
549 system.cpu.commit.branches 298259106 # Number of branches committed
550 system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
551 system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
552 system.cpu.commit.function_calls 41577833 # Number of function calls committed.
553 system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
554 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
555 system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
556 system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
557 system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
558 system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
559 system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
560 system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
561 system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
562 system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
563 system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
564 system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
565 system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
566 system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
567 system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
568 system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
569 system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
570 system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
571 system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
572 system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
573 system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
574 system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
575 system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
576 system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
577 system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
578 system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
579 system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
580 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
581 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
582 system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
583 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
584 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
585 system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
586 system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
587 system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
588 system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
589 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
590 system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
591 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
592 system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
593 system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
594 system.cpu.icache.tags.replacements 22329 # number of replacements
595 system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
596 system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
597 system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
598 system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
599 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
600 system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
601 system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
602 system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
603 system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
604 system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
605 system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
606 system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits
607 system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits
608 system.cpu.icache.overall_hits::total 345973619 # number of overall hits
609 system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses
610 system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses
611 system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses
612 system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses
613 system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses
614 system.cpu.icache.overall_misses::total 30537 # number of overall misses
615 system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles
616 system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles
617 system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles
618 system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles
619 system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles
620 system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles
621 system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses)
622 system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses)
623 system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses
624 system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses
625 system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses
626 system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses
627 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
628 system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
629 system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
630 system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
631 system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
632 system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
633 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency
634 system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency
635 system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
636 system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency
637 system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
638 system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency
639 system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked
640 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
641 system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
642 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
643 system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked
644 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
645 system.cpu.icache.fast_writes 0 # number of fast writes performed
646 system.cpu.icache.cache_copies 0 # number of cache copies performed
647 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits
648 system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits
649 system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits
650 system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits
651 system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits
652 system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits
653 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses
654 system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses
655 system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses
656 system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses
657 system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses
658 system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses
659 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles
660 system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles
661 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles
662 system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles
663 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles
664 system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles
665 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
666 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
667 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
668 system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
669 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
670 system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
671 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency
672 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency
673 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
674 system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
675 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
676 system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
677 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
678 system.cpu.l2cache.tags.replacements 442208 # number of replacements
679 system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
680 system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
681 system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
682 system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
683 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
684 system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
685 system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
686 system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
687 system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy
688 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy
689 system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy
690 system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
691 system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits
692 system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits
693 system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits
694 system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits
695 system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits
696 system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
697 system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
698 system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits
699 system.cpu.l2cache.ReadExReq_hits::total 6444 # number of ReadExReq hits
700 system.cpu.l2cache.demand_hits::cpu.inst 21578 # number of demand (read+write) hits
701 system.cpu.l2cache.demand_hits::cpu.data 1064316 # number of demand (read+write) hits
702 system.cpu.l2cache.demand_hits::total 1085894 # number of demand (read+write) hits
703 system.cpu.l2cache.overall_hits::cpu.inst 21578 # number of overall hits
704 system.cpu.l2cache.overall_hits::cpu.data 1064316 # number of overall hits
705 system.cpu.l2cache.overall_hits::total 1085894 # number of overall hits
706 system.cpu.l2cache.ReadReq_misses::cpu.inst 2434 # number of ReadReq misses
707 system.cpu.l2cache.ReadReq_misses::cpu.data 406511 # number of ReadReq misses
708 system.cpu.l2cache.ReadReq_misses::total 408945 # number of ReadReq misses
709 system.cpu.l2cache.UpgradeReq_misses::cpu.data 4361 # number of UpgradeReq misses
710 system.cpu.l2cache.UpgradeReq_misses::total 4361 # number of UpgradeReq misses
711 system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
712 system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
713 system.cpu.l2cache.demand_misses::cpu.inst 2434 # number of demand (read+write) misses
714 system.cpu.l2cache.demand_misses::cpu.data 472586 # number of demand (read+write) misses
715 system.cpu.l2cache.demand_misses::total 475020 # number of demand (read+write) misses
716 system.cpu.l2cache.overall_misses::cpu.inst 2434 # number of overall misses
717 system.cpu.l2cache.overall_misses::cpu.data 472586 # number of overall misses
718 system.cpu.l2cache.overall_misses::total 475020 # number of overall misses
719 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173732500 # number of ReadReq miss cycles
720 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30711118250 # number of ReadReq miss cycles
721 system.cpu.l2cache.ReadReq_miss_latency::total 30884850750 # number of ReadReq miss cycles
722 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4593677250 # number of ReadExReq miss cycles
723 system.cpu.l2cache.ReadExReq_miss_latency::total 4593677250 # number of ReadExReq miss cycles
724 system.cpu.l2cache.demand_miss_latency::cpu.inst 173732500 # number of demand (read+write) miss cycles
725 system.cpu.l2cache.demand_miss_latency::cpu.data 35304795500 # number of demand (read+write) miss cycles
726 system.cpu.l2cache.demand_miss_latency::total 35478528000 # number of demand (read+write) miss cycles
727 system.cpu.l2cache.overall_miss_latency::cpu.inst 173732500 # number of overall miss cycles
728 system.cpu.l2cache.overall_miss_latency::cpu.data 35304795500 # number of overall miss cycles
729 system.cpu.l2cache.overall_miss_latency::total 35478528000 # number of overall miss cycles
730 system.cpu.l2cache.ReadReq_accesses::cpu.inst 24012 # number of ReadReq accesses(hits+misses)
731 system.cpu.l2cache.ReadReq_accesses::cpu.data 1464383 # number of ReadReq accesses(hits+misses)
732 system.cpu.l2cache.ReadReq_accesses::total 1488395 # number of ReadReq accesses(hits+misses)
733 system.cpu.l2cache.Writeback_accesses::writebacks 96304 # number of Writeback accesses(hits+misses)
734 system.cpu.l2cache.Writeback_accesses::total 96304 # number of Writeback accesses(hits+misses)
735 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4364 # number of UpgradeReq accesses(hits+misses)
736 system.cpu.l2cache.UpgradeReq_accesses::total 4364 # number of UpgradeReq accesses(hits+misses)
737 system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses)
738 system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
739 system.cpu.l2cache.demand_accesses::cpu.inst 24012 # number of demand (read+write) accesses
740 system.cpu.l2cache.demand_accesses::cpu.data 1536902 # number of demand (read+write) accesses
741 system.cpu.l2cache.demand_accesses::total 1560914 # number of demand (read+write) accesses
742 system.cpu.l2cache.overall_accesses::cpu.inst 24012 # number of overall (read+write) accesses
743 system.cpu.l2cache.overall_accesses::cpu.data 1536902 # number of overall (read+write) accesses
744 system.cpu.l2cache.overall_accesses::total 1560914 # number of overall (read+write) accesses
745 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101366 # miss rate for ReadReq accesses
746 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277599 # miss rate for ReadReq accesses
747 system.cpu.l2cache.ReadReq_miss_rate::total 0.274756 # miss rate for ReadReq accesses
748 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999313 # miss rate for UpgradeReq accesses
749 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999313 # miss rate for UpgradeReq accesses
750 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911141 # miss rate for ReadExReq accesses
751 system.cpu.l2cache.ReadExReq_miss_rate::total 0.911141 # miss rate for ReadExReq accesses
752 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101366 # miss rate for demand accesses
753 system.cpu.l2cache.demand_miss_rate::cpu.data 0.307493 # miss rate for demand accesses
754 system.cpu.l2cache.demand_miss_rate::total 0.304322 # miss rate for demand accesses
755 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101366 # miss rate for overall accesses
756 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307493 # miss rate for overall accesses
757 system.cpu.l2cache.overall_miss_rate::total 0.304322 # miss rate for overall accesses
758 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366 # average ReadReq miss latency
759 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045 # average ReadReq miss latency
760 system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455 # average ReadReq miss latency
761 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991 # average ReadExReq miss latency
762 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991 # average ReadExReq miss latency
763 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
764 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
765 system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116 # average overall miss latency
766 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
767 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
768 system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency
769 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
770 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
771 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
772 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
773 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
774 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
775 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
776 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
777 system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
778 system.cpu.l2cache.writebacks::total 66098 # number of writebacks
779 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
780 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
781 system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
782 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
783 system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
784 system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
785 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
786 system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
787 system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
788 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2432 # number of ReadReq MSHR misses
789 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406485 # number of ReadReq MSHR misses
790 system.cpu.l2cache.ReadReq_mshr_misses::total 408917 # number of ReadReq MSHR misses
791 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4361 # number of UpgradeReq MSHR misses
792 system.cpu.l2cache.UpgradeReq_mshr_misses::total 4361 # number of UpgradeReq MSHR misses
793 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
794 system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
795 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2432 # number of demand (read+write) MSHR misses
796 system.cpu.l2cache.demand_mshr_misses::cpu.data 472560 # number of demand (read+write) MSHR misses
797 system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses
798 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2432 # number of overall MSHR misses
799 system.cpu.l2cache.overall_mshr_misses::cpu.data 472560 # number of overall MSHR misses
800 system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses
801 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142964000 # number of ReadReq MSHR miss cycles
802 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25574268250 # number of ReadReq MSHR miss cycles
803 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25717232250 # number of ReadReq MSHR miss cycles
804 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43614361 # number of UpgradeReq MSHR miss cycles
805 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43614361 # number of UpgradeReq MSHR miss cycles
806 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3760538250 # number of ReadExReq MSHR miss cycles
807 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3760538250 # number of ReadExReq MSHR miss cycles
808 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142964000 # number of demand (read+write) MSHR miss cycles
809 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29334806500 # number of demand (read+write) MSHR miss cycles
810 system.cpu.l2cache.demand_mshr_miss_latency::total 29477770500 # number of demand (read+write) MSHR miss cycles
811 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142964000 # number of overall MSHR miss cycles
812 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29334806500 # number of overall MSHR miss cycles
813 system.cpu.l2cache.overall_mshr_miss_latency::total 29477770500 # number of overall MSHR miss cycles
814 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for ReadReq accesses
815 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277581 # mshr miss rate for ReadReq accesses
816 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274737 # mshr miss rate for ReadReq accesses
817 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999313 # mshr miss rate for UpgradeReq accesses
818 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999313 # mshr miss rate for UpgradeReq accesses
819 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911141 # mshr miss rate for ReadExReq accesses
820 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911141 # mshr miss rate for ReadExReq accesses
821 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for demand accesses
822 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for demand accesses
823 system.cpu.l2cache.demand_mshr_miss_rate::total 0.304304 # mshr miss rate for demand accesses
824 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for overall accesses
825 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for overall accesses
826 system.cpu.l2cache.overall_mshr_miss_rate::total 0.304304 # mshr miss rate for overall accesses
827 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474 # average ReadReq mshr miss latency
828 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639 # average ReadReq mshr miss latency
829 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197 # average ReadReq mshr miss latency
830 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
831 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
832 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency
833 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency
834 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
835 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
836 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
837 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency
838 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
839 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
840 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
841 system.cpu.dcache.tags.replacements 1532805 # number of replacements
842 system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use
843 system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks.
844 system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks.
845 system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks.
846 system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit.
847 system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor
848 system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy
849 system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy
850 system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits
851 system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits
852 system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits
853 system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits
854 system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
855 system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
856 system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
857 system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
858 system.cpu.dcache.demand_hits::cpu.data 972883701 # number of demand (read+write) hits
859 system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits
860 system.cpu.dcache.overall_hits::cpu.data 972883701 # number of overall hits
861 system.cpu.dcache.overall_hits::total 972883701 # number of overall hits
862 system.cpu.dcache.ReadReq_misses::cpu.data 1953888 # number of ReadReq misses
863 system.cpu.dcache.ReadReq_misses::total 1953888 # number of ReadReq misses
864 system.cpu.dcache.WriteReq_misses::cpu.data 842462 # number of WriteReq misses
865 system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses
866 system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
867 system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
868 system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses
869 system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses
870 system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses
871 system.cpu.dcache.overall_misses::total 2796350 # number of overall misses
872 system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles
873 system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles
874 system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles
875 system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles
876 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles
877 system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles
878 system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles
879 system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles
880 system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles
881 system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles
882 system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses)
883 system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses)
884 system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
885 system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
886 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
887 system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
888 system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
889 system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
890 system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses
891 system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses
892 system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses
893 system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses
894 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses
895 system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses
896 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses
897 system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses
898 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
899 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
900 system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
901 system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
902 system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
903 system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
904 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency
905 system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency
906 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency
907 system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency
908 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency
909 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency
910 system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
911 system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency
912 system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
913 system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency
914 system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked
915 system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
916 system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked
917 system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
918 system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked
919 system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked
920 system.cpu.dcache.fast_writes 0 # number of fast writes performed
921 system.cpu.dcache.cache_copies 0 # number of cache copies performed
922 system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks
923 system.cpu.dcache.writebacks::total 96304 # number of writebacks
924 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits
925 system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits
926 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits
927 system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits
928 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
929 system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
930 system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits
931 system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits
932 system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits
933 system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits
934 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses
935 system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses
936 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses
937 system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses
938 system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses
939 system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses
940 system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses
941 system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses
942 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles
943 system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles
944 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles
945 system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles
946 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles
947 system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles
948 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles
949 system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles
950 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses
951 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses
952 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
953 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
954 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses
955 system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses
956 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses
957 system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses
958 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency
959 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency
960 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency
961 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency
962 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
963 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
964 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
965 system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
966 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
968 ---------- End Simulation Statistics ----------
projects / gem5.git / blob