2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.339013 # Number of seconds simulated
4 sim_ticks 339012932000 # Number of ticks simulated
5 final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 218277 # Simulator instruction rate (inst/s)
8 host_op_rate 268728 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 115505586 # Simulator tick rate (ticks/s)
10 host_mem_usage 277356 # Number of bytes of host memory used
11 host_seconds 2935.04 # Real time elapsed on the host
12 sim_insts 640649299 # Number of instructions simulated
13 sim_ops 788724958 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory
20 system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory
21 system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory
22 system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory
24 system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory
25 system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory
28 system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory
29 system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory
30 system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory
31 system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s)
39 system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.readReqs 957477 # Number of read requests accepted
45 system.physmem.writeReqs 66339 # Number of write requests accepted
46 system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue
47 system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue
48 system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM
49 system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue
50 system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM
51 system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side
52 system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side
53 system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue
54 system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one
55 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56 system.physmem.perBankRdBursts::0 19910 # Per bank write bursts
57 system.physmem.perBankRdBursts::1 19533 # Per bank write bursts
58 system.physmem.perBankRdBursts::2 657271 # Per bank write bursts
59 system.physmem.perBankRdBursts::3 20982 # Per bank write bursts
60 system.physmem.perBankRdBursts::4 19710 # Per bank write bursts
61 system.physmem.perBankRdBursts::5 21143 # Per bank write bursts
62 system.physmem.perBankRdBursts::6 19634 # Per bank write bursts
63 system.physmem.perBankRdBursts::7 20055 # Per bank write bursts
64 system.physmem.perBankRdBursts::8 19495 # Per bank write bursts
65 system.physmem.perBankRdBursts::9 20079 # Per bank write bursts
66 system.physmem.perBankRdBursts::10 19428 # Per bank write bursts
67 system.physmem.perBankRdBursts::11 19728 # Per bank write bursts
68 system.physmem.perBankRdBursts::12 19649 # Per bank write bursts
69 system.physmem.perBankRdBursts::13 21208 # Per bank write bursts
70 system.physmem.perBankRdBursts::14 19490 # Per bank write bursts
71 system.physmem.perBankRdBursts::15 19853 # Per bank write bursts
72 system.physmem.perBankWrBursts::0 4286 # Per bank write bursts
73 system.physmem.perBankWrBursts::1 4105 # Per bank write bursts
74 system.physmem.perBankWrBursts::2 4145 # Per bank write bursts
75 system.physmem.perBankWrBursts::3 4153 # Per bank write bursts
76 system.physmem.perBankWrBursts::4 4249 # Per bank write bursts
77 system.physmem.perBankWrBursts::5 4230 # Per bank write bursts
78 system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
79 system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
80 system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
81 system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
82 system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
83 system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
84 system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
85 system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
86 system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
87 system.physmem.perBankWrBursts::15 4149 # Per bank write bursts
88 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
90 system.physmem.totGap 339012921500 # Total gap between requests
91 system.physmem.readPktSize::0 0 # Read request sizes (log2)
92 system.physmem.readPktSize::1 0 # Read request sizes (log2)
93 system.physmem.readPktSize::2 0 # Read request sizes (log2)
94 system.physmem.readPktSize::3 0 # Read request sizes (log2)
95 system.physmem.readPktSize::4 0 # Read request sizes (log2)
96 system.physmem.readPktSize::5 0 # Read request sizes (log2)
97 system.physmem.readPktSize::6 957477 # Read request sizes (log2)
98 system.physmem.writePktSize::0 0 # Write request sizes (log2)
99 system.physmem.writePktSize::1 0 # Write request sizes (log2)
100 system.physmem.writePktSize::2 0 # Write request sizes (log2)
101 system.physmem.writePktSize::3 0 # Write request sizes (log2)
102 system.physmem.writePktSize::4 0 # Write request sizes (log2)
103 system.physmem.writePktSize::5 0 # Write request sizes (log2)
104 system.physmem.writePktSize::6 66339 # Write request sizes (log2)
105 system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
137 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
201 system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation
215 system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes
231 system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads
257 system.physmem.totQLat 27473404757 # Total ticks spent queuing
258 system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM
259 system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers
260 system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst
261 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
262 system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst
263 system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s
264 system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s
265 system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s
266 system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s
267 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
268 system.physmem.busUtil 1.51 # Data bus utilization in percentage
269 system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads
270 system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes
271 system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
272 system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing
273 system.physmem.readRowHits 805066 # Number of row buffer hits during reads
274 system.physmem.writeRowHits 23137 # Number of row buffer hits during writes
275 system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads
276 system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes
277 system.physmem.avgGap 331126.81 # Average gap between requests
278 system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined
279 system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ)
280 system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ)
281 system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ)
282 system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ)
283 system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ)
284 system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ)
285 system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ)
286 system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ)
287 system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ)
288 system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ)
289 system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ)
290 system.physmem_0.averagePower 558.908824 # Core power per rank (mW)
291 system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank
292 system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states
293 system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states
294 system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states
295 system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states
296 system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states
297 system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states
298 system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ)
299 system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ)
300 system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ)
301 system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ)
302 system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ)
303 system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ)
304 system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ)
305 system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ)
306 system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ)
307 system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ)
308 system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ)
309 system.physmem_1.averagePower 480.431501 # Core power per rank (mW)
310 system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank
311 system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states
312 system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states
313 system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states
314 system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states
315 system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states
316 system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states
317 system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
318 system.cpu.branchPred.lookups 174656775 # Number of BP lookups
319 system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted
320 system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect
321 system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups
322 system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits
323 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
324 system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage
325 system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target.
326 system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions.
327 system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups.
328 system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits.
329 system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses.
330 system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches.
331 system.cpu_clk_domain.clock 500 # Clock period in ticks
332 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
333 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
334 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
335 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
336 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
337 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
338 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
339 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
340 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
341 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
342 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
343 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
344 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
345 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
346 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
347 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
348 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
349 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
350 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
351 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
352 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
353 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
354 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
355 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
356 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
357 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
358 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
359 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
360 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
361 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
362 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
363 system.cpu.dtb.walker.walks 0 # Table walker walks requested
364 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
365 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
366 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
367 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
368 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
369 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
370 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
371 system.cpu.dtb.inst_hits 0 # ITB inst hits
372 system.cpu.dtb.inst_misses 0 # ITB inst misses
373 system.cpu.dtb.read_hits 0 # DTB read hits
374 system.cpu.dtb.read_misses 0 # DTB read misses
375 system.cpu.dtb.write_hits 0 # DTB write hits
376 system.cpu.dtb.write_misses 0 # DTB write misses
377 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
378 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
379 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
380 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
381 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
382 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
383 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
384 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
385 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
386 system.cpu.dtb.read_accesses 0 # DTB read accesses
387 system.cpu.dtb.write_accesses 0 # DTB write accesses
388 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
389 system.cpu.dtb.hits 0 # DTB hits
390 system.cpu.dtb.misses 0 # DTB misses
391 system.cpu.dtb.accesses 0 # DTB accesses
392 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
393 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
394 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
395 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
396 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
397 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
398 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
399 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
400 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
401 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
402 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
403 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
404 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
405 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
406 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
407 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
408 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
409 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
410 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
411 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
412 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
413 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
414 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
415 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
416 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
417 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
418 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
419 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
420 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
421 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
422 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
423 system.cpu.itb.walker.walks 0 # Table walker walks requested
424 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
425 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
426 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
427 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
428 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
429 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
430 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
431 system.cpu.itb.inst_hits 0 # ITB inst hits
432 system.cpu.itb.inst_misses 0 # ITB inst misses
433 system.cpu.itb.read_hits 0 # DTB read hits
434 system.cpu.itb.read_misses 0 # DTB read misses
435 system.cpu.itb.write_hits 0 # DTB write hits
436 system.cpu.itb.write_misses 0 # DTB write misses
437 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
438 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
439 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
440 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
441 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
442 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
443 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
444 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
445 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
446 system.cpu.itb.read_accesses 0 # DTB read accesses
447 system.cpu.itb.write_accesses 0 # DTB write accesses
448 system.cpu.itb.inst_accesses 0 # ITB inst accesses
449 system.cpu.itb.hits 0 # DTB hits
450 system.cpu.itb.misses 0 # DTB misses
451 system.cpu.itb.accesses 0 # DTB accesses
452 system.cpu.workload.num_syscalls 673 # Number of system calls
453 system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states
454 system.cpu.numCycles 678025865 # number of cpu cycles simulated
455 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
456 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
457 system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss
458 system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed
459 system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered
460 system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken
461 system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked
462 system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing
463 system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
464 system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps
465 system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR
466 system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched
467 system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed
468 system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total)
469 system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total)
470 system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total)
471 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
472 system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total)
473 system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total)
474 system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total)
475 system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total)
476 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
477 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
478 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
479 system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total)
480 system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle
481 system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle
482 system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle
483 system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked
484 system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running
485 system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking
486 system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing
487 system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch
488 system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction
489 system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode
490 system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode
491 system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing
492 system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle
493 system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking
494 system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst
495 system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running
496 system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking
497 system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename
498 system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename
499 system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full
500 system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full
501 system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full
502 system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full
503 system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed
504 system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made
505 system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups
506 system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups
507 system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
508 system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing
509 system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed
510 system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed
511 system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer
512 system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit.
513 system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit.
514 system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads.
515 system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores.
516 system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec)
517 system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ
518 system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued
519 system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued
520 system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling
521 system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph
522 system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed
523 system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle
524 system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle
525 system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle
526 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
527 system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle
528 system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle
529 system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle
530 system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle
531 system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle
532 system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle
533 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
534 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
535 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
536 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
537 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
538 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
539 system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle
540 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
541 system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available
542 system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available
543 system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available
544 system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available
545 system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available
546 system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available
547 system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available
548 system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available
549 system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available
550 system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available
551 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available
552 system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available
553 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available
554 system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available
555 system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available
556 system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available
557 system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available
558 system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available
559 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available
560 system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available
561 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available
562 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available
563 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available
564 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available
565 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available
566 system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available
567 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available
568 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available
569 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available
570 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available
571 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available
572 system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available
573 system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available
574 system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available
575 system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available
576 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
577 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
578 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
579 system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued
580 system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued
581 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued
582 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued
583 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued
584 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued
585 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued
586 system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued
587 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued
588 system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued
589 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued
590 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued
591 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued
592 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued
593 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued
594 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued
595 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued
596 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued
597 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued
598 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued
599 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued
600 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued
601 system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued
602 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
603 system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued
604 system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued
605 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
606 system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued
607 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued
608 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued
609 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued
610 system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued
611 system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued
612 system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued
613 system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued
614 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
615 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
616 system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued
617 system.cpu.iq.rate 1.268433 # Inst issue rate
618 system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested
619 system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst)
620 system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads
621 system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes
622 system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses
623 system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads
624 system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes
625 system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses
626 system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses
627 system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses
628 system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores
629 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
630 system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed
631 system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed
632 system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations
633 system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed
634 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
635 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
636 system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled
637 system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked
638 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
639 system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing
640 system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking
641 system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking
642 system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ
643 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
644 system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions
645 system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions
646 system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions
647 system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall
648 system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall
649 system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations
650 system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly
651 system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly
652 system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute
653 system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions
654 system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed
655 system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute
656 system.cpu.iew.exec_swp 0 # number of swp insts executed
657 system.cpu.iew.exec_nop 9874 # number of nop insts executed
658 system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed
659 system.cpu.iew.exec_branches 143381564 # Number of branches executed
660 system.cpu.iew.exec_stores 152690015 # Number of stores executed
661 system.cpu.iew.exec_rate 1.253898 # Inst execution rate
662 system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit
663 system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back
664 system.cpu.iew.wb_producers 487342605 # num instructions producing a value
665 system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value
666 system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle
667 system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back
668 system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit
669 system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
670 system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted
671 system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle
672 system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle
673 system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle
674 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
675 system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle
676 system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle
677 system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle
678 system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle
679 system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle
680 system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle
681 system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle
682 system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle
683 system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle
684 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
685 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
686 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
687 system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle
688 system.cpu.commit.committedInsts 640654411 # Number of instructions committed
689 system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
690 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
691 system.cpu.commit.refs 381221434 # Number of memory references committed
692 system.cpu.commit.loads 252240938 # Number of loads committed
693 system.cpu.commit.membars 5740 # Number of memory barriers committed
694 system.cpu.commit.branches 137364860 # Number of branches committed
695 system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
696 system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
697 system.cpu.commit.function_calls 19275340 # Number of function calls committed.
698 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
699 system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
700 system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
701 system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
702 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
703 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
704 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
705 system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
706 system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction
707 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
708 system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction
709 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
710 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
711 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
712 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
713 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
714 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
715 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
716 system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
717 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
718 system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
719 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
720 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
721 system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
722 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
723 system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
724 system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
725 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
726 system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
727 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
728 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
729 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
730 system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction
731 system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction
732 system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction
733 system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction
734 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
735 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
736 system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
737 system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached
738 system.cpu.rob.rob_reads 1524914900 # The number of ROB reads
739 system.cpu.rob.rob_writes 1798382781 # The number of ROB writes
740 system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
741 system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling
742 system.cpu.committedInsts 640649299 # Number of Instructions Simulated
743 system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
744 system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction
745 system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads
746 system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle
747 system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads
748 system.cpu.int_regfile_reads 868463326 # number of integer regfile reads
749 system.cpu.int_regfile_writes 500698648 # number of integer regfile writes
750 system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads
751 system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes
752 system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads
753 system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes
754 system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads
755 system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
756 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
757 system.cpu.dcache.tags.replacements 2756453 # number of replacements
758 system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use
759 system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks.
760 system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks.
761 system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks.
762 system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit.
763 system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor
764 system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy
765 system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy
766 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
767 system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
768 system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
769 system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id
770 system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
771 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
772 system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses
773 system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses
774 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
775 system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits
776 system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits
777 system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits
778 system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits
779 system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
780 system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
781 system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
782 system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
783 system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
784 system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
785 system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits
786 system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits
787 system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits
788 system.cpu.dcache.overall_hits::total 371037940 # number of overall hits
789 system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses
790 system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses
791 system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses
792 system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses
793 system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
794 system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
795 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
796 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
797 system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses
798 system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses
799 system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses
800 system.cpu.dcache.overall_misses::total 3446044 # number of overall misses
801 system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles
802 system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles
803 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles
804 system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles
805 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles
806 system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles
807 system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles
808 system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles
809 system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles
810 system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles
811 system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses)
812 system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses)
813 system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
814 system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
815 system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses)
816 system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses)
817 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses)
818 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses)
819 system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
820 system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
821 system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses
822 system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses
823 system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses
824 system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses
825 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses
826 system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses
827 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses
828 system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses
829 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses
830 system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses
831 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses
832 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses
833 system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses
834 system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses
835 system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses
836 system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses
837 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency
838 system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency
839 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency
840 system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency
841 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency
842 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency
843 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency
844 system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency
845 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency
846 system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency
847 system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked
848 system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked
849 system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
850 system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked
851 system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
852 system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked
853 system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks
854 system.cpu.dcache.writebacks::total 2756453 # number of writebacks
855 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits
856 system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits
857 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits
858 system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits
859 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
860 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
861 system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits
862 system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits
863 system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits
864 system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits
865 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses
866 system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses
867 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses
868 system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses
869 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses
870 system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses
871 system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses
872 system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses
873 system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses
874 system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses
875 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles
876 system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles
877 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles
878 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles
879 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles
880 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles
881 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles
882 system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles
883 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles
884 system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles
885 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses
886 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses
887 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses
888 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses
889 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses
890 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses
891 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses
892 system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses
893 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses
894 system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses
895 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency
896 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency
897 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency
898 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency
899 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency
900 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency
901 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency
902 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency
903 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency
904 system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency
905 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
906 system.cpu.icache.tags.replacements 1979522 # number of replacements
907 system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use
908 system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks.
909 system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks.
910 system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks.
911 system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit.
912 system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor
913 system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy
914 system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy
915 system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
916 system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
917 system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
918 system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
919 system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
920 system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id
921 system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
922 system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses
923 system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses
924 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
925 system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits
926 system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits
927 system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits
928 system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits
929 system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits
930 system.cpu.icache.overall_hits::total 245757684 # number of overall hits
931 system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses
932 system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses
933 system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses
934 system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses
935 system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses
936 system.cpu.icache.overall_misses::total 1983224 # number of overall misses
937 system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles
938 system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles
939 system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles
940 system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles
941 system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles
942 system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles
943 system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses)
944 system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses)
945 system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses
946 system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses
947 system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses
948 system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses
949 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses
950 system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses
951 system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses
952 system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses
953 system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses
954 system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses
955 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency
956 system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency
957 system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency
958 system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency
959 system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency
960 system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency
961 system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked
962 system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked
963 system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked
964 system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
965 system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked
966 system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked
967 system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks
968 system.cpu.icache.writebacks::total 1979522 # number of writebacks
969 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits
970 system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits
971 system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits
972 system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits
973 system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits
974 system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits
975 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses
976 system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses
977 system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses
978 system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses
979 system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses
980 system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses
981 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles
982 system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles
983 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles
984 system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles
985 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles
986 system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles
987 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses
988 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses
989 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses
990 system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses
991 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses
992 system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses
993 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency
994 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency
995 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency
996 system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency
997 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency
998 system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency
999 system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
1000 system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued
1001 system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified
1002 system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue
1003 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1004 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1005 system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing
1006 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
1007 system.cpu.l2cache.tags.replacements 297323 # number of replacements
1008 system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use
1009 system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks.
1010 system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks.
1011 system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks.
1012 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1013 system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor
1014 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor
1015 system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy
1016 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy
1017 system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy
1018 system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id
1019 system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id
1020 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
1021 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id
1022 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id
1023 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id
1024 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
1025 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
1026 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id
1027 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id
1028 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id
1029 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id
1030 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id
1031 system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses
1032 system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses
1033 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
1034 system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits
1035 system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits
1036 system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits
1037 system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits
1038 system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits
1039 system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits
1040 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # number of ReadCleanReq hits
1041 system.cpu.l2cache.ReadCleanReq_hits::total 1975820 # number of ReadCleanReq hits
1042 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285803 # number of ReadSharedReq hits
1043 system.cpu.l2cache.ReadSharedReq_hits::total 1285803 # number of ReadSharedReq hits
1044 system.cpu.l2cache.demand_hits::cpu.inst 1975820 # number of demand (read+write) hits
1045 system.cpu.l2cache.demand_hits::cpu.data 2004463 # number of demand (read+write) hits
1046 system.cpu.l2cache.demand_hits::total 3980283 # number of demand (read+write) hits
1047 system.cpu.l2cache.overall_hits::cpu.inst 1975820 # number of overall hits
1048 system.cpu.l2cache.overall_hits::cpu.data 2004463 # number of overall hits
1049 system.cpu.l2cache.overall_hits::total 3980283 # number of overall hits
1050 system.cpu.l2cache.UpgradeReq_misses::cpu.data 190 # number of UpgradeReq misses
1051 system.cpu.l2cache.UpgradeReq_misses::total 190 # number of UpgradeReq misses
1052 system.cpu.l2cache.ReadExReq_misses::cpu.data 2186 # number of ReadExReq misses
1053 system.cpu.l2cache.ReadExReq_misses::total 2186 # number of ReadExReq misses
1054 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses
1055 system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses
1056 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses
1057 system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses
1058 system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses
1059 system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses
1060 system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses
1061 system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses
1062 system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses
1063 system.cpu.l2cache.overall_misses::total 756717 # number of overall misses
1064 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles
1065 system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles
1066 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles
1067 system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles
1068 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles
1069 system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles
1070 system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles
1071 system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles
1072 system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles
1073 system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles
1074 system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles
1075 system.cpu.l2cache.overall_miss_latency::total 64352827500 # number of overall miss cycles
1076 system.cpu.l2cache.WritebackDirty_accesses::writebacks 735952 # number of WritebackDirty accesses(hits+misses)
1077 system.cpu.l2cache.WritebackDirty_accesses::total 735952 # number of WritebackDirty accesses(hits+misses)
1078 system.cpu.l2cache.WritebackClean_accesses::writebacks 3357075 # number of WritebackClean accesses(hits+misses)
1079 system.cpu.l2cache.WritebackClean_accesses::total 3357075 # number of WritebackClean accesses(hits+misses)
1080 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190 # number of UpgradeReq accesses(hits+misses)
1081 system.cpu.l2cache.UpgradeReq_accesses::total 190 # number of UpgradeReq accesses(hits+misses)
1082 system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses)
1083 system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses)
1084 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses)
1085 system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses)
1086 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses)
1087 system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses)
1088 system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses
1089 system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses
1090 system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses
1091 system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses
1092 system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses
1093 system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses
1094 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1095 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1096 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses
1097 system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses
1098 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses
1099 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses
1100 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses
1101 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses
1102 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses
1103 system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses
1104 system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses
1105 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses
1106 system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses
1107 system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses
1108 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency
1109 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency
1110 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency
1111 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency
1112 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency
1113 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency
1114 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency
1115 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency
1116 system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency
1117 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency
1118 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency
1119 system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency
1120 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1121 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1122 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1123 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1124 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1125 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1126 system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference
1127 system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks
1128 system.cpu.l2cache.writebacks::total 66339 # number of writebacks
1129 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 799 # number of ReadExReq MSHR hits
1130 system.cpu.l2cache.ReadExReq_mshr_hits::total 799 # number of ReadExReq MSHR hits
1131 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1132 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1133 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1026 # number of ReadSharedReq MSHR hits
1134 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1026 # number of ReadSharedReq MSHR hits
1135 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1136 system.cpu.l2cache.demand_mshr_hits::cpu.data 1825 # number of demand (read+write) MSHR hits
1137 system.cpu.l2cache.demand_mshr_hits::total 1826 # number of demand (read+write) MSHR hits
1138 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1139 system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits
1140 system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits
1141 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses
1142 system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses
1143 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses
1144 system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses
1145 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses
1146 system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses
1147 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses
1148 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses
1149 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses
1150 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses
1151 system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses
1152 system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses
1153 system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses
1154 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses
1155 system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses
1156 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses
1157 system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses
1158 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles
1159 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles
1160 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles
1161 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles
1162 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles
1163 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles
1164 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles
1165 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles
1166 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles
1167 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles
1168 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles
1169 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles
1170 system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles
1171 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles
1172 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles
1173 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles
1174 system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles
1175 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1176 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1177 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1178 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1179 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses
1180 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses
1181 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses
1182 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses
1183 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses
1184 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses
1185 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses
1186 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses
1187 system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses
1188 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses
1189 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses
1190 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1191 system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses
1192 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency
1193 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency
1194 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency
1195 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency
1196 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency
1197 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency
1198 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency
1199 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency
1200 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency
1201 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency
1202 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency
1203 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency
1204 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency
1205 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency
1206 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency
1207 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency
1208 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency
1209 system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter.
1210 system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1211 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1212 system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter.
1213 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1214 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1215 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
1216 system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution
1217 system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution
1218 system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution
1219 system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution
1220 system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution
1221 system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution
1222 system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution
1223 system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution
1224 system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution
1225 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution
1226 system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution
1227 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes)
1228 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes)
1229 system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes)
1230 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes)
1231 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes)
1232 system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes)
1233 system.cpu.toL2Bus.snoops 552812 # Total snoops (count)
1234 system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes)
1235 system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram
1236 system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram
1237 system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram
1238 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1239 system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram
1240 system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram
1241 system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1242 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1243 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1244 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1245 system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram
1246 system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks)
1247 system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
1248 system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks)
1249 system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
1250 system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks)
1251 system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
1252 system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter.
1253 system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1254 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1255 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1256 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1257 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1258 system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states
1259 system.membus.trans_dist::ReadResp 956088 # Transaction distribution
1260 system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution
1261 system.membus.trans_dist::CleanEvict 230984 # Transaction distribution
1262 system.membus.trans_dist::UpgradeReq 190 # Transaction distribution
1263 system.membus.trans_dist::ReadExReq 1387 # Transaction distribution
1264 system.membus.trans_dist::ReadExResp 1387 # Transaction distribution
1265 system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution
1266 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes)
1267 system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes)
1268 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes)
1269 system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes)
1270 system.membus.snoops 0 # Total snoops (count)
1271 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1272 system.membus.snoop_fanout::samples 957667 # Request fanout histogram
1273 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1274 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1275 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1276 system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram
1277 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1278 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1279 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1280 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1281 system.membus.snoop_fanout::total 957667 # Request fanout histogram
1282 system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks)
1283 system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
1284 system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks)
1285 system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
1287 ---------- End Simulation Statistics ----------
projects / gem5.git / blob