2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.635788 # Number of seconds simulated
4 sim_ticks 635788224000 # Number of ticks simulated
5 final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 107590 # Simulator instruction rate (inst/s)
8 host_op_rate 146523 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 49411882 # Simulator tick rate (ticks/s)
10 host_mem_usage 254872 # Number of bytes of host memory used
11 host_seconds 12867.11 # Real time elapsed on the host
12 sim_insts 1384378595 # Number of instructions simulated
13 sim_ops 1885333347 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 475105 # Total number of read requests seen
38 system.physmem.writeReqs 66098 # Total number of write requests seen
39 system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 30406656 # Total number of bytes read from memory
41 system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 635788203500 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 475105 # Categorize read packet sizes
88 system.physmem.readPktSize::7 0 # Categorize read packet sizes
89 system.physmem.readPktSize::8 0 # Categorize read packet sizes
90 system.physmem.writePktSize::0 0 # categorize write packet sizes
91 system.physmem.writePktSize::1 0 # categorize write packet sizes
92 system.physmem.writePktSize::2 0 # categorize write packet sizes
93 system.physmem.writePktSize::3 0 # categorize write packet sizes
94 system.physmem.writePktSize::4 0 # categorize write packet sizes
95 system.physmem.writePktSize::5 0 # categorize write packet sizes
96 system.physmem.writePktSize::6 66098 # categorize write packet sizes
97 system.physmem.writePktSize::7 0 # categorize write packet sizes
98 system.physmem.writePktSize::8 0 # categorize write packet sizes
99 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
100 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
101 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
102 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
103 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
104 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
105 system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes
106 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
107 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
108 system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
141 system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
174 system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays
175 system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests
176 system.physmem.totBusLat 1899772000 # Total cycles spent in databus access
177 system.physmem.totBankLat 12889702000 # Total cycles spent in bank access
178 system.physmem.avgQLat 4835.74 # Average queueing delay per request
179 system.physmem.avgBankLat 27139.47 # Average bank access latency per request
180 system.physmem.avgBusLat 4000.00 # Average bus latency per request
181 system.physmem.avgMemAccLat 35975.21 # Average memory access latency
182 system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s
183 system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s
184 system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s
185 system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s
186 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
187 system.physmem.busUtil 0.34 # Data bus utilization in percentage
188 system.physmem.avgRdQLen 0.03 # Average read queue length over time
189 system.physmem.avgWrQLen 17.42 # Average write queue length over time
190 system.physmem.readRowHits 249227 # Number of row buffer hits during reads
191 system.physmem.writeRowHits 48069 # Number of row buffer hits during writes
192 system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads
193 system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes
194 system.physmem.avgGap 1174768.44 # Average gap between requests
195 system.cpu.dtb.inst_hits 0 # ITB inst hits
196 system.cpu.dtb.inst_misses 0 # ITB inst misses
197 system.cpu.dtb.read_hits 0 # DTB read hits
198 system.cpu.dtb.read_misses 0 # DTB read misses
199 system.cpu.dtb.write_hits 0 # DTB write hits
200 system.cpu.dtb.write_misses 0 # DTB write misses
201 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
202 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
203 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
204 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
205 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
206 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
207 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
208 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
209 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
210 system.cpu.dtb.read_accesses 0 # DTB read accesses
211 system.cpu.dtb.write_accesses 0 # DTB write accesses
212 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
213 system.cpu.dtb.hits 0 # DTB hits
214 system.cpu.dtb.misses 0 # DTB misses
215 system.cpu.dtb.accesses 0 # DTB accesses
216 system.cpu.itb.inst_hits 0 # ITB inst hits
217 system.cpu.itb.inst_misses 0 # ITB inst misses
218 system.cpu.itb.read_hits 0 # DTB read hits
219 system.cpu.itb.read_misses 0 # DTB read misses
220 system.cpu.itb.write_hits 0 # DTB write hits
221 system.cpu.itb.write_misses 0 # DTB write misses
222 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
223 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
224 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
225 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
226 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
227 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
228 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
229 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
230 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
231 system.cpu.itb.read_accesses 0 # DTB read accesses
232 system.cpu.itb.write_accesses 0 # DTB write accesses
233 system.cpu.itb.inst_accesses 0 # ITB inst accesses
234 system.cpu.itb.hits 0 # DTB hits
235 system.cpu.itb.misses 0 # DTB misses
236 system.cpu.itb.accesses 0 # DTB accesses
237 system.cpu.workload.num_syscalls 1411 # Number of system calls
238 system.cpu.numCycles 1271576449 # number of cpu cycles simulated
239 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
240 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
241 system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups
242 system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted
243 system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect
244 system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups
245 system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits
246 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
247 system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target.
248 system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions.
249 system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss
250 system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed
251 system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered
252 system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken
253 system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked
254 system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing
255 system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked
256 system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
257 system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps
258 system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR
259 system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched
260 system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed
261 system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
265 system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total)
266 system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total)
267 system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total)
268 system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total)
269 system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total)
270 system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total)
271 system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total)
272 system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total)
273 system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total)
274 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
275 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
276 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
277 system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total)
278 system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle
279 system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle
280 system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle
281 system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked
282 system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running
283 system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking
284 system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing
285 system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch
286 system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction
287 system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode
288 system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode
289 system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing
290 system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle
291 system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking
292 system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst
293 system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running
294 system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking
295 system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename
296 system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full
297 system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full
298 system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full
299 system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
300 system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed
301 system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made
302 system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups
303 system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups
304 system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed
305 system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing
306 system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed
307 system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed
308 system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer
309 system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit.
310 system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit.
311 system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads.
312 system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores.
313 system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec)
314 system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ
315 system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued
316 system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued
317 system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling
318 system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph
319 system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed
320 system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle
323 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
324 system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle
325 system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle
326 system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle
327 system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle
328 system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle
329 system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle
330 system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle
331 system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle
332 system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle
333 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
334 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
335 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
336 system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle
337 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
338 system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available
339 system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available
340 system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
341 system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
342 system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
343 system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
344 system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
345 system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
346 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
353 system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
354 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
355 system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
356 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
357 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
358 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
359 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
360 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
361 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
362 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
363 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
364 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
365 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
366 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
367 system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available
368 system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available
369 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
370 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
371 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
372 system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued
373 system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued
374 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued
375 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued
376 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued
377 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued
378 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued
379 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued
380 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued
387 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued
388 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued
389 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued
390 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued
391 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued
392 system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued
393 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued
394 system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued
395 system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued
396 system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued
397 system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued
398 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued
399 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued
400 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued
401 system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued
402 system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued
403 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
404 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
405 system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued
406 system.cpu.iq.rate 1.943803 # Inst issue rate
407 system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested
408 system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst)
409 system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads
410 system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes
411 system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses
412 system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads
413 system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes
414 system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses
415 system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses
416 system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses
417 system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores
418 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
419 system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed
420 system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed
421 system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations
422 system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed
423 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
424 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
425 system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
426 system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked
427 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
428 system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing
429 system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking
430 system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking
431 system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ
432 system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch
433 system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions
434 system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions
435 system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions
436 system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall
437 system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall
438 system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations
439 system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly
440 system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly
441 system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute
442 system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions
443 system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed
444 system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute
445 system.cpu.iew.exec_swp 0 # number of swp insts executed
446 system.cpu.iew.exec_nop 14051 # number of nop insts executed
447 system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed
448 system.cpu.iew.exec_branches 327128098 # Number of branches executed
449 system.cpu.iew.exec_stores 436123806 # Number of stores executed
450 system.cpu.iew.exec_rate 1.883710 # Inst execution rate
451 system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit
452 system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back
453 system.cpu.iew.wb_producers 1354502475 # num instructions producing a value
454 system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value
455 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
456 system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle
457 system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back
458 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
459 system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit
460 system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards
461 system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted
462 system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle
465 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
466 system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle
467 system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle
468 system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle
469 system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle
470 system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle
471 system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle
472 system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle
473 system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle
474 system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle
475 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
476 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
477 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
478 system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle
479 system.cpu.commit.committedInsts 1384389611 # Number of instructions committed
480 system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed
481 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
482 system.cpu.commit.refs 908385680 # Number of memory references committed
483 system.cpu.commit.loads 631388782 # Number of loads committed
484 system.cpu.commit.membars 9986 # Number of memory barriers committed
485 system.cpu.commit.branches 299635996 # Number of branches committed
486 system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
487 system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions.
488 system.cpu.commit.function_calls 41577833 # Number of function calls committed.
489 system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached
490 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
491 system.cpu.rob.rob_reads 3864096043 # The number of ROB reads
492 system.cpu.rob.rob_writes 5823945497 # The number of ROB writes
493 system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself
494 system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling
495 system.cpu.committedInsts 1384378595 # Number of Instructions Simulated
496 system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated
497 system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated
498 system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction
499 system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads
500 system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle
501 system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads
502 system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads
503 system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes
504 system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads
505 system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes
506 system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads
507 system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes
508 system.cpu.icache.replacements 23916 # number of replacements
509 system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use
510 system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks.
511 system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks.
512 system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks.
513 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
514 system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor
515 system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy
516 system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy
517 system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits
518 system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits
519 system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits
520 system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits
521 system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits
522 system.cpu.icache.overall_hits::total 346934721 # number of overall hits
523 system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses
524 system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses
525 system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses
526 system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses
527 system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses
528 system.cpu.icache.overall_misses::total 32652 # number of overall misses
529 system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles
530 system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles
531 system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles
532 system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles
533 system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles
534 system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles
535 system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses)
536 system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses)
537 system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses
538 system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses
539 system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses
540 system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses
541 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses
542 system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses
543 system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses
544 system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses
545 system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses
546 system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses
547 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency
548 system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency
549 system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency
550 system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency
551 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency
552 system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency
553 system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked
554 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
555 system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked
556 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
557 system.cpu.icache.avg_blocked_cycles::no_mshrs 41.685714 # average number of cycles each access was blocked
558 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
559 system.cpu.icache.fast_writes 0 # number of fast writes performed
560 system.cpu.icache.cache_copies 0 # number of cache copies performed
561 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2714 # number of ReadReq MSHR hits
562 system.cpu.icache.ReadReq_mshr_hits::total 2714 # number of ReadReq MSHR hits
563 system.cpu.icache.demand_mshr_hits::cpu.inst 2714 # number of demand (read+write) MSHR hits
564 system.cpu.icache.demand_mshr_hits::total 2714 # number of demand (read+write) MSHR hits
565 system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits
566 system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits
567 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses
568 system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses
569 system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses
570 system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses
571 system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses
572 system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses
573 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles
574 system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles
575 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR miss cycles
576 system.cpu.icache.demand_mshr_miss_latency::total 396628999 # number of demand (read+write) MSHR miss cycles
577 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 396628999 # number of overall MSHR miss cycles
578 system.cpu.icache.overall_mshr_miss_latency::total 396628999 # number of overall MSHR miss cycles
579 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
580 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
581 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
582 system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
583 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
584 system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
585 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency
586 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency
587 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency
588 system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency
589 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency
590 system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency
591 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
592 system.cpu.dcache.replacements 1533079 # number of replacements
593 system.cpu.dcache.tagsinuse 4094.602102 # Cycle average of tags in use
594 system.cpu.dcache.total_refs 974126836 # Total number of references to valid blocks.
595 system.cpu.dcache.sampled_refs 1537175 # Sample count of references to valid blocks.
596 system.cpu.dcache.avg_refs 633.712385 # Average number of references to valid blocks.
597 system.cpu.dcache.warmup_cycle 342496000 # Cycle when the warmup percentage was hit.
598 system.cpu.dcache.occ_blocks::cpu.data 4094.602102 # Average occupied blocks per requestor
599 system.cpu.dcache.occ_percent::cpu.data 0.999659 # Average percentage of cache occupancy
600 system.cpu.dcache.occ_percent::total 0.999659 # Average percentage of cache occupancy
601 system.cpu.dcache.ReadReq_hits::cpu.data 697989238 # number of ReadReq hits
602 system.cpu.dcache.ReadReq_hits::total 697989238 # number of ReadReq hits
603 system.cpu.dcache.WriteReq_hits::cpu.data 276101323 # number of WriteReq hits
604 system.cpu.dcache.WriteReq_hits::total 276101323 # number of WriteReq hits
605 system.cpu.dcache.LoadLockedReq_hits::cpu.data 12267 # number of LoadLockedReq hits
606 system.cpu.dcache.LoadLockedReq_hits::total 12267 # number of LoadLockedReq hits
607 system.cpu.dcache.StoreCondReq_hits::cpu.data 11586 # number of StoreCondReq hits
608 system.cpu.dcache.StoreCondReq_hits::total 11586 # number of StoreCondReq hits
609 system.cpu.dcache.demand_hits::cpu.data 974090561 # number of demand (read+write) hits
610 system.cpu.dcache.demand_hits::total 974090561 # number of demand (read+write) hits
611 system.cpu.dcache.overall_hits::cpu.data 974090561 # number of overall hits
612 system.cpu.dcache.overall_hits::total 974090561 # number of overall hits
613 system.cpu.dcache.ReadReq_misses::cpu.data 2001936 # number of ReadReq misses
614 system.cpu.dcache.ReadReq_misses::total 2001936 # number of ReadReq misses
615 system.cpu.dcache.WriteReq_misses::cpu.data 834355 # number of WriteReq misses
616 system.cpu.dcache.WriteReq_misses::total 834355 # number of WriteReq misses
617 system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
618 system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
619 system.cpu.dcache.demand_misses::cpu.data 2836291 # number of demand (read+write) misses
620 system.cpu.dcache.demand_misses::total 2836291 # number of demand (read+write) misses
621 system.cpu.dcache.overall_misses::cpu.data 2836291 # number of overall misses
622 system.cpu.dcache.overall_misses::total 2836291 # number of overall misses
623 system.cpu.dcache.ReadReq_miss_latency::cpu.data 68815075500 # number of ReadReq miss cycles
624 system.cpu.dcache.ReadReq_miss_latency::total 68815075500 # number of ReadReq miss cycles
625 system.cpu.dcache.WriteReq_miss_latency::cpu.data 39938491970 # number of WriteReq miss cycles
626 system.cpu.dcache.WriteReq_miss_latency::total 39938491970 # number of WriteReq miss cycles
627 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles
628 system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles
629 system.cpu.dcache.demand_miss_latency::cpu.data 108753567470 # number of demand (read+write) miss cycles
630 system.cpu.dcache.demand_miss_latency::total 108753567470 # number of demand (read+write) miss cycles
631 system.cpu.dcache.overall_miss_latency::cpu.data 108753567470 # number of overall miss cycles
632 system.cpu.dcache.overall_miss_latency::total 108753567470 # number of overall miss cycles
633 system.cpu.dcache.ReadReq_accesses::cpu.data 699991174 # number of ReadReq accesses(hits+misses)
634 system.cpu.dcache.ReadReq_accesses::total 699991174 # number of ReadReq accesses(hits+misses)
635 system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
636 system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
637 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12269 # number of LoadLockedReq accesses(hits+misses)
638 system.cpu.dcache.LoadLockedReq_accesses::total 12269 # number of LoadLockedReq accesses(hits+misses)
639 system.cpu.dcache.StoreCondReq_accesses::cpu.data 11586 # number of StoreCondReq accesses(hits+misses)
640 system.cpu.dcache.StoreCondReq_accesses::total 11586 # number of StoreCondReq accesses(hits+misses)
641 system.cpu.dcache.demand_accesses::cpu.data 976926852 # number of demand (read+write) accesses
642 system.cpu.dcache.demand_accesses::total 976926852 # number of demand (read+write) accesses
643 system.cpu.dcache.overall_accesses::cpu.data 976926852 # number of overall (read+write) accesses
644 system.cpu.dcache.overall_accesses::total 976926852 # number of overall (read+write) accesses
645 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002860 # miss rate for ReadReq accesses
646 system.cpu.dcache.ReadReq_miss_rate::total 0.002860 # miss rate for ReadReq accesses
647 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003013 # miss rate for WriteReq accesses
648 system.cpu.dcache.WriteReq_miss_rate::total 0.003013 # miss rate for WriteReq accesses
649 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses
650 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses
651 system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses
652 system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses
653 system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses
654 system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses
655 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency
656 system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency
657 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency
658 system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency
659 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency
660 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency
661 system.cpu.dcache.demand_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency
662 system.cpu.dcache.demand_avg_miss_latency::total 38343.585856 # average overall miss latency
663 system.cpu.dcache.overall_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency
664 system.cpu.dcache.overall_avg_miss_latency::total 38343.585856 # average overall miss latency
665 system.cpu.dcache.blocked_cycles::no_mshrs 1801 # number of cycles access was blocked
666 system.cpu.dcache.blocked_cycles::no_targets 752 # number of cycles access was blocked
667 system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked
668 system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked
669 system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.016667 # average number of cycles each access was blocked
670 system.cpu.dcache.avg_blocked_cycles::no_targets 8.847059 # average number of cycles each access was blocked
671 system.cpu.dcache.fast_writes 0 # number of fast writes performed
672 system.cpu.dcache.cache_copies 0 # number of cache copies performed
673 system.cpu.dcache.writebacks::writebacks 96247 # number of writebacks
674 system.cpu.dcache.writebacks::total 96247 # number of writebacks
675 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 537314 # number of ReadReq MSHR hits
676 system.cpu.dcache.ReadReq_mshr_hits::total 537314 # number of ReadReq MSHR hits
677 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757477 # number of WriteReq MSHR hits
678 system.cpu.dcache.WriteReq_mshr_hits::total 757477 # number of WriteReq MSHR hits
679 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
680 system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
681 system.cpu.dcache.demand_mshr_hits::cpu.data 1294791 # number of demand (read+write) MSHR hits
682 system.cpu.dcache.demand_mshr_hits::total 1294791 # number of demand (read+write) MSHR hits
683 system.cpu.dcache.overall_mshr_hits::cpu.data 1294791 # number of overall MSHR hits
684 system.cpu.dcache.overall_mshr_hits::total 1294791 # number of overall MSHR hits
685 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464622 # number of ReadReq MSHR misses
686 system.cpu.dcache.ReadReq_mshr_misses::total 1464622 # number of ReadReq MSHR misses
687 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76878 # number of WriteReq MSHR misses
688 system.cpu.dcache.WriteReq_mshr_misses::total 76878 # number of WriteReq MSHR misses
689 system.cpu.dcache.demand_mshr_misses::cpu.data 1541500 # number of demand (read+write) MSHR misses
690 system.cpu.dcache.demand_mshr_misses::total 1541500 # number of demand (read+write) MSHR misses
691 system.cpu.dcache.overall_mshr_misses::cpu.data 1541500 # number of overall MSHR misses
692 system.cpu.dcache.overall_mshr_misses::total 1541500 # number of overall MSHR misses
693 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36879858500 # number of ReadReq MSHR miss cycles
694 system.cpu.dcache.ReadReq_mshr_miss_latency::total 36879858500 # number of ReadReq MSHR miss cycles
695 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3477356000 # number of WriteReq MSHR miss cycles
696 system.cpu.dcache.WriteReq_mshr_miss_latency::total 3477356000 # number of WriteReq MSHR miss cycles
697 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40357214500 # number of demand (read+write) MSHR miss cycles
698 system.cpu.dcache.demand_mshr_miss_latency::total 40357214500 # number of demand (read+write) MSHR miss cycles
699 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40357214500 # number of overall MSHR miss cycles
700 system.cpu.dcache.overall_mshr_miss_latency::total 40357214500 # number of overall MSHR miss cycles
701 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002092 # mshr miss rate for ReadReq accesses
702 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002092 # mshr miss rate for ReadReq accesses
703 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
704 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
705 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for demand accesses
706 system.cpu.dcache.demand_mshr_miss_rate::total 0.001578 # mshr miss rate for demand accesses
707 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for overall accesses
708 system.cpu.dcache.overall_mshr_miss_rate::total 0.001578 # mshr miss rate for overall accesses
709 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25180.461921 # average ReadReq mshr miss latency
710 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25180.461921 # average ReadReq mshr miss latency
711 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45232.134031 # average WriteReq mshr miss latency
712 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45232.134031 # average WriteReq mshr miss latency
713 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency
714 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency
715 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency
716 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency
717 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
718 system.cpu.l2cache.replacements 442324 # number of replacements
719 system.cpu.l2cache.tagsinuse 32688.980204 # Cycle average of tags in use
720 system.cpu.l2cache.total_refs 1110893 # Total number of references to valid blocks.
721 system.cpu.l2cache.sampled_refs 475069 # Sample count of references to valid blocks.
722 system.cpu.l2cache.avg_refs 2.338382 # Average number of references to valid blocks.
723 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
724 system.cpu.l2cache.occ_blocks::writebacks 1305.388172 # Average occupied blocks per requestor
725 system.cpu.l2cache.occ_blocks::cpu.inst 55.371770 # Average occupied blocks per requestor
726 system.cpu.l2cache.occ_blocks::cpu.data 31328.220262 # Average occupied blocks per requestor
727 system.cpu.l2cache.occ_percent::writebacks 0.039837 # Average percentage of cache occupancy
728 system.cpu.l2cache.occ_percent::cpu.inst 0.001690 # Average percentage of cache occupancy
729 system.cpu.l2cache.occ_percent::cpu.data 0.956061 # Average percentage of cache occupancy
730 system.cpu.l2cache.occ_percent::total 0.997589 # Average percentage of cache occupancy
731 system.cpu.l2cache.ReadReq_hits::cpu.inst 23103 # number of ReadReq hits
732 system.cpu.l2cache.ReadReq_hits::cpu.data 1058082 # number of ReadReq hits
733 system.cpu.l2cache.ReadReq_hits::total 1081185 # number of ReadReq hits
734 system.cpu.l2cache.Writeback_hits::writebacks 96247 # number of Writeback hits
735 system.cpu.l2cache.Writeback_hits::total 96247 # number of Writeback hits
736 system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
737 system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
738 system.cpu.l2cache.ReadExReq_hits::cpu.data 6476 # number of ReadExReq hits
739 system.cpu.l2cache.ReadExReq_hits::total 6476 # number of ReadExReq hits
740 system.cpu.l2cache.demand_hits::cpu.inst 23103 # number of demand (read+write) hits
741 system.cpu.l2cache.demand_hits::cpu.data 1064558 # number of demand (read+write) hits
742 system.cpu.l2cache.demand_hits::total 1087661 # number of demand (read+write) hits
743 system.cpu.l2cache.overall_hits::cpu.inst 23103 # number of overall hits
744 system.cpu.l2cache.overall_hits::cpu.data 1064558 # number of overall hits
745 system.cpu.l2cache.overall_hits::total 1087661 # number of overall hits
746 system.cpu.l2cache.ReadReq_misses::cpu.inst 2512 # number of ReadReq misses
747 system.cpu.l2cache.ReadReq_misses::cpu.data 406540 # number of ReadReq misses
748 system.cpu.l2cache.ReadReq_misses::total 409052 # number of ReadReq misses
749 system.cpu.l2cache.UpgradeReq_misses::cpu.data 4321 # number of UpgradeReq misses
750 system.cpu.l2cache.UpgradeReq_misses::total 4321 # number of UpgradeReq misses
751 system.cpu.l2cache.ReadExReq_misses::cpu.data 66078 # number of ReadExReq misses
752 system.cpu.l2cache.ReadExReq_misses::total 66078 # number of ReadExReq misses
753 system.cpu.l2cache.demand_misses::cpu.inst 2512 # number of demand (read+write) misses
754 system.cpu.l2cache.demand_misses::cpu.data 472618 # number of demand (read+write) misses
755 system.cpu.l2cache.demand_misses::total 475130 # number of demand (read+write) misses
756 system.cpu.l2cache.overall_misses::cpu.inst 2512 # number of overall misses
757 system.cpu.l2cache.overall_misses::cpu.data 472618 # number of overall misses
758 system.cpu.l2cache.overall_misses::total 475130 # number of overall misses
759 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 131130500 # number of ReadReq miss cycles
760 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24833789000 # number of ReadReq miss cycles
761 system.cpu.l2cache.ReadReq_miss_latency::total 24964919500 # number of ReadReq miss cycles
762 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3241668500 # number of ReadExReq miss cycles
763 system.cpu.l2cache.ReadExReq_miss_latency::total 3241668500 # number of ReadExReq miss cycles
764 system.cpu.l2cache.demand_miss_latency::cpu.inst 131130500 # number of demand (read+write) miss cycles
765 system.cpu.l2cache.demand_miss_latency::cpu.data 28075457500 # number of demand (read+write) miss cycles
766 system.cpu.l2cache.demand_miss_latency::total 28206588000 # number of demand (read+write) miss cycles
767 system.cpu.l2cache.overall_miss_latency::cpu.inst 131130500 # number of overall miss cycles
768 system.cpu.l2cache.overall_miss_latency::cpu.data 28075457500 # number of overall miss cycles
769 system.cpu.l2cache.overall_miss_latency::total 28206588000 # number of overall miss cycles
770 system.cpu.l2cache.ReadReq_accesses::cpu.inst 25615 # number of ReadReq accesses(hits+misses)
771 system.cpu.l2cache.ReadReq_accesses::cpu.data 1464622 # number of ReadReq accesses(hits+misses)
772 system.cpu.l2cache.ReadReq_accesses::total 1490237 # number of ReadReq accesses(hits+misses)
773 system.cpu.l2cache.Writeback_accesses::writebacks 96247 # number of Writeback accesses(hits+misses)
774 system.cpu.l2cache.Writeback_accesses::total 96247 # number of Writeback accesses(hits+misses)
775 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4324 # number of UpgradeReq accesses(hits+misses)
776 system.cpu.l2cache.UpgradeReq_accesses::total 4324 # number of UpgradeReq accesses(hits+misses)
777 system.cpu.l2cache.ReadExReq_accesses::cpu.data 72554 # number of ReadExReq accesses(hits+misses)
778 system.cpu.l2cache.ReadExReq_accesses::total 72554 # number of ReadExReq accesses(hits+misses)
779 system.cpu.l2cache.demand_accesses::cpu.inst 25615 # number of demand (read+write) accesses
780 system.cpu.l2cache.demand_accesses::cpu.data 1537176 # number of demand (read+write) accesses
781 system.cpu.l2cache.demand_accesses::total 1562791 # number of demand (read+write) accesses
782 system.cpu.l2cache.overall_accesses::cpu.inst 25615 # number of overall (read+write) accesses
783 system.cpu.l2cache.overall_accesses::cpu.data 1537176 # number of overall (read+write) accesses
784 system.cpu.l2cache.overall_accesses::total 1562791 # number of overall (read+write) accesses
785 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098068 # miss rate for ReadReq accesses
786 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277573 # miss rate for ReadReq accesses
787 system.cpu.l2cache.ReadReq_miss_rate::total 0.274488 # miss rate for ReadReq accesses
788 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999306 # miss rate for UpgradeReq accesses
789 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999306 # miss rate for UpgradeReq accesses
790 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910742 # miss rate for ReadExReq accesses
791 system.cpu.l2cache.ReadExReq_miss_rate::total 0.910742 # miss rate for ReadExReq accesses
792 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098068 # miss rate for demand accesses
793 system.cpu.l2cache.demand_miss_rate::cpu.data 0.307459 # miss rate for demand accesses
794 system.cpu.l2cache.demand_miss_rate::total 0.304027 # miss rate for demand accesses
795 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098068 # miss rate for overall accesses
796 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307459 # miss rate for overall accesses
797 system.cpu.l2cache.overall_miss_rate::total 0.304027 # miss rate for overall accesses
798 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52201.632166 # average ReadReq miss latency
799 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61085.720962 # average ReadReq miss latency
800 system.cpu.l2cache.ReadReq_avg_miss_latency::total 61031.163520 # average ReadReq miss latency
801 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49058.211508 # average ReadExReq miss latency
802 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49058.211508 # average ReadExReq miss latency
803 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52201.632166 # average overall miss latency
804 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59404.122357 # average overall miss latency
805 system.cpu.l2cache.demand_avg_miss_latency::total 59366.042978 # average overall miss latency
806 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52201.632166 # average overall miss latency
807 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59404.122357 # average overall miss latency
808 system.cpu.l2cache.overall_avg_miss_latency::total 59366.042978 # average overall miss latency
809 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
810 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
811 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
812 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
813 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
814 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
815 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
816 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
817 system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
818 system.cpu.l2cache.writebacks::total 66098 # number of writebacks
819 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
820 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
821 system.cpu.l2cache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits
822 system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
823 system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
824 system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
825 system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
826 system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
827 system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits
828 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2509 # number of ReadReq MSHR misses
829 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406518 # number of ReadReq MSHR misses
830 system.cpu.l2cache.ReadReq_mshr_misses::total 409027 # number of ReadReq MSHR misses
831 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4321 # number of UpgradeReq MSHR misses
832 system.cpu.l2cache.UpgradeReq_mshr_misses::total 4321 # number of UpgradeReq MSHR misses
833 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses
834 system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses
835 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2509 # number of demand (read+write) MSHR misses
836 system.cpu.l2cache.demand_mshr_misses::cpu.data 472596 # number of demand (read+write) MSHR misses
837 system.cpu.l2cache.demand_mshr_misses::total 475105 # number of demand (read+write) MSHR misses
838 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2509 # number of overall MSHR misses
839 system.cpu.l2cache.overall_mshr_misses::cpu.data 472596 # number of overall MSHR misses
840 system.cpu.l2cache.overall_mshr_misses::total 475105 # number of overall MSHR misses
841 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 99443391 # number of ReadReq MSHR miss cycles
842 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19690336164 # number of ReadReq MSHR miss cycles
843 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19789779555 # number of ReadReq MSHR miss cycles
844 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43223820 # number of UpgradeReq MSHR miss cycles
845 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43223820 # number of UpgradeReq MSHR miss cycles
846 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2389121519 # number of ReadExReq MSHR miss cycles
847 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2389121519 # number of ReadExReq MSHR miss cycles
848 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99443391 # number of demand (read+write) MSHR miss cycles
849 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22079457683 # number of demand (read+write) MSHR miss cycles
850 system.cpu.l2cache.demand_mshr_miss_latency::total 22178901074 # number of demand (read+write) MSHR miss cycles
851 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99443391 # number of overall MSHR miss cycles
852 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22079457683 # number of overall MSHR miss cycles
853 system.cpu.l2cache.overall_mshr_miss_latency::total 22178901074 # number of overall MSHR miss cycles
854 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for ReadReq accesses
855 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses
856 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274471 # mshr miss rate for ReadReq accesses
857 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999306 # mshr miss rate for UpgradeReq accesses
858 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999306 # mshr miss rate for UpgradeReq accesses
859 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910742 # mshr miss rate for ReadExReq accesses
860 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910742 # mshr miss rate for ReadExReq accesses
861 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for demand accesses
862 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for demand accesses
863 system.cpu.l2cache.demand_mshr_miss_rate::total 0.304011 # mshr miss rate for demand accesses
864 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for overall accesses
865 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for overall accesses
866 system.cpu.l2cache.overall_mshr_miss_rate::total 0.304011 # mshr miss rate for overall accesses
867 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39634.671582 # average ReadReq mshr miss latency
868 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48436.566558 # average ReadReq mshr miss latency
869 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48382.575123 # average ReadReq mshr miss latency
870 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.198334 # average UpgradeReq mshr miss latency
871 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.198334 # average UpgradeReq mshr miss latency
872 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36156.080980 # average ReadExReq mshr miss latency
873 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36156.080980 # average ReadExReq mshr miss latency
874 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency
875 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency
876 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency
877 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency
878 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency
879 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency
880 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
882 ---------- End Simulation Statistics ----------
projects / gem5.git / blob