8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
24 memories=system.physmem
28 work_begin_ckpt_count=0
29 work_begin_cpu_id_exit=-1
30 work_begin_exit_count=0
31 work_cpus_ckpt_count=0
35 system_port=system.membus.slave[0]
41 voltage_domain=system.voltage_domain
45 children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
47 clk_domain=system.cpu_clk_domain
49 do_checkpoint_insts=true
51 do_statistics_insts=true
52 dstage2_mmu=system.cpu.dstage2_mmu
57 function_trace_start=0
58 interrupts=system.cpu.interrupts
60 istage2_mmu=system.cpu.istage2_mmu
62 max_insts_all_threads=0
63 max_insts_any_thread=0
64 max_loads_all_threads=0
65 max_loads_any_thread=0
69 simpoint_interval=100000000
70 simpoint_profile=false
71 simpoint_profile_file=simpoint.bb.gz
73 simulate_data_stalls=false
74 simulate_inst_stalls=false
77 tracer=system.cpu.tracer
79 workload=system.cpu.workload
80 dcache_port=system.membus.slave[2]
81 icache_port=system.membus.slave[1]
83 [system.cpu.dstage2_mmu]
87 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
90 [system.cpu.dstage2_mmu.stage2_tlb]
96 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
98 [system.cpu.dstage2_mmu.stage2_tlb.walker]
100 clk_domain=system.cpu_clk_domain
103 num_squash_per_cycle=2
105 port=system.membus.slave[6]
113 walker=system.cpu.dtb.walker
115 [system.cpu.dtb.walker]
117 clk_domain=system.cpu_clk_domain
120 num_squash_per_cycle=2
122 port=system.membus.slave[4]
124 [system.cpu.interrupts]
134 id_aa64dfr0_el1=1052678
138 id_aa64mmfr0_el1=15728642
157 [system.cpu.istage2_mmu]
161 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
164 [system.cpu.istage2_mmu.stage2_tlb]
170 walker=system.cpu.istage2_mmu.stage2_tlb.walker
172 [system.cpu.istage2_mmu.stage2_tlb.walker]
174 clk_domain=system.cpu_clk_domain
177 num_squash_per_cycle=2
179 port=system.membus.slave[5]
187 walker=system.cpu.itb.walker
189 [system.cpu.itb.walker]
191 clk_domain=system.cpu_clk_domain
194 num_squash_per_cycle=2
196 port=system.membus.slave[3]
202 [system.cpu.workload]
204 cmd=perlbmk -I. -I lib lgred.makerand.pl
205 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
211 executable=/dist/cpu2000/binaries/arm/linux/perlbmk
214 max_stack_size=67108864
222 [system.cpu_clk_domain]
226 voltage_domain=system.voltage_domain
230 clk_domain=system.clk_domain
234 use_default_range=false
236 master=system.physmem.port
237 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
242 clk_domain=system.clk_domain
243 conf_table_reported=true
250 port=system.membus.master[0]
252 [system.voltage_domain]