8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
25 memories=system.physmem
29 work_begin_ckpt_count=0
30 work_begin_cpu_id_exit=-1
31 work_begin_exit_count=0
32 work_cpus_ckpt_count=0
36 system_port=system.membus.slave[0]
44 voltage_domain=system.voltage_domain
48 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
51 clk_domain=system.cpu_clk_domain
53 do_checkpoint_insts=true
55 do_statistics_insts=true
56 dstage2_mmu=system.cpu.dstage2_mmu
60 function_trace_start=0
61 interrupts=system.cpu.interrupts
63 istage2_mmu=system.cpu.istage2_mmu
65 max_insts_all_threads=0
66 max_insts_any_thread=0
67 max_loads_all_threads=0
68 max_loads_any_thread=0
76 tracer=system.cpu.tracer
77 workload=system.cpu.workload
78 dcache_port=system.cpu.dcache.cpu_side
79 icache_port=system.cpu.icache.cpu_side
84 addr_ranges=0:18446744073709551615
86 clk_domain=system.cpu_clk_domain
93 prefetch_on_access=false
96 sequential_access=false
99 tags=system.cpu.dcache.tags
103 cpu_side=system.cpu.dcache_port
104 mem_side=system.cpu.toL2Bus.slave[1]
106 [system.cpu.dcache.tags]
110 clk_domain=system.cpu_clk_domain
113 sequential_access=false
116 [system.cpu.dstage2_mmu]
120 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
123 [system.cpu.dstage2_mmu.stage2_tlb]
129 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
131 [system.cpu.dstage2_mmu.stage2_tlb.walker]
133 clk_domain=system.cpu_clk_domain
136 num_squash_per_cycle=2
138 port=system.cpu.toL2Bus.slave[5]
146 walker=system.cpu.dtb.walker
148 [system.cpu.dtb.walker]
150 clk_domain=system.cpu_clk_domain
153 num_squash_per_cycle=2
155 port=system.cpu.toL2Bus.slave[3]
160 addr_ranges=0:18446744073709551615
162 clk_domain=system.cpu_clk_domain
169 prefetch_on_access=false
172 sequential_access=false
175 tags=system.cpu.icache.tags
179 cpu_side=system.cpu.icache_port
180 mem_side=system.cpu.toL2Bus.slave[0]
182 [system.cpu.icache.tags]
186 clk_domain=system.cpu_clk_domain
189 sequential_access=false
192 [system.cpu.interrupts]
202 id_aa64dfr0_el1=1052678
206 id_aa64mmfr0_el1=15728642
225 [system.cpu.istage2_mmu]
229 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
232 [system.cpu.istage2_mmu.stage2_tlb]
238 walker=system.cpu.istage2_mmu.stage2_tlb.walker
240 [system.cpu.istage2_mmu.stage2_tlb.walker]
242 clk_domain=system.cpu_clk_domain
245 num_squash_per_cycle=2
247 port=system.cpu.toL2Bus.slave[4]
255 walker=system.cpu.itb.walker
257 [system.cpu.itb.walker]
259 clk_domain=system.cpu_clk_domain
262 num_squash_per_cycle=2
264 port=system.cpu.toL2Bus.slave[2]
269 addr_ranges=0:18446744073709551615
271 clk_domain=system.cpu_clk_domain
278 prefetch_on_access=false
281 sequential_access=false
284 tags=system.cpu.l2cache.tags
288 cpu_side=system.cpu.toL2Bus.master[0]
289 mem_side=system.membus.slave[1]
291 [system.cpu.l2cache.tags]
295 clk_domain=system.cpu_clk_domain
298 sequential_access=false
303 clk_domain=system.cpu_clk_domain
308 use_default_range=false
310 master=system.cpu.l2cache.cpu_side
311 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
317 [system.cpu.workload]
319 cmd=perlbmk -I. -I lib mdred.makerand.pl
320 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
326 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
329 max_stack_size=67108864
338 [system.cpu_clk_domain]
344 voltage_domain=system.voltage_domain
346 [system.dvfs_handler]
351 sys_clk_domain=system.clk_domain
352 transition_latency=100000000
356 clk_domain=system.clk_domain
361 use_default_range=false
363 master=system.physmem.port
364 slave=system.system_port system.cpu.l2cache.mem_side
369 clk_domain=system.clk_domain
370 conf_table_reported=true
377 port=system.membus.master[0]
379 [system.voltage_domain]