e7d15bd7cc645e354671c093149ac01c3d2ec271
6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
14 clk_domain=system.clk_domain
17 load_addr_mask=1099511627775
20 memories=system.physmem
24 work_begin_ckpt_count=0
25 work_begin_cpu_id_exit=-1
26 work_begin_exit_count=0
27 work_cpus_ckpt_count=0
31 system_port=system.membus.slave[0]
36 voltage_domain=system.voltage_domain
40 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
42 clk_domain=system.cpu_clk_domain
44 do_checkpoint_insts=true
46 do_statistics_insts=true
49 function_trace_start=0
50 interrupts=system.cpu.interrupts
53 max_insts_all_threads=0
54 max_insts_any_thread=0
55 max_loads_all_threads=0
56 max_loads_any_thread=0
63 tracer=system.cpu.tracer
64 workload=system.cpu.workload
65 dcache_port=system.cpu.dcache.cpu_side
66 icache_port=system.cpu.icache.cpu_side
71 addr_ranges=0:18446744073709551615
73 clk_domain=system.cpu_clk_domain
79 prefetch_on_access=false
84 tags=system.cpu.dcache.tags
88 cpu_side=system.cpu.dcache_port
89 mem_side=system.cpu.toL2Bus.slave[1]
91 [system.cpu.dcache.tags]
95 clk_domain=system.cpu_clk_domain
103 walker=system.cpu.dtb.walker
105 [system.cpu.dtb.walker]
107 clk_domain=system.cpu_clk_domain
108 num_squash_per_cycle=2
110 port=system.cpu.toL2Bus.slave[3]
115 addr_ranges=0:18446744073709551615
117 clk_domain=system.cpu_clk_domain
123 prefetch_on_access=false
128 tags=system.cpu.icache.tags
132 cpu_side=system.cpu.icache_port
133 mem_side=system.cpu.toL2Bus.slave[0]
135 [system.cpu.icache.tags]
139 clk_domain=system.cpu_clk_domain
143 [system.cpu.interrupts]
167 walker=system.cpu.itb.walker
169 [system.cpu.itb.walker]
171 clk_domain=system.cpu_clk_domain
172 num_squash_per_cycle=2
174 port=system.cpu.toL2Bus.slave[2]
179 addr_ranges=0:18446744073709551615
181 clk_domain=system.cpu_clk_domain
187 prefetch_on_access=false
192 tags=system.cpu.l2cache.tags
196 cpu_side=system.cpu.toL2Bus.master[0]
197 mem_side=system.membus.slave[1]
199 [system.cpu.l2cache.tags]
203 clk_domain=system.cpu_clk_domain
209 clk_domain=system.cpu_clk_domain
212 use_default_range=false
214 master=system.cpu.l2cache.cpu_side
215 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
220 [system.cpu.workload]
222 cmd=perlbmk -I. -I lib lgred.makerand.pl
223 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
228 executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
231 max_stack_size=67108864
239 [system.cpu_clk_domain]
242 voltage_domain=system.voltage_domain
246 clk_domain=system.clk_domain
249 use_default_range=false
251 master=system.physmem.port
252 slave=system.system_port system.cpu.l2cache.mem_side
257 clk_domain=system.clk_domain
258 conf_table_reported=true
264 port=system.membus.master[0]
266 [system.voltage_domain]