tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 kernel_addr_check=true
  21 load_addr_mask=1099511627775
  22 load_offset=0
  23 mem_mode=timing
  24 mem_ranges=
  25 memories=system.physmem
  26 mmap_using_noreserve=false
  27 num_work_ids=16
  28 readfile=
  29 symbolfile=
  30 work_begin_ckpt_count=0
  31 work_begin_cpu_id_exit=-1
  32 work_begin_exit_count=0
  33 work_cpus_ckpt_count=0
  34 work_end_ckpt_count=0
  35 work_end_exit_count=0
  36 work_item_id=-1
  37 system_port=system.membus.slave[0]
  38
  39 [system.clk_domain]
  40 type=SrcClockDomain
  41 clock=1000
  42 domain_id=-1
  43 eventq_index=0
  44 init_perf_level=0
  45 voltage_domain=system.voltage_domain
  46
  47 [system.cpu]
  48 type=TimingSimpleCPU
  49 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  50 branchPred=Null
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 cpu_id=0
  54 do_checkpoint_insts=true
  55 do_quiesce=true
  56 do_statistics_insts=true
  57 dstage2_mmu=system.cpu.dstage2_mmu
  58 dtb=system.cpu.dtb
  59 eventq_index=0
  60 function_trace=false
  61 function_trace_start=0
  62 interrupts=system.cpu.interrupts
  63 isa=system.cpu.isa
  64 istage2_mmu=system.cpu.istage2_mmu
  65 itb=system.cpu.itb
  66 max_insts_all_threads=0
  67 max_insts_any_thread=0
  68 max_loads_all_threads=0
  69 max_loads_any_thread=0
  70 numThreads=1
  71 profile=0
  72 progress_interval=0
  73 simpoint_start_insts=
  74 socket_id=0
  75 switched_out=false
  76 system=system
  77 tracer=system.cpu.tracer
  78 workload=system.cpu.workload
  79 dcache_port=system.cpu.dcache.cpu_side
  80 icache_port=system.cpu.icache.cpu_side
  81
  82 [system.cpu.dcache]
  83 type=BaseCache
  84 children=tags
  85 addr_ranges=0:18446744073709551615
  86 assoc=2
  87 clk_domain=system.cpu_clk_domain
  88 demand_mshr_reserve=1
  89 eventq_index=0
  90 forward_snoops=true
  91 hit_latency=2
  92 is_read_only=false
  93 max_miss_count=0
  94 mshrs=4
  95 prefetch_on_access=false
  96 prefetcher=Null
  97 response_latency=2
  98 sequential_access=false
  99 size=262144
 100 system=system
 101 tags=system.cpu.dcache.tags
 102 tgts_per_mshr=20
 103 write_buffers=8
 104 cpu_side=system.cpu.dcache_port
 105 mem_side=system.cpu.toL2Bus.slave[1]
 106
 107 [system.cpu.dcache.tags]
 108 type=LRU
 109 assoc=2
 110 block_size=64
 111 clk_domain=system.cpu_clk_domain
 112 eventq_index=0
 113 hit_latency=2
 114 sequential_access=false
 115 size=262144
 116
 117 [system.cpu.dstage2_mmu]
 118 type=ArmStage2MMU
 119 children=stage2_tlb
 120 eventq_index=0
 121 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 122 sys=system
 123 tlb=system.cpu.dtb
 124
 125 [system.cpu.dstage2_mmu.stage2_tlb]
 126 type=ArmTLB
 127 children=walker
 128 eventq_index=0
 129 is_stage2=true
 130 size=32
 131 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 132
 133 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 134 type=ArmTableWalker
 135 clk_domain=system.cpu_clk_domain
 136 eventq_index=0
 137 is_stage2=true
 138 num_squash_per_cycle=2
 139 sys=system
 140
 141 [system.cpu.dtb]
 142 type=ArmTLB
 143 children=walker
 144 eventq_index=0
 145 is_stage2=false
 146 size=64
 147 walker=system.cpu.dtb.walker
 148
 149 [system.cpu.dtb.walker]
 150 type=ArmTableWalker
 151 clk_domain=system.cpu_clk_domain
 152 eventq_index=0
 153 is_stage2=false
 154 num_squash_per_cycle=2
 155 sys=system
 156 port=system.cpu.toL2Bus.slave[3]
 157
 158 [system.cpu.icache]
 159 type=BaseCache
 160 children=tags
 161 addr_ranges=0:18446744073709551615
 162 assoc=2
 163 clk_domain=system.cpu_clk_domain
 164 demand_mshr_reserve=1
 165 eventq_index=0
 166 forward_snoops=true
 167 hit_latency=2
 168 is_read_only=true
 169 max_miss_count=0
 170 mshrs=4
 171 prefetch_on_access=false
 172 prefetcher=Null
 173 response_latency=2
 174 sequential_access=false
 175 size=131072
 176 system=system
 177 tags=system.cpu.icache.tags
 178 tgts_per_mshr=20
 179 write_buffers=8
 180 cpu_side=system.cpu.icache_port
 181 mem_side=system.cpu.toL2Bus.slave[0]
 182
 183 [system.cpu.icache.tags]
 184 type=LRU
 185 assoc=2
 186 block_size=64
 187 clk_domain=system.cpu_clk_domain
 188 eventq_index=0
 189 hit_latency=2
 190 sequential_access=false
 191 size=131072
 192
 193 [system.cpu.interrupts]
 194 type=ArmInterrupts
 195 eventq_index=0
 196
 197 [system.cpu.isa]
 198 type=ArmISA
 199 eventq_index=0
 200 fpsid=1090793632
 201 id_aa64afr0_el1=0
 202 id_aa64afr1_el1=0
 203 id_aa64dfr0_el1=1052678
 204 id_aa64dfr1_el1=0
 205 id_aa64isar0_el1=0
 206 id_aa64isar1_el1=0
 207 id_aa64mmfr0_el1=15728642
 208 id_aa64mmfr1_el1=0
 209 id_aa64pfr0_el1=17
 210 id_aa64pfr1_el1=0
 211 id_isar0=34607377
 212 id_isar1=34677009
 213 id_isar2=555950401
 214 id_isar3=17899825
 215 id_isar4=268501314
 216 id_isar5=0
 217 id_mmfr0=270536963
 218 id_mmfr1=0
 219 id_mmfr2=19070976
 220 id_mmfr3=34611729
 221 id_pfr0=49
 222 id_pfr1=4113
 223 midr=1091551472
 224 pmu=Null
 225 system=system
 226
 227 [system.cpu.istage2_mmu]
 228 type=ArmStage2MMU
 229 children=stage2_tlb
 230 eventq_index=0
 231 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 232 sys=system
 233 tlb=system.cpu.itb
 234
 235 [system.cpu.istage2_mmu.stage2_tlb]
 236 type=ArmTLB
 237 children=walker
 238 eventq_index=0
 239 is_stage2=true
 240 size=32
 241 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 242
 243 [system.cpu.istage2_mmu.stage2_tlb.walker]
 244 type=ArmTableWalker
 245 clk_domain=system.cpu_clk_domain
 246 eventq_index=0
 247 is_stage2=true
 248 num_squash_per_cycle=2
 249 sys=system
 250
 251 [system.cpu.itb]
 252 type=ArmTLB
 253 children=walker
 254 eventq_index=0
 255 is_stage2=false
 256 size=64
 257 walker=system.cpu.itb.walker
 258
 259 [system.cpu.itb.walker]
 260 type=ArmTableWalker
 261 clk_domain=system.cpu_clk_domain
 262 eventq_index=0
 263 is_stage2=false
 264 num_squash_per_cycle=2
 265 sys=system
 266 port=system.cpu.toL2Bus.slave[2]
 267
 268 [system.cpu.l2cache]
 269 type=BaseCache
 270 children=tags
 271 addr_ranges=0:18446744073709551615
 272 assoc=8
 273 clk_domain=system.cpu_clk_domain
 274 demand_mshr_reserve=1
 275 eventq_index=0
 276 forward_snoops=true
 277 hit_latency=20
 278 is_read_only=false
 279 max_miss_count=0
 280 mshrs=20
 281 prefetch_on_access=false
 282 prefetcher=Null
 283 response_latency=20
 284 sequential_access=false
 285 size=2097152
 286 system=system
 287 tags=system.cpu.l2cache.tags
 288 tgts_per_mshr=12
 289 write_buffers=8
 290 cpu_side=system.cpu.toL2Bus.master[0]
 291 mem_side=system.membus.slave[1]
 292
 293 [system.cpu.l2cache.tags]
 294 type=LRU
 295 assoc=8
 296 block_size=64
 297 clk_domain=system.cpu_clk_domain
 298 eventq_index=0
 299 hit_latency=20
 300 sequential_access=false
 301 size=2097152
 302
 303 [system.cpu.toL2Bus]
 304 type=CoherentXBar
 305 clk_domain=system.cpu_clk_domain
 306 eventq_index=0
 307 forward_latency=0
 308 frontend_latency=1
 309 response_latency=1
 310 snoop_filter=Null
 311 snoop_response_latency=1
 312 system=system
 313 use_default_range=false
 314 width=32
 315 master=system.cpu.l2cache.cpu_side
 316 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 317
 318 [system.cpu.tracer]
 319 type=ExeTracer
 320 eventq_index=0
 321
 322 [system.cpu.workload]
 323 type=LiveProcess
 324 cmd=perlbmk -I. -I lib mdred.makerand.pl
 325 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 326 drivers=
 327 egid=100
 328 env=
 329 errout=cerr
 330 euid=100
 331 eventq_index=0
 332 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 333 gid=100
 334 input=cin
 335 kvmInSE=false
 336 max_stack_size=67108864
 337 output=cout
 338 pid=100
 339 ppid=99
 340 simpoint=0
 341 system=system
 342 uid=100
 343 useArchPT=false
 344
 345 [system.cpu_clk_domain]
 346 type=SrcClockDomain
 347 clock=500
 348 domain_id=-1
 349 eventq_index=0
 350 init_perf_level=0
 351 voltage_domain=system.voltage_domain
 352
 353 [system.dvfs_handler]
 354 type=DVFSHandler
 355 domains=
 356 enable=false
 357 eventq_index=0
 358 sys_clk_domain=system.clk_domain
 359 transition_latency=100000000
 360
 361 [system.membus]
 362 type=CoherentXBar
 363 clk_domain=system.clk_domain
 364 eventq_index=0
 365 forward_latency=4
 366 frontend_latency=3
 367 response_latency=2
 368 snoop_filter=Null
 369 snoop_response_latency=4
 370 system=system
 371 use_default_range=false
 372 width=16
 373 master=system.physmem.port
 374 slave=system.system_port system.cpu.l2cache.mem_side
 375
 376 [system.physmem]
 377 type=SimpleMemory
 378 bandwidth=73.000000
 379 clk_domain=system.clk_domain
 380 conf_table_reported=true
 381 eventq_index=0
 382 in_addr_map=true
 383 latency=30000
 384 latency_var=0
 385 null=false
 386 range=0:134217727
 387 port=system.membus.master[0]
 388
 389 [system.voltage_domain]
 390 type=VoltageDomain
 391 eventq_index=0
 392 voltage=1.000000
 393