tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=InOrderCPU
  40 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  41 activity=0
  42 branchPred=system.cpu.branchPred
  43 cachePorts=2
  44 checker=Null
  45 clk_domain=system.cpu_clk_domain
  46 cpu_id=0
  47 div16Latency=1
  48 div16RepeatRate=1
  49 div24Latency=1
  50 div24RepeatRate=1
  51 div32Latency=1
  52 div32RepeatRate=1
  53 div8Latency=1
  54 div8RepeatRate=1
  55 do_checkpoint_insts=true
  56 do_quiesce=true
  57 do_statistics_insts=true
  58 dtb=system.cpu.dtb
  59 fetchBuffSize=4
  60 function_trace=false
  61 function_trace_start=0
  62 interrupts=system.cpu.interrupts
  63 isa=system.cpu.isa
  64 itb=system.cpu.itb
  65 max_insts_all_threads=0
  66 max_insts_any_thread=0
  67 max_loads_all_threads=0
  68 max_loads_any_thread=0
  69 memBlockSize=64
  70 multLatency=1
  71 multRepeatRate=1
  72 numThreads=1
  73 profile=0
  74 progress_interval=0
  75 simpoint_start_insts=
  76 stageTracing=false
  77 stageWidth=4
  78 switched_out=false
  79 system=system
  80 threadModel=SMT
  81 tracer=system.cpu.tracer
  82 workload=system.cpu.workload
  83 dcache_port=system.cpu.dcache.cpu_side
  84 icache_port=system.cpu.icache.cpu_side
  85
  86 [system.cpu.branchPred]
  87 type=BranchPredictor
  88 BTBEntries=4096
  89 BTBTagSize=16
  90 RASSize=16
  91 choiceCtrBits=2
  92 choicePredictorSize=8192
  93 globalCtrBits=2
  94 globalPredictorSize=8192
  95 instShiftAmt=2
  96 localCtrBits=2
  97 localHistoryTableSize=2048
  98 localPredictorSize=2048
  99 numThreads=1
 100 predType=tournament
 101
 102 [system.cpu.dcache]
 103 type=BaseCache
 104 children=tags
 105 addr_ranges=0:18446744073709551615
 106 assoc=2
 107 clk_domain=system.cpu_clk_domain
 108 forward_snoops=true
 109 hit_latency=2
 110 is_top_level=true
 111 max_miss_count=0
 112 mshrs=4
 113 prefetch_on_access=false
 114 prefetcher=Null
 115 response_latency=2
 116 size=262144
 117 system=system
 118 tags=system.cpu.dcache.tags
 119 tgts_per_mshr=20
 120 two_queue=false
 121 write_buffers=8
 122 cpu_side=system.cpu.dcache_port
 123 mem_side=system.cpu.toL2Bus.slave[1]
 124
 125 [system.cpu.dcache.tags]
 126 type=LRU
 127 assoc=2
 128 block_size=64
 129 clk_domain=system.cpu_clk_domain
 130 hit_latency=2
 131 size=262144
 132
 133 [system.cpu.dtb]
 134 type=AlphaTLB
 135 size=64
 136
 137 [system.cpu.icache]
 138 type=BaseCache
 139 children=tags
 140 addr_ranges=0:18446744073709551615
 141 assoc=2
 142 clk_domain=system.cpu_clk_domain
 143 forward_snoops=true
 144 hit_latency=2
 145 is_top_level=true
 146 max_miss_count=0
 147 mshrs=4
 148 prefetch_on_access=false
 149 prefetcher=Null
 150 response_latency=2
 151 size=131072
 152 system=system
 153 tags=system.cpu.icache.tags
 154 tgts_per_mshr=20
 155 two_queue=false
 156 write_buffers=8
 157 cpu_side=system.cpu.icache_port
 158 mem_side=system.cpu.toL2Bus.slave[0]
 159
 160 [system.cpu.icache.tags]
 161 type=LRU
 162 assoc=2
 163 block_size=64
 164 clk_domain=system.cpu_clk_domain
 165 hit_latency=2
 166 size=131072
 167
 168 [system.cpu.interrupts]
 169 type=AlphaInterrupts
 170
 171 [system.cpu.isa]
 172 type=AlphaISA
 173
 174 [system.cpu.itb]
 175 type=AlphaTLB
 176 size=48
 177
 178 [system.cpu.l2cache]
 179 type=BaseCache
 180 children=tags
 181 addr_ranges=0:18446744073709551615
 182 assoc=8
 183 clk_domain=system.cpu_clk_domain
 184 forward_snoops=true
 185 hit_latency=20
 186 is_top_level=false
 187 max_miss_count=0
 188 mshrs=20
 189 prefetch_on_access=false
 190 prefetcher=Null
 191 response_latency=20
 192 size=2097152
 193 system=system
 194 tags=system.cpu.l2cache.tags
 195 tgts_per_mshr=12
 196 two_queue=false
 197 write_buffers=8
 198 cpu_side=system.cpu.toL2Bus.master[0]
 199 mem_side=system.membus.slave[1]
 200
 201 [system.cpu.l2cache.tags]
 202 type=LRU
 203 assoc=8
 204 block_size=64
 205 clk_domain=system.cpu_clk_domain
 206 hit_latency=20
 207 size=2097152
 208
 209 [system.cpu.toL2Bus]
 210 type=CoherentBus
 211 clk_domain=system.cpu_clk_domain
 212 header_cycles=1
 213 system=system
 214 use_default_range=false
 215 width=32
 216 master=system.cpu.l2cache.cpu_side
 217 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 218
 219 [system.cpu.tracer]
 220 type=ExeTracer
 221
 222 [system.cpu.workload]
 223 type=LiveProcess
 224 cmd=vortex lendian.raw
 225 cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 226 egid=100
 227 env=
 228 errout=cerr
 229 euid=100
 230 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 231 gid=100
 232 input=cin
 233 max_stack_size=67108864
 234 output=cout
 235 pid=100
 236 ppid=99
 237 simpoint=0
 238 system=system
 239 uid=100
 240
 241 [system.cpu_clk_domain]
 242 type=SrcClockDomain
 243 clock=500
 244 voltage_domain=system.voltage_domain
 245
 246 [system.membus]
 247 type=CoherentBus
 248 clk_domain=system.clk_domain
 249 header_cycles=1
 250 system=system
 251 use_default_range=false
 252 width=8
 253 master=system.physmem.port
 254 slave=system.system_port system.cpu.l2cache.mem_side
 255
 256 [system.physmem]
 257 type=SimpleDRAM
 258 activation_limit=4
 259 addr_mapping=RaBaChCo
 260 banks_per_rank=8
 261 burst_length=8
 262 channels=1
 263 clk_domain=system.clk_domain
 264 conf_table_reported=true
 265 device_bus_width=8
 266 device_rowbuffer_size=1024
 267 devices_per_rank=8
 268 in_addr_map=true
 269 mem_sched_policy=frfcfs
 270 null=false
 271 page_policy=open
 272 range=0:134217727
 273 ranks_per_channel=2
 274 read_buffer_size=32
 275 static_backend_latency=10000
 276 static_frontend_latency=10000
 277 tBURST=5000
 278 tCL=13750
 279 tRCD=13750
 280 tREFI=7800000
 281 tRFC=300000
 282 tRP=13750
 283 tWTR=7500
 284 tXAW=40000
 285 write_buffer_size=32
 286 write_thresh_perc=70
 287 port=system.membus.master[0]
 288
 289 [system.voltage_domain]
 290 type=VoltageDomain
 291 voltage=1.000000
 292