2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.043690 # Number of seconds simulated
4 sim_ticks 43690025000 # Number of ticks simulated
5 final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 91247 # Simulator instruction rate (inst/s)
8 host_op_rate 91247 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 45127446 # Simulator tick rate (ticks/s)
10 host_mem_usage 283120 # Number of bytes of host memory used
11 host_seconds 968.15 # Real time elapsed on the host
12 sim_insts 88340673 # Number of instructions simulated
13 sim_ops 88340673 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 165515 # Number of read requests accepted
38 system.physmem.writeReqs 113997 # Number of write requests accepted
39 system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue
40 system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue
41 system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM
42 system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue
43 system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM
44 system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side
45 system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side
46 system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue
47 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
48 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
49 system.physmem.perBankRdBursts::0 10379 # Per bank write bursts
50 system.physmem.perBankRdBursts::1 10437 # Per bank write bursts
51 system.physmem.perBankRdBursts::2 10256 # Per bank write bursts
52 system.physmem.perBankRdBursts::3 10015 # Per bank write bursts
53 system.physmem.perBankRdBursts::4 10350 # Per bank write bursts
54 system.physmem.perBankRdBursts::5 10362 # Per bank write bursts
55 system.physmem.perBankRdBursts::6 9796 # Per bank write bursts
56 system.physmem.perBankRdBursts::7 10273 # Per bank write bursts
57 system.physmem.perBankRdBursts::8 10509 # Per bank write bursts
58 system.physmem.perBankRdBursts::9 10590 # Per bank write bursts
59 system.physmem.perBankRdBursts::10 10479 # Per bank write bursts
60 system.physmem.perBankRdBursts::11 10188 # Per bank write bursts
61 system.physmem.perBankRdBursts::12 10237 # Per bank write bursts
62 system.physmem.perBankRdBursts::13 10581 # Per bank write bursts
63 system.physmem.perBankRdBursts::14 10468 # Per bank write bursts
64 system.physmem.perBankRdBursts::15 10593 # Per bank write bursts
65 system.physmem.perBankWrBursts::0 7081 # Per bank write bursts
66 system.physmem.perBankWrBursts::1 7259 # Per bank write bursts
67 system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
68 system.physmem.perBankWrBursts::3 6998 # Per bank write bursts
69 system.physmem.perBankWrBursts::4 7125 # Per bank write bursts
70 system.physmem.perBankWrBursts::5 7173 # Per bank write bursts
71 system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
72 system.physmem.perBankWrBursts::7 7091 # Per bank write bursts
73 system.physmem.perBankWrBursts::8 7219 # Per bank write bursts
74 system.physmem.perBankWrBursts::9 6938 # Per bank write bursts
75 system.physmem.perBankWrBursts::10 7084 # Per bank write bursts
76 system.physmem.perBankWrBursts::11 6989 # Per bank write bursts
77 system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
78 system.physmem.perBankWrBursts::13 7284 # Per bank write bursts
79 system.physmem.perBankWrBursts::14 7282 # Per bank write bursts
80 system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
81 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
82 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
83 system.physmem.totGap 43690004000 # Total gap between requests
84 system.physmem.readPktSize::0 0 # Read request sizes (log2)
85 system.physmem.readPktSize::1 0 # Read request sizes (log2)
86 system.physmem.readPktSize::2 0 # Read request sizes (log2)
87 system.physmem.readPktSize::3 0 # Read request sizes (log2)
88 system.physmem.readPktSize::4 0 # Read request sizes (log2)
89 system.physmem.readPktSize::5 0 # Read request sizes (log2)
90 system.physmem.readPktSize::6 165515 # Read request sizes (log2)
91 system.physmem.writePktSize::0 0 # Write request sizes (log2)
92 system.physmem.writePktSize::1 0 # Write request sizes (log2)
93 system.physmem.writePktSize::2 0 # Write request sizes (log2)
94 system.physmem.writePktSize::3 0 # Write request sizes (log2)
95 system.physmem.writePktSize::4 0 # Write request sizes (log2)
96 system.physmem.writePktSize::5 0 # Write request sizes (log2)
97 system.physmem.writePktSize::6 113997 # Write request sizes (log2)
98 system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
130 system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
162 system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation
293 system.physmem.totQLat 6031819750 # Total ticks spent queuing
294 system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM
295 system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers
296 system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks
297 system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst
298 system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst
299 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
300 system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst
301 system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s
302 system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s
303 system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s
304 system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s
305 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
306 system.physmem.busUtil 3.20 # Data bus utilization in percentage
307 system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads
308 system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes
309 system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing
310 system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing
311 system.physmem.readRowHits 151507 # Number of row buffer hits during reads
312 system.physmem.writeRowHits 76598 # Number of row buffer hits during writes
313 system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads
314 system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes
315 system.physmem.avgGap 156308.15 # Average gap between requests
316 system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
317 system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state
318 system.membus.throughput 409447420 # Throughput (bytes/s)
319 system.membus.trans_dist::ReadReq 34625 # Transaction distribution
320 system.membus.trans_dist::ReadResp 34625 # Transaction distribution
321 system.membus.trans_dist::Writeback 113997 # Transaction distribution
322 system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
323 system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
324 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes)
325 system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes)
326 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes)
327 system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
328 system.membus.data_through_bus 17888768 # Total data (bytes)
329 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
330 system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks)
331 system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
332 system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks)
333 system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
334 system.cpu.branchPred.lookups 18742723 # Number of BP lookups
335 system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted
336 system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect
337 system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups
338 system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits
339 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
340 system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage
341 system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target.
342 system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
343 system.cpu.dtb.fetch_hits 0 # ITB hits
344 system.cpu.dtb.fetch_misses 0 # ITB misses
345 system.cpu.dtb.fetch_acv 0 # ITB acv
346 system.cpu.dtb.fetch_accesses 0 # ITB accesses
347 system.cpu.dtb.read_hits 20277713 # DTB read hits
348 system.cpu.dtb.read_misses 90148 # DTB read misses
349 system.cpu.dtb.read_acv 0 # DTB read access violations
350 system.cpu.dtb.read_accesses 20367861 # DTB read accesses
351 system.cpu.dtb.write_hits 14728970 # DTB write hits
352 system.cpu.dtb.write_misses 7252 # DTB write misses
353 system.cpu.dtb.write_acv 0 # DTB write access violations
354 system.cpu.dtb.write_accesses 14736222 # DTB write accesses
355 system.cpu.dtb.data_hits 35006683 # DTB hits
356 system.cpu.dtb.data_misses 97400 # DTB misses
357 system.cpu.dtb.data_acv 0 # DTB access violations
358 system.cpu.dtb.data_accesses 35104083 # DTB accesses
359 system.cpu.itb.fetch_hits 12367758 # ITB hits
360 system.cpu.itb.fetch_misses 11021 # ITB misses
361 system.cpu.itb.fetch_acv 0 # ITB acv
362 system.cpu.itb.fetch_accesses 12378779 # ITB accesses
363 system.cpu.itb.read_hits 0 # DTB read hits
364 system.cpu.itb.read_misses 0 # DTB read misses
365 system.cpu.itb.read_acv 0 # DTB read access violations
366 system.cpu.itb.read_accesses 0 # DTB read accesses
367 system.cpu.itb.write_hits 0 # DTB write hits
368 system.cpu.itb.write_misses 0 # DTB write misses
369 system.cpu.itb.write_acv 0 # DTB write access violations
370 system.cpu.itb.write_accesses 0 # DTB write accesses
371 system.cpu.itb.data_hits 0 # DTB hits
372 system.cpu.itb.data_misses 0 # DTB misses
373 system.cpu.itb.data_acv 0 # DTB access violations
374 system.cpu.itb.data_accesses 0 # DTB accesses
375 system.cpu.workload.num_syscalls 4583 # Number of system calls
376 system.cpu.numCycles 87380051 # number of cpu cycles simulated
377 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
378 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
379 system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True).
380 system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False).
381 system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File
382 system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
383 system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File
384 system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File
385 system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
386 system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File
387 system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic
388 system.cpu.agen_unit.agens 35060070 # Number of Address Generations
389 system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken.
390 system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken).
391 system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted
392 system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted
393 system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts
394 system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed.
395 system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
396 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
397 system.cpu.contextSwitches 1 # Number of context switches
398 system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
399 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
400 system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself
401 system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed
402 system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed.
403 system.cpu.activity 79.624156 # Percentage of cycles cpu is active
404 system.cpu.comLoads 20276638 # Number of Load instructions committed
405 system.cpu.comStores 14613377 # Number of Store instructions committed
406 system.cpu.comBranches 13754477 # Number of Branches instructions committed
407 system.cpu.comNops 8748916 # Number of Nop instructions committed
408 system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
409 system.cpu.comInts 30791227 # Number of Integer instructions committed
410 system.cpu.comFloats 151453 # Number of Floating Point instructions committed
411 system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
412 system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
413 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
414 system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
415 system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread)
416 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
417 system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads
418 system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread)
419 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
420 system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads
421 system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed.
422 system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed.
423 system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts).
424 system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed.
425 system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed.
426 system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts).
427 system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed.
428 system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed.
429 system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts).
430 system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed.
431 system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed.
432 system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts).
433 system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed.
434 system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed.
435 system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts).
436 system.cpu.icache.tags.replacements 84371 # number of replacements
437 system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use
438 system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks.
439 system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
440 system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks.
441 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
442 system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor
443 system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy
444 system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy
445 system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits
446 system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits
447 system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits
448 system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits
449 system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits
450 system.cpu.icache.overall_hits::total 12250505 # number of overall hits
451 system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses
452 system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses
453 system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses
454 system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses
455 system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses
456 system.cpu.icache.overall_misses::total 117242 # number of overall misses
457 system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles
458 system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles
459 system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles
460 system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles
461 system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles
462 system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles
463 system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses)
464 system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses)
465 system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses
466 system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses
467 system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses
468 system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses
469 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses
470 system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses
471 system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses
472 system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses
473 system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses
474 system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses
475 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency
476 system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency
477 system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency
478 system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency
479 system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency
480 system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency
481 system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked
482 system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
483 system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
484 system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
485 system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked
486 system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked
487 system.cpu.icache.fast_writes 0 # number of fast writes performed
488 system.cpu.icache.cache_copies 0 # number of cache copies performed
489 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits
490 system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits
491 system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits
492 system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits
493 system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits
494 system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits
495 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses
496 system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses
497 system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses
498 system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses
499 system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses
500 system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses
501 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles
502 system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles
503 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles
504 system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles
505 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles
506 system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles
507 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses
508 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses
509 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses
510 system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses
511 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses
512 system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses
513 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency
514 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency
515 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency
516 system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency
517 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency
518 system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency
519 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
520 system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s)
521 system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution
522 system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution
523 system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution
524 system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
525 system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
526 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes)
527 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes)
528 system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes)
529 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes)
530 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes)
531 system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes)
532 system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes)
533 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
534 system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks)
535 system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
536 system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks)
537 system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
538 system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks)
539 system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
540 system.cpu.l2cache.tags.replacements 131591 # number of replacements
541 system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use
542 system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks.
543 system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
544 system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks.
545 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
546 system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor
547 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor
548 system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor
549 system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy
550 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy
551 system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy
552 system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy
553 system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits
554 system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits
555 system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits
556 system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits
557 system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits
558 system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
559 system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
560 system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits
561 system.cpu.l2cache.demand_hits::cpu.data 45934 # number of demand (read+write) hits
562 system.cpu.l2cache.demand_hits::total 125248 # number of demand (read+write) hits
563 system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits
564 system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits
565 system.cpu.l2cache.overall_hits::total 125248 # number of overall hits
566 system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses
567 system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses
568 system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses
569 system.cpu.l2cache.ReadExReq_misses::cpu.data 130890 # number of ReadExReq misses
570 system.cpu.l2cache.ReadExReq_misses::total 130890 # number of ReadExReq misses
571 system.cpu.l2cache.demand_misses::cpu.inst 7103 # number of demand (read+write) misses
572 system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
573 system.cpu.l2cache.demand_misses::total 165515 # number of demand (read+write) misses
574 system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses
575 system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
576 system.cpu.l2cache.overall_misses::total 165515 # number of overall misses
577 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles
578 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles
579 system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles
580 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980250 # number of ReadExReq miss cycles
581 system.cpu.l2cache.ReadExReq_miss_latency::total 13452980250 # number of ReadExReq miss cycles
582 system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles
583 system.cpu.l2cache.demand_miss_latency::cpu.data 15496302250 # number of demand (read+write) miss cycles
584 system.cpu.l2cache.demand_miss_latency::total 16046428000 # number of demand (read+write) miss cycles
585 system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles
586 system.cpu.l2cache.overall_miss_latency::cpu.data 15496302250 # number of overall miss cycles
587 system.cpu.l2cache.overall_miss_latency::total 16046428000 # number of overall miss cycles
588 system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses)
589 system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
590 system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses)
591 system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses)
592 system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses)
593 system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses)
594 system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses)
595 system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses
596 system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses
597 system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses
598 system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses
599 system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses
600 system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses
601 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses
602 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses
603 system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses
604 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
605 system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
606 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses
607 system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses
608 system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses
609 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses
610 system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses
611 system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses
612 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency
613 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency
614 system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency
615 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency
616 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency
617 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency
618 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency
619 system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency
620 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency
621 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency
622 system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency
623 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
624 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
625 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
626 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
627 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
628 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
629 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
630 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
631 system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
632 system.cpu.l2cache.writebacks::total 113997 # number of writebacks
633 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses
634 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27522 # number of ReadReq MSHR misses
635 system.cpu.l2cache.ReadReq_mshr_misses::total 34625 # number of ReadReq MSHR misses
636 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130890 # number of ReadExReq MSHR misses
637 system.cpu.l2cache.ReadExReq_mshr_misses::total 130890 # number of ReadExReq MSHR misses
638 system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses
639 system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
640 system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses
641 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses
642 system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
643 system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses
644 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles
645 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # number of ReadReq MSHR miss cycles
646 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156502250 # number of ReadReq MSHR miss cycles
647 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11851363750 # number of ReadExReq MSHR miss cycles
648 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11851363750 # number of ReadExReq MSHR miss cycles
649 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460945750 # number of demand (read+write) MSHR miss cycles
650 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13546920250 # number of demand (read+write) MSHR miss cycles
651 system.cpu.l2cache.demand_mshr_miss_latency::total 14007866000 # number of demand (read+write) MSHR miss cycles
652 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460945750 # number of overall MSHR miss cycles
653 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13546920250 # number of overall MSHR miss cycles
654 system.cpu.l2cache.overall_mshr_miss_latency::total 14007866000 # number of overall MSHR miss cycles
655 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses
656 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses
657 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses
658 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
659 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
660 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses
661 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses
662 system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses
663 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses
664 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses
665 system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses
666 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency
667 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency
668 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency
669 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency
670 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency
671 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency
672 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency
673 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency
674 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency
675 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency
676 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency
677 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
678 system.cpu.dcache.tags.replacements 200250 # number of replacements
679 system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use
680 system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks.
681 system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks.
682 system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks.
683 system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit.
684 system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor
685 system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy
686 system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy
687 system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits
688 system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits
689 system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits
690 system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits
691 system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits
692 system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits
693 system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits
694 system.cpu.dcache.overall_hits::total 33754883 # number of overall hits
695 system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses
696 system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses
697 system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses
698 system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses
699 system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses
700 system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses
701 system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses
702 system.cpu.dcache.overall_misses::total 1135132 # number of overall misses
703 system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles
704 system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles
705 system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles
706 system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles
707 system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles
708 system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles
709 system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles
710 system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles
711 system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
712 system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
713 system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
714 system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
715 system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
716 system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
717 system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
718 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
719 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses
720 system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses
721 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses
722 system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses
723 system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses
724 system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
725 system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
726 system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
727 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency
728 system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency
729 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency
730 system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency
731 system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency
732 system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency
733 system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency
734 system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency
735 system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked
736 system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked
737 system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked
738 system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
739 system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked
740 system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked
741 system.cpu.dcache.fast_writes 0 # number of fast writes performed
742 system.cpu.dcache.cache_copies 0 # number of cache copies performed
743 system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks
744 system.cpu.dcache.writebacks::total 168351 # number of writebacks
745 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits
746 system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits
747 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits
748 system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits
749 system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits
750 system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits
751 system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits
752 system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits
753 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
754 system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
755 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
756 system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
757 system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses
758 system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses
759 system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses
760 system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses
761 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles
762 system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles
763 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles
764 system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles
765 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles
766 system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles
767 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles
768 system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles
769 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
770 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
771 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
772 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
773 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
774 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
775 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
776 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
777 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency
778 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency
779 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency
780 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency
781 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency
782 system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency
783 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency
784 system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency
785 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
787 ---------- End Simulation Statistics ----------
projects / gem5.git / blob