tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=
  27 memories=system.physmem
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[0]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 clock=1000
  51 domain_id=-1
  52 eventq_index=0
  53 init_perf_level=0
  54 voltage_domain=system.voltage_domain
  55
  56 [system.cpu]
  57 type=MinorCPU
  58 children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
  59 branchPred=system.cpu.branchPred
  60 checker=Null
  61 clk_domain=system.cpu_clk_domain
  62 cpu_id=0
  63 decodeCycleInput=true
  64 decodeInputBufferSize=3
  65 decodeInputWidth=2
  66 decodeToExecuteForwardDelay=1
  67 default_p_state=UNDEFINED
  68 do_checkpoint_insts=true
  69 do_quiesce=true
  70 do_statistics_insts=true
  71 dtb=system.cpu.dtb
  72 enableIdling=true
  73 eventq_index=0
  74 executeAllowEarlyMemoryIssue=true
  75 executeBranchDelay=1
  76 executeCommitLimit=2
  77 executeCycleInput=true
  78 executeFuncUnits=system.cpu.executeFuncUnits
  79 executeInputBufferSize=7
  80 executeInputWidth=2
  81 executeIssueLimit=2
  82 executeLSQMaxStoreBufferStoresPerCycle=2
  83 executeLSQRequestsQueueSize=1
  84 executeLSQStoreBufferSize=5
  85 executeLSQTransfersQueueSize=2
  86 executeMaxAccessesInMemory=2
  87 executeMemoryCommitLimit=1
  88 executeMemoryIssueLimit=1
  89 executeMemoryWidth=0
  90 executeSetTraceTimeOnCommit=true
  91 executeSetTraceTimeOnIssue=false
  92 fetch1FetchLimit=1
  93 fetch1LineSnapWidth=0
  94 fetch1LineWidth=0
  95 fetch1ToFetch2BackwardDelay=1
  96 fetch1ToFetch2ForwardDelay=1
  97 fetch2CycleInput=true
  98 fetch2InputBufferSize=2
  99 fetch2ToDecodeForwardDelay=1
 100 function_trace=false
 101 function_trace_start=0
 102 interrupts=system.cpu.interrupts
 103 isa=system.cpu.isa
 104 itb=system.cpu.itb
 105 max_insts_all_threads=0
 106 max_insts_any_thread=0
 107 max_loads_all_threads=0
 108 max_loads_any_thread=0
 109 numThreads=1
 110 p_state_clk_gate_bins=20
 111 p_state_clk_gate_max=1000000000000
 112 p_state_clk_gate_min=1000
 113 power_model=Null
 114 profile=0
 115 progress_interval=0
 116 simpoint_start_insts=
 117 socket_id=0
 118 switched_out=false
 119 system=system
 120 threadPolicy=RoundRobin
 121 tracer=system.cpu.tracer
 122 workload=system.cpu.workload
 123 dcache_port=system.cpu.dcache.cpu_side
 124 icache_port=system.cpu.icache.cpu_side
 125
 126 [system.cpu.branchPred]
 127 type=TournamentBP
 128 BTBEntries=4096
 129 BTBTagSize=16
 130 RASSize=16
 131 choiceCtrBits=2
 132 choicePredictorSize=8192
 133 eventq_index=0
 134 globalCtrBits=2
 135 globalPredictorSize=8192
 136 indirectHashGHR=true
 137 indirectHashTargets=true
 138 indirectPathLength=3
 139 indirectSets=256
 140 indirectTagSize=16
 141 indirectWays=2
 142 instShiftAmt=2
 143 localCtrBits=2
 144 localHistoryTableSize=2048
 145 localPredictorSize=2048
 146 numThreads=1
 147 useIndirect=true
 148
 149 [system.cpu.dcache]
 150 type=Cache
 151 children=tags
 152 addr_ranges=0:18446744073709551615:0:0:0:0
 153 assoc=2
 154 clk_domain=system.cpu_clk_domain
 155 clusivity=mostly_incl
 156 default_p_state=UNDEFINED
 157 demand_mshr_reserve=1
 158 eventq_index=0
 159 hit_latency=2
 160 is_read_only=false
 161 max_miss_count=0
 162 mshrs=4
 163 p_state_clk_gate_bins=20
 164 p_state_clk_gate_max=1000000000000
 165 p_state_clk_gate_min=1000
 166 power_model=Null
 167 prefetch_on_access=false
 168 prefetcher=Null
 169 response_latency=2
 170 sequential_access=false
 171 size=262144
 172 system=system
 173 tags=system.cpu.dcache.tags
 174 tgts_per_mshr=20
 175 write_buffers=8
 176 writeback_clean=false
 177 cpu_side=system.cpu.dcache_port
 178 mem_side=system.cpu.toL2Bus.slave[1]
 179
 180 [system.cpu.dcache.tags]
 181 type=LRU
 182 assoc=2
 183 block_size=64
 184 clk_domain=system.cpu_clk_domain
 185 default_p_state=UNDEFINED
 186 eventq_index=0
 187 hit_latency=2
 188 p_state_clk_gate_bins=20
 189 p_state_clk_gate_max=1000000000000
 190 p_state_clk_gate_min=1000
 191 power_model=Null
 192 sequential_access=false
 193 size=262144
 194
 195 [system.cpu.dtb]
 196 type=AlphaTLB
 197 eventq_index=0
 198 size=64
 199
 200 [system.cpu.executeFuncUnits]
 201 type=MinorFUPool
 202 children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
 203 eventq_index=0
 204 funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
 205
 206 [system.cpu.executeFuncUnits.funcUnits0]
 207 type=MinorFU
 208 children=opClasses timings
 209 cantForwardFromFUIndices=
 210 eventq_index=0
 211 issueLat=1
 212 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
 213 opLat=3
 214 timings=system.cpu.executeFuncUnits.funcUnits0.timings
 215
 216 [system.cpu.executeFuncUnits.funcUnits0.opClasses]
 217 type=MinorOpClassSet
 218 children=opClasses
 219 eventq_index=0
 220 opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
 221
 222 [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
 223 type=MinorOpClass
 224 eventq_index=0
 225 opClass=IntAlu
 226
 227 [system.cpu.executeFuncUnits.funcUnits0.timings]
 228 type=MinorFUTiming
 229 children=opClasses
 230 description=Int
 231 eventq_index=0
 232 extraAssumedLat=0
 233 extraCommitLat=0
 234 extraCommitLatExpr=Null
 235 mask=0
 236 match=0
 237 opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
 238 srcRegsRelativeLats=2
 239 suppress=false
 240
 241 [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
 242 type=MinorOpClassSet
 243 eventq_index=0
 244 opClasses=
 245
 246 [system.cpu.executeFuncUnits.funcUnits1]
 247 type=MinorFU
 248 children=opClasses timings
 249 cantForwardFromFUIndices=
 250 eventq_index=0
 251 issueLat=1
 252 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
 253 opLat=3
 254 timings=system.cpu.executeFuncUnits.funcUnits1.timings
 255
 256 [system.cpu.executeFuncUnits.funcUnits1.opClasses]
 257 type=MinorOpClassSet
 258 children=opClasses
 259 eventq_index=0
 260 opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
 261
 262 [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
 263 type=MinorOpClass
 264 eventq_index=0
 265 opClass=IntAlu
 266
 267 [system.cpu.executeFuncUnits.funcUnits1.timings]
 268 type=MinorFUTiming
 269 children=opClasses
 270 description=Int
 271 eventq_index=0
 272 extraAssumedLat=0
 273 extraCommitLat=0
 274 extraCommitLatExpr=Null
 275 mask=0
 276 match=0
 277 opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
 278 srcRegsRelativeLats=2
 279 suppress=false
 280
 281 [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
 282 type=MinorOpClassSet
 283 eventq_index=0
 284 opClasses=
 285
 286 [system.cpu.executeFuncUnits.funcUnits2]
 287 type=MinorFU
 288 children=opClasses timings
 289 cantForwardFromFUIndices=
 290 eventq_index=0
 291 issueLat=1
 292 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
 293 opLat=3
 294 timings=system.cpu.executeFuncUnits.funcUnits2.timings
 295
 296 [system.cpu.executeFuncUnits.funcUnits2.opClasses]
 297 type=MinorOpClassSet
 298 children=opClasses
 299 eventq_index=0
 300 opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
 301
 302 [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
 303 type=MinorOpClass
 304 eventq_index=0
 305 opClass=IntMult
 306
 307 [system.cpu.executeFuncUnits.funcUnits2.timings]
 308 type=MinorFUTiming
 309 children=opClasses
 310 description=Mul
 311 eventq_index=0
 312 extraAssumedLat=0
 313 extraCommitLat=0
 314 extraCommitLatExpr=Null
 315 mask=0
 316 match=0
 317 opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
 318 srcRegsRelativeLats=0
 319 suppress=false
 320
 321 [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
 322 type=MinorOpClassSet
 323 eventq_index=0
 324 opClasses=
 325
 326 [system.cpu.executeFuncUnits.funcUnits3]
 327 type=MinorFU
 328 children=opClasses
 329 cantForwardFromFUIndices=
 330 eventq_index=0
 331 issueLat=9
 332 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
 333 opLat=9
 334 timings=
 335
 336 [system.cpu.executeFuncUnits.funcUnits3.opClasses]
 337 type=MinorOpClassSet
 338 children=opClasses
 339 eventq_index=0
 340 opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
 341
 342 [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
 343 type=MinorOpClass
 344 eventq_index=0
 345 opClass=IntDiv
 346
 347 [system.cpu.executeFuncUnits.funcUnits4]
 348 type=MinorFU
 349 children=opClasses timings
 350 cantForwardFromFUIndices=
 351 eventq_index=0
 352 issueLat=1
 353 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
 354 opLat=6
 355 timings=system.cpu.executeFuncUnits.funcUnits4.timings
 356
 357 [system.cpu.executeFuncUnits.funcUnits4.opClasses]
 358 type=MinorOpClassSet
 359 children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
 360 eventq_index=0
 361 opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
 362
 363 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
 364 type=MinorOpClass
 365 eventq_index=0
 366 opClass=FloatAdd
 367
 368 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
 369 type=MinorOpClass
 370 eventq_index=0
 371 opClass=FloatCmp
 372
 373 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
 374 type=MinorOpClass
 375 eventq_index=0
 376 opClass=FloatCvt
 377
 378 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
 379 type=MinorOpClass
 380 eventq_index=0
 381 opClass=FloatMult
 382
 383 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
 384 type=MinorOpClass
 385 eventq_index=0
 386 opClass=FloatDiv
 387
 388 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
 389 type=MinorOpClass
 390 eventq_index=0
 391 opClass=FloatSqrt
 392
 393 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
 394 type=MinorOpClass
 395 eventq_index=0
 396 opClass=SimdAdd
 397
 398 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
 399 type=MinorOpClass
 400 eventq_index=0
 401 opClass=SimdAddAcc
 402
 403 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
 404 type=MinorOpClass
 405 eventq_index=0
 406 opClass=SimdAlu
 407
 408 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
 409 type=MinorOpClass
 410 eventq_index=0
 411 opClass=SimdCmp
 412
 413 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
 414 type=MinorOpClass
 415 eventq_index=0
 416 opClass=SimdCvt
 417
 418 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
 419 type=MinorOpClass
 420 eventq_index=0
 421 opClass=SimdMisc
 422
 423 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
 424 type=MinorOpClass
 425 eventq_index=0
 426 opClass=SimdMult
 427
 428 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
 429 type=MinorOpClass
 430 eventq_index=0
 431 opClass=SimdMultAcc
 432
 433 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
 434 type=MinorOpClass
 435 eventq_index=0
 436 opClass=SimdShift
 437
 438 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
 439 type=MinorOpClass
 440 eventq_index=0
 441 opClass=SimdShiftAcc
 442
 443 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
 444 type=MinorOpClass
 445 eventq_index=0
 446 opClass=SimdSqrt
 447
 448 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
 449 type=MinorOpClass
 450 eventq_index=0
 451 opClass=SimdFloatAdd
 452
 453 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
 454 type=MinorOpClass
 455 eventq_index=0
 456 opClass=SimdFloatAlu
 457
 458 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
 459 type=MinorOpClass
 460 eventq_index=0
 461 opClass=SimdFloatCmp
 462
 463 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
 464 type=MinorOpClass
 465 eventq_index=0
 466 opClass=SimdFloatCvt
 467
 468 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
 469 type=MinorOpClass
 470 eventq_index=0
 471 opClass=SimdFloatDiv
 472
 473 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
 474 type=MinorOpClass
 475 eventq_index=0
 476 opClass=SimdFloatMisc
 477
 478 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
 479 type=MinorOpClass
 480 eventq_index=0
 481 opClass=SimdFloatMult
 482
 483 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
 484 type=MinorOpClass
 485 eventq_index=0
 486 opClass=SimdFloatMultAcc
 487
 488 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
 489 type=MinorOpClass
 490 eventq_index=0
 491 opClass=SimdFloatSqrt
 492
 493 [system.cpu.executeFuncUnits.funcUnits4.timings]
 494 type=MinorFUTiming
 495 children=opClasses
 496 description=FloatSimd
 497 eventq_index=0
 498 extraAssumedLat=0
 499 extraCommitLat=0
 500 extraCommitLatExpr=Null
 501 mask=0
 502 match=0
 503 opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
 504 srcRegsRelativeLats=2
 505 suppress=false
 506
 507 [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
 508 type=MinorOpClassSet
 509 eventq_index=0
 510 opClasses=
 511
 512 [system.cpu.executeFuncUnits.funcUnits5]
 513 type=MinorFU
 514 children=opClasses timings
 515 cantForwardFromFUIndices=
 516 eventq_index=0
 517 issueLat=1
 518 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
 519 opLat=1
 520 timings=system.cpu.executeFuncUnits.funcUnits5.timings
 521
 522 [system.cpu.executeFuncUnits.funcUnits5.opClasses]
 523 type=MinorOpClassSet
 524 children=opClasses0 opClasses1
 525 eventq_index=0
 526 opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
 527
 528 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
 529 type=MinorOpClass
 530 eventq_index=0
 531 opClass=MemRead
 532
 533 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
 534 type=MinorOpClass
 535 eventq_index=0
 536 opClass=MemWrite
 537
 538 [system.cpu.executeFuncUnits.funcUnits5.timings]
 539 type=MinorFUTiming
 540 children=opClasses
 541 description=Mem
 542 eventq_index=0
 543 extraAssumedLat=2
 544 extraCommitLat=0
 545 extraCommitLatExpr=Null
 546 mask=0
 547 match=0
 548 opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
 549 srcRegsRelativeLats=1
 550 suppress=false
 551
 552 [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
 553 type=MinorOpClassSet
 554 eventq_index=0
 555 opClasses=
 556
 557 [system.cpu.executeFuncUnits.funcUnits6]
 558 type=MinorFU
 559 children=opClasses
 560 cantForwardFromFUIndices=
 561 eventq_index=0
 562 issueLat=1
 563 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
 564 opLat=1
 565 timings=
 566
 567 [system.cpu.executeFuncUnits.funcUnits6.opClasses]
 568 type=MinorOpClassSet
 569 children=opClasses0 opClasses1
 570 eventq_index=0
 571 opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
 572
 573 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
 574 type=MinorOpClass
 575 eventq_index=0
 576 opClass=IprAccess
 577
 578 [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
 579 type=MinorOpClass
 580 eventq_index=0
 581 opClass=InstPrefetch
 582
 583 [system.cpu.icache]
 584 type=Cache
 585 children=tags
 586 addr_ranges=0:18446744073709551615:0:0:0:0
 587 assoc=2
 588 clk_domain=system.cpu_clk_domain
 589 clusivity=mostly_incl
 590 default_p_state=UNDEFINED
 591 demand_mshr_reserve=1
 592 eventq_index=0
 593 hit_latency=2
 594 is_read_only=true
 595 max_miss_count=0
 596 mshrs=4
 597 p_state_clk_gate_bins=20
 598 p_state_clk_gate_max=1000000000000
 599 p_state_clk_gate_min=1000
 600 power_model=Null
 601 prefetch_on_access=false
 602 prefetcher=Null
 603 response_latency=2
 604 sequential_access=false
 605 size=131072
 606 system=system
 607 tags=system.cpu.icache.tags
 608 tgts_per_mshr=20
 609 write_buffers=8
 610 writeback_clean=true
 611 cpu_side=system.cpu.icache_port
 612 mem_side=system.cpu.toL2Bus.slave[0]
 613
 614 [system.cpu.icache.tags]
 615 type=LRU
 616 assoc=2
 617 block_size=64
 618 clk_domain=system.cpu_clk_domain
 619 default_p_state=UNDEFINED
 620 eventq_index=0
 621 hit_latency=2
 622 p_state_clk_gate_bins=20
 623 p_state_clk_gate_max=1000000000000
 624 p_state_clk_gate_min=1000
 625 power_model=Null
 626 sequential_access=false
 627 size=131072
 628
 629 [system.cpu.interrupts]
 630 type=AlphaInterrupts
 631 eventq_index=0
 632
 633 [system.cpu.isa]
 634 type=AlphaISA
 635 eventq_index=0
 636 system=system
 637
 638 [system.cpu.itb]
 639 type=AlphaTLB
 640 eventq_index=0
 641 size=48
 642
 643 [system.cpu.l2cache]
 644 type=Cache
 645 children=tags
 646 addr_ranges=0:18446744073709551615:0:0:0:0
 647 assoc=8
 648 clk_domain=system.cpu_clk_domain
 649 clusivity=mostly_incl
 650 default_p_state=UNDEFINED
 651 demand_mshr_reserve=1
 652 eventq_index=0
 653 hit_latency=20
 654 is_read_only=false
 655 max_miss_count=0
 656 mshrs=20
 657 p_state_clk_gate_bins=20
 658 p_state_clk_gate_max=1000000000000
 659 p_state_clk_gate_min=1000
 660 power_model=Null
 661 prefetch_on_access=false
 662 prefetcher=Null
 663 response_latency=20
 664 sequential_access=false
 665 size=2097152
 666 system=system
 667 tags=system.cpu.l2cache.tags
 668 tgts_per_mshr=12
 669 write_buffers=8
 670 writeback_clean=false
 671 cpu_side=system.cpu.toL2Bus.master[0]
 672 mem_side=system.membus.slave[1]
 673
 674 [system.cpu.l2cache.tags]
 675 type=LRU
 676 assoc=8
 677 block_size=64
 678 clk_domain=system.cpu_clk_domain
 679 default_p_state=UNDEFINED
 680 eventq_index=0
 681 hit_latency=20
 682 p_state_clk_gate_bins=20
 683 p_state_clk_gate_max=1000000000000
 684 p_state_clk_gate_min=1000
 685 power_model=Null
 686 sequential_access=false
 687 size=2097152
 688
 689 [system.cpu.toL2Bus]
 690 type=CoherentXBar
 691 children=snoop_filter
 692 clk_domain=system.cpu_clk_domain
 693 default_p_state=UNDEFINED
 694 eventq_index=0
 695 forward_latency=0
 696 frontend_latency=1
 697 p_state_clk_gate_bins=20
 698 p_state_clk_gate_max=1000000000000
 699 p_state_clk_gate_min=1000
 700 point_of_coherency=false
 701 power_model=Null
 702 response_latency=1
 703 snoop_filter=system.cpu.toL2Bus.snoop_filter
 704 snoop_response_latency=1
 705 system=system
 706 use_default_range=false
 707 width=32
 708 master=system.cpu.l2cache.cpu_side
 709 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 710
 711 [system.cpu.toL2Bus.snoop_filter]
 712 type=SnoopFilter
 713 eventq_index=0
 714 lookup_latency=0
 715 max_capacity=8388608
 716 system=system
 717
 718 [system.cpu.tracer]
 719 type=ExeTracer
 720 eventq_index=0
 721
 722 [system.cpu.workload]
 723 type=LiveProcess
 724 cmd=vortex lendian.raw
 725 cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing
 726 drivers=
 727 egid=100
 728 env=
 729 errout=cerr
 730 euid=100
 731 eventq_index=0
 732 executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
 733 gid=100
 734 input=cin
 735 kvmInSE=false
 736 max_stack_size=67108864
 737 output=cout
 738 pid=100
 739 ppid=99
 740 simpoint=0
 741 system=system
 742 uid=100
 743 useArchPT=false
 744
 745 [system.cpu_clk_domain]
 746 type=SrcClockDomain
 747 clock=500
 748 domain_id=-1
 749 eventq_index=0
 750 init_perf_level=0
 751 voltage_domain=system.voltage_domain
 752
 753 [system.dvfs_handler]
 754 type=DVFSHandler
 755 domains=
 756 enable=false
 757 eventq_index=0
 758 sys_clk_domain=system.clk_domain
 759 transition_latency=100000000
 760
 761 [system.membus]
 762 type=CoherentXBar
 763 children=snoop_filter
 764 clk_domain=system.clk_domain
 765 default_p_state=UNDEFINED
 766 eventq_index=0
 767 forward_latency=4
 768 frontend_latency=3
 769 p_state_clk_gate_bins=20
 770 p_state_clk_gate_max=1000000000000
 771 p_state_clk_gate_min=1000
 772 point_of_coherency=true
 773 power_model=Null
 774 response_latency=2
 775 snoop_filter=system.membus.snoop_filter
 776 snoop_response_latency=4
 777 system=system
 778 use_default_range=false
 779 width=16
 780 master=system.physmem.port
 781 slave=system.system_port system.cpu.l2cache.mem_side
 782
 783 [system.membus.snoop_filter]
 784 type=SnoopFilter
 785 eventq_index=0
 786 lookup_latency=1
 787 max_capacity=8388608
 788 system=system
 789
 790 [system.physmem]
 791 type=DRAMCtrl
 792 IDD0=0.055000
 793 IDD02=0.000000
 794 IDD2N=0.032000
 795 IDD2N2=0.000000
 796 IDD2P0=0.000000
 797 IDD2P02=0.000000
 798 IDD2P1=0.032000
 799 IDD2P12=0.000000
 800 IDD3N=0.038000
 801 IDD3N2=0.000000
 802 IDD3P0=0.000000
 803 IDD3P02=0.000000
 804 IDD3P1=0.038000
 805 IDD3P12=0.000000
 806 IDD4R=0.157000
 807 IDD4R2=0.000000
 808 IDD4W=0.125000
 809 IDD4W2=0.000000
 810 IDD5=0.235000
 811 IDD52=0.000000
 812 IDD6=0.020000
 813 IDD62=0.000000
 814 VDD=1.500000
 815 VDD2=0.000000
 816 activation_limit=4
 817 addr_mapping=RoRaBaCoCh
 818 bank_groups_per_rank=0
 819 banks_per_rank=8
 820 burst_length=8
 821 channels=1
 822 clk_domain=system.clk_domain
 823 conf_table_reported=true
 824 default_p_state=UNDEFINED
 825 device_bus_width=8
 826 device_rowbuffer_size=1024
 827 device_size=536870912
 828 devices_per_rank=8
 829 dll=true
 830 eventq_index=0
 831 in_addr_map=true
 832 kvm_map=true
 833 max_accesses_per_row=16
 834 mem_sched_policy=frfcfs
 835 min_writes_per_switch=16
 836 null=false
 837 p_state_clk_gate_bins=20
 838 p_state_clk_gate_max=1000000000000
 839 p_state_clk_gate_min=1000
 840 page_policy=open_adaptive
 841 power_model=Null
 842 range=0:134217727:0:0:0:0
 843 ranks_per_channel=2
 844 read_buffer_size=32
 845 static_backend_latency=10000
 846 static_frontend_latency=10000
 847 tBURST=5000
 848 tCCD_L=0
 849 tCK=1250
 850 tCL=13750
 851 tCS=2500
 852 tRAS=35000
 853 tRCD=13750
 854 tREFI=7800000
 855 tRFC=260000
 856 tRP=13750
 857 tRRD=6000
 858 tRRD_L=0
 859 tRTP=7500
 860 tRTW=2500
 861 tWR=15000
 862 tWTR=7500
 863 tXAW=30000
 864 tXP=6000
 865 tXPDLL=0
 866 tXS=270000
 867 tXSDLL=0
 868 write_buffer_size=64
 869 write_high_thresh_perc=85
 870 write_low_thresh_perc=50
 871 port=system.membus.master[0]
 872
 873 [system.voltage_domain]
 874 type=VoltageDomain
 875 eventq_index=0
 876 voltage=1.000000
 877