8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 kernel_addr_check=true
21 load_addr_mask=1099511627775
25 memories=system.physmem
29 work_begin_ckpt_count=0
30 work_begin_cpu_id_exit=-1
31 work_begin_exit_count=0
32 work_cpus_ckpt_count=0
36 system_port=system.membus.slave[0]
44 voltage_domain=system.voltage_domain
48 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
57 branchPred=system.cpu.branchPred
60 clk_domain=system.cpu_clk_domain
71 do_checkpoint_insts=true
73 do_statistics_insts=true
82 fuPool=system.cpu.fuPool
84 function_trace_start=0
89 interrupts=system.cpu.interrupts
94 max_insts_all_threads=0
95 max_insts_any_thread=0
96 max_loads_all_threads=0
97 max_loads_any_thread=0
108 renameToDecodeDelay=1
113 simpoint_start_insts=
114 smtCommitPolicy=RoundRobin
115 smtFetchPolicy=SingleThread
116 smtIQPolicy=Partitioned
118 smtLSQPolicy=Partitioned
120 smtNumFetchingThreads=1
121 smtROBPolicy=Partitioned
125 store_set_clear_period=250000
128 tracer=system.cpu.tracer
131 workload=system.cpu.workload
132 dcache_port=system.cpu.dcache.cpu_side
133 icache_port=system.cpu.icache.cpu_side
135 [system.cpu.branchPred]
141 choicePredictorSize=8192
144 globalPredictorSize=8192
147 localHistoryTableSize=2048
148 localPredictorSize=2048
155 addr_ranges=0:18446744073709551615
157 clk_domain=system.cpu_clk_domain
164 prefetch_on_access=false
167 sequential_access=false
170 tags=system.cpu.dcache.tags
174 cpu_side=system.cpu.dcache_port
175 mem_side=system.cpu.toL2Bus.slave[1]
177 [system.cpu.dcache.tags]
181 clk_domain=system.cpu_clk_domain
184 sequential_access=false
194 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
195 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
198 [system.cpu.fuPool.FUList0]
203 opList=system.cpu.fuPool.FUList0.opList
205 [system.cpu.fuPool.FUList0.opList]
212 [system.cpu.fuPool.FUList1]
214 children=opList0 opList1
217 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
219 [system.cpu.fuPool.FUList1.opList0]
226 [system.cpu.fuPool.FUList1.opList1]
233 [system.cpu.fuPool.FUList2]
235 children=opList0 opList1 opList2
238 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
240 [system.cpu.fuPool.FUList2.opList0]
247 [system.cpu.fuPool.FUList2.opList1]
254 [system.cpu.fuPool.FUList2.opList2]
261 [system.cpu.fuPool.FUList3]
263 children=opList0 opList1 opList2
266 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
268 [system.cpu.fuPool.FUList3.opList0]
275 [system.cpu.fuPool.FUList3.opList1]
282 [system.cpu.fuPool.FUList3.opList2]
289 [system.cpu.fuPool.FUList4]
294 opList=system.cpu.fuPool.FUList4.opList
296 [system.cpu.fuPool.FUList4.opList]
303 [system.cpu.fuPool.FUList5]
305 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
308 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
310 [system.cpu.fuPool.FUList5.opList00]
317 [system.cpu.fuPool.FUList5.opList01]
324 [system.cpu.fuPool.FUList5.opList02]
331 [system.cpu.fuPool.FUList5.opList03]
338 [system.cpu.fuPool.FUList5.opList04]
345 [system.cpu.fuPool.FUList5.opList05]
352 [system.cpu.fuPool.FUList5.opList06]
359 [system.cpu.fuPool.FUList5.opList07]
366 [system.cpu.fuPool.FUList5.opList08]
373 [system.cpu.fuPool.FUList5.opList09]
380 [system.cpu.fuPool.FUList5.opList10]
387 [system.cpu.fuPool.FUList5.opList11]
394 [system.cpu.fuPool.FUList5.opList12]
401 [system.cpu.fuPool.FUList5.opList13]
408 [system.cpu.fuPool.FUList5.opList14]
415 [system.cpu.fuPool.FUList5.opList15]
422 [system.cpu.fuPool.FUList5.opList16]
426 opClass=SimdFloatMisc
429 [system.cpu.fuPool.FUList5.opList17]
433 opClass=SimdFloatMult
436 [system.cpu.fuPool.FUList5.opList18]
440 opClass=SimdFloatMultAcc
443 [system.cpu.fuPool.FUList5.opList19]
447 opClass=SimdFloatSqrt
450 [system.cpu.fuPool.FUList6]
455 opList=system.cpu.fuPool.FUList6.opList
457 [system.cpu.fuPool.FUList6.opList]
464 [system.cpu.fuPool.FUList7]
466 children=opList0 opList1
469 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
471 [system.cpu.fuPool.FUList7.opList0]
478 [system.cpu.fuPool.FUList7.opList1]
485 [system.cpu.fuPool.FUList8]
490 opList=system.cpu.fuPool.FUList8.opList
492 [system.cpu.fuPool.FUList8.opList]
502 addr_ranges=0:18446744073709551615
504 clk_domain=system.cpu_clk_domain
511 prefetch_on_access=false
514 sequential_access=false
517 tags=system.cpu.icache.tags
521 cpu_side=system.cpu.icache_port
522 mem_side=system.cpu.toL2Bus.slave[0]
524 [system.cpu.icache.tags]
528 clk_domain=system.cpu_clk_domain
531 sequential_access=false
534 [system.cpu.interrupts]
551 addr_ranges=0:18446744073709551615
553 clk_domain=system.cpu_clk_domain
560 prefetch_on_access=false
563 sequential_access=false
566 tags=system.cpu.l2cache.tags
570 cpu_side=system.cpu.toL2Bus.master[0]
571 mem_side=system.membus.slave[1]
573 [system.cpu.l2cache.tags]
577 clk_domain=system.cpu_clk_domain
580 sequential_access=false
585 clk_domain=system.cpu_clk_domain
590 use_default_range=false
592 master=system.cpu.l2cache.cpu_side
593 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
599 [system.cpu.workload]
601 cmd=vortex lendian.raw
602 cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
608 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
611 max_stack_size=67108864
620 [system.cpu_clk_domain]
626 voltage_domain=system.voltage_domain
628 [system.dvfs_handler]
633 sys_clk_domain=system.clk_domain
634 transition_latency=100000000
638 clk_domain=system.clk_domain
643 use_default_range=false
645 master=system.physmem.port
646 slave=system.system_port system.cpu.l2cache.mem_side
675 addr_mapping=RoRaBaChCo
676 bank_groups_per_rank=0
680 clk_domain=system.clk_domain
681 conf_table_reported=true
683 device_rowbuffer_size=1024
688 max_accesses_per_row=16
689 mem_sched_policy=frfcfs
690 min_writes_per_switch=16
692 page_policy=open_adaptive
696 static_backend_latency=10000
697 static_frontend_latency=10000
720 write_high_thresh_perc=85
721 write_low_thresh_perc=50
722 port=system.membus.master[0]
724 [system.voltage_domain]