e46a676ebe617986098be2b43e1846a91959a2cc
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
24 memories=system.physmem
28 work_begin_ckpt_count=0
29 work_begin_cpu_id_exit=-1
30 work_begin_exit_count=0
31 work_cpus_ckpt_count=0
35 system_port=system.membus.slave[0]
43 voltage_domain=system.voltage_domain
47 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
56 branchPred=system.cpu.branchPred
59 clk_domain=system.cpu_clk_domain
70 do_checkpoint_insts=true
72 do_statistics_insts=true
80 fuPool=system.cpu.fuPool
82 function_trace_start=0
87 interrupts=system.cpu.interrupts
92 max_insts_all_threads=0
93 max_insts_any_thread=0
94 max_loads_all_threads=0
95 max_loads_any_thread=0
106 renameToDecodeDelay=1
111 simpoint_start_insts=
112 smtCommitPolicy=RoundRobin
113 smtFetchPolicy=SingleThread
114 smtIQPolicy=Partitioned
116 smtLSQPolicy=Partitioned
118 smtNumFetchingThreads=1
119 smtROBPolicy=Partitioned
123 store_set_clear_period=250000
126 tracer=system.cpu.tracer
130 workload=system.cpu.workload
131 dcache_port=system.cpu.dcache.cpu_side
132 icache_port=system.cpu.icache.cpu_side
134 [system.cpu.branchPred]
140 choicePredictorSize=8192
143 globalPredictorSize=8192
146 localHistoryTableSize=2048
147 localPredictorSize=2048
154 addr_ranges=0:18446744073709551615
156 clk_domain=system.cpu_clk_domain
163 prefetch_on_access=false
166 sequential_access=false
169 tags=system.cpu.dcache.tags
173 cpu_side=system.cpu.dcache_port
174 mem_side=system.cpu.toL2Bus.slave[1]
176 [system.cpu.dcache.tags]
180 clk_domain=system.cpu_clk_domain
183 sequential_access=false
193 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
194 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
197 [system.cpu.fuPool.FUList0]
202 opList=system.cpu.fuPool.FUList0.opList
204 [system.cpu.fuPool.FUList0.opList]
211 [system.cpu.fuPool.FUList1]
213 children=opList0 opList1
216 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
218 [system.cpu.fuPool.FUList1.opList0]
225 [system.cpu.fuPool.FUList1.opList1]
232 [system.cpu.fuPool.FUList2]
234 children=opList0 opList1 opList2
237 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
239 [system.cpu.fuPool.FUList2.opList0]
246 [system.cpu.fuPool.FUList2.opList1]
253 [system.cpu.fuPool.FUList2.opList2]
260 [system.cpu.fuPool.FUList3]
262 children=opList0 opList1 opList2
265 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
267 [system.cpu.fuPool.FUList3.opList0]
274 [system.cpu.fuPool.FUList3.opList1]
281 [system.cpu.fuPool.FUList3.opList2]
288 [system.cpu.fuPool.FUList4]
293 opList=system.cpu.fuPool.FUList4.opList
295 [system.cpu.fuPool.FUList4.opList]
302 [system.cpu.fuPool.FUList5]
304 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
307 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
309 [system.cpu.fuPool.FUList5.opList00]
316 [system.cpu.fuPool.FUList5.opList01]
323 [system.cpu.fuPool.FUList5.opList02]
330 [system.cpu.fuPool.FUList5.opList03]
337 [system.cpu.fuPool.FUList5.opList04]
344 [system.cpu.fuPool.FUList5.opList05]
351 [system.cpu.fuPool.FUList5.opList06]
358 [system.cpu.fuPool.FUList5.opList07]
365 [system.cpu.fuPool.FUList5.opList08]
372 [system.cpu.fuPool.FUList5.opList09]
379 [system.cpu.fuPool.FUList5.opList10]
386 [system.cpu.fuPool.FUList5.opList11]
393 [system.cpu.fuPool.FUList5.opList12]
400 [system.cpu.fuPool.FUList5.opList13]
407 [system.cpu.fuPool.FUList5.opList14]
414 [system.cpu.fuPool.FUList5.opList15]
421 [system.cpu.fuPool.FUList5.opList16]
425 opClass=SimdFloatMisc
428 [system.cpu.fuPool.FUList5.opList17]
432 opClass=SimdFloatMult
435 [system.cpu.fuPool.FUList5.opList18]
439 opClass=SimdFloatMultAcc
442 [system.cpu.fuPool.FUList5.opList19]
446 opClass=SimdFloatSqrt
449 [system.cpu.fuPool.FUList6]
454 opList=system.cpu.fuPool.FUList6.opList
456 [system.cpu.fuPool.FUList6.opList]
463 [system.cpu.fuPool.FUList7]
465 children=opList0 opList1
468 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
470 [system.cpu.fuPool.FUList7.opList0]
477 [system.cpu.fuPool.FUList7.opList1]
484 [system.cpu.fuPool.FUList8]
489 opList=system.cpu.fuPool.FUList8.opList
491 [system.cpu.fuPool.FUList8.opList]
501 addr_ranges=0:18446744073709551615
503 clk_domain=system.cpu_clk_domain
510 prefetch_on_access=false
513 sequential_access=false
516 tags=system.cpu.icache.tags
520 cpu_side=system.cpu.icache_port
521 mem_side=system.cpu.toL2Bus.slave[0]
523 [system.cpu.icache.tags]
527 clk_domain=system.cpu_clk_domain
530 sequential_access=false
533 [system.cpu.interrupts]
550 addr_ranges=0:18446744073709551615
552 clk_domain=system.cpu_clk_domain
559 prefetch_on_access=false
562 sequential_access=false
565 tags=system.cpu.l2cache.tags
569 cpu_side=system.cpu.toL2Bus.master[0]
570 mem_side=system.membus.slave[1]
572 [system.cpu.l2cache.tags]
576 clk_domain=system.cpu_clk_domain
579 sequential_access=false
584 clk_domain=system.cpu_clk_domain
588 use_default_range=false
590 master=system.cpu.l2cache.cpu_side
591 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
597 [system.cpu.workload]
599 cmd=vortex lendian.raw
600 cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
606 executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
609 max_stack_size=67108864
617 [system.cpu_clk_domain]
623 voltage_domain=system.voltage_domain
625 [system.dvfs_handler]
630 sys_clk_domain=system.clk_domain
631 transition_latency=100000000
635 clk_domain=system.clk_domain
639 use_default_range=false
641 master=system.physmem.port
642 slave=system.system_port system.cpu.l2cache.mem_side
647 addr_mapping=RoRaBaChCo
651 clk_domain=system.clk_domain
652 conf_table_reported=true
654 device_rowbuffer_size=1024
658 max_accesses_per_row=16
659 mem_sched_policy=frfcfs
660 min_writes_per_switch=16
662 page_policy=open_adaptive
666 static_backend_latency=10000
667 static_frontend_latency=10000
683 write_high_thresh_perc=85
684 write_low_thresh_perc=50
685 port=system.membus.master[0]
687 [system.voltage_domain]