2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.022262 # Number of seconds simulated
4 sim_ticks 22262172500 # Number of ticks simulated
5 final_tick 22262172500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 164105 # Simulator instruction rate (inst/s)
8 host_op_rate 164105 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 45900767 # Simulator tick rate (ticks/s)
10 host_mem_usage 245260 # Number of bytes of host memory used
11 host_seconds 485.01 # Real time elapsed on the host
12 sim_insts 79591756 # Number of instructions simulated
13 sim_ops 79591756 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 487296 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 10152448 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 10639744 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 487296 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 487296 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 7297472 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 7297472 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 7614 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 158632 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 166246 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 114023 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 114023 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 21888969 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 456040308 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 477929277 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 21888969 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 21888969 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 327796939 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 327796939 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 327796939 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 21888969 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 456040308 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 805726216 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 166246 # Number of read requests accepted
40 system.physmem.writeReqs 114023 # Number of write requests accepted
41 system.physmem.readBursts 166246 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 114023 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 10639232 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 7295808 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 10639744 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 7297472 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 10440 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 10463 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 10061 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 10417 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 10395 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 9841 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 10308 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 10597 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 10638 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 10546 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 10227 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 10273 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 10619 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 10481 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 10621 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 7082 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 7258 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 6997 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 7170 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 6776 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 7085 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 7222 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 6942 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 7084 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 6990 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 6966 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 7288 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 22262139000 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 166246 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 114023 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 51670 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 53911 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 45458 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 15180 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 839 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 879 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 1392 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 2489 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 4591 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 5919 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 6398 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 7095 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 7509 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 7936 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 8984 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 9696 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 8624 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 8779 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 8776 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 8045 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 263 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 156 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 80 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 52156 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 343.855817 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 201.745106 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 344.281593 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 18285 35.06% 35.06% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 10756 20.62% 55.68% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 5580 10.70% 66.38% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 3146 6.03% 72.41% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 2660 5.10% 77.51% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 1727 3.31% 80.82% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 1787 3.43% 84.25% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 1244 2.39% 86.63% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 6971 13.37% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 52156 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 6968 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 23.856056 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 342.059287 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 6967 99.99% 99.99% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::total 6968 # Reads before turning the bus around for writes
216 system.physmem.wrPerTurnAround::samples 6968 # Writes before turning the bus around for reads
217 system.physmem.wrPerTurnAround::mean 16.360075 # Writes before turning the bus around for reads
218 system.physmem.wrPerTurnAround::gmean 16.330777 # Writes before turning the bus around for reads
219 system.physmem.wrPerTurnAround::stdev 1.045922 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::16 6065 87.04% 87.04% # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::17 29 0.42% 87.46% # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::18 476 6.83% 94.29% # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::19 227 3.26% 97.55% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::20 92 1.32% 98.87% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::21 39 0.56% 99.43% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::22 17 0.24% 99.67% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::23 11 0.16% 99.83% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::total 6968 # Writes before turning the bus around for reads
232 system.physmem.totQLat 5413019750 # Total ticks spent queuing
233 system.physmem.totMemAccLat 8529982250 # Total ticks spent from burst creation until serviced by the DRAM
234 system.physmem.totBusLat 831190000 # Total ticks spent in databus transfers
235 system.physmem.avgQLat 32561.87 # Average queueing delay per DRAM burst
236 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
237 system.physmem.avgMemAccLat 51311.87 # Average memory access latency per DRAM burst
238 system.physmem.avgRdBW 477.91 # Average DRAM read bandwidth in MiByte/s
239 system.physmem.avgWrBW 327.72 # Average achieved write bandwidth in MiByte/s
240 system.physmem.avgRdBWSys 477.93 # Average system read bandwidth in MiByte/s
241 system.physmem.avgWrBWSys 327.80 # Average system write bandwidth in MiByte/s
242 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
243 system.physmem.busUtil 6.29 # Data bus utilization in percentage
244 system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads
245 system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes
246 system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
247 system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
248 system.physmem.readRowHits 146096 # Number of row buffer hits during reads
249 system.physmem.writeRowHits 81976 # Number of row buffer hits during writes
250 system.physmem.readRowHitRate 87.88 # Row buffer hit rate for reads
251 system.physmem.writeRowHitRate 71.89 # Row buffer hit rate for writes
252 system.physmem.avgGap 79431.33 # Average gap between requests
253 system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined
254 system.physmem.memoryStateTime::IDLE 9551525000 # Time in different power states
255 system.physmem.memoryStateTime::REF 743340000 # Time in different power states
256 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
257 system.physmem.memoryStateTime::ACT 11966317750 # Time in different power states
258 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
259 system.membus.throughput 805726216 # Throughput (bytes/s)
260 system.membus.trans_dist::ReadReq 35460 # Transaction distribution
261 system.membus.trans_dist::ReadResp 35460 # Transaction distribution
262 system.membus.trans_dist::Writeback 114023 # Transaction distribution
263 system.membus.trans_dist::ReadExReq 130786 # Transaction distribution
264 system.membus.trans_dist::ReadExResp 130786 # Transaction distribution
265 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446515 # Packet count per connected master and slave (bytes)
266 system.membus.pkt_count::total 446515 # Packet count per connected master and slave (bytes)
267 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17937216 # Cumulative packet size per connected master and slave (bytes)
268 system.membus.tot_pkt_size::total 17937216 # Cumulative packet size per connected master and slave (bytes)
269 system.membus.data_through_bus 17937216 # Total data (bytes)
270 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
271 system.membus.reqLayer0.occupancy 1235956000 # Layer occupancy (ticks)
272 system.membus.reqLayer0.utilization 5.6 # Layer utilization (%)
273 system.membus.respLayer1.occupancy 1525146000 # Layer occupancy (ticks)
274 system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
275 system.cpu_clk_domain.clock 500 # Clock period in ticks
276 system.cpu.branchPred.lookups 16618538 # Number of BP lookups
277 system.cpu.branchPred.condPredicted 10751969 # Number of conditional branches predicted
278 system.cpu.branchPred.condIncorrect 360716 # Number of conditional branches incorrect
279 system.cpu.branchPred.BTBLookups 10752045 # Number of BTB lookups
280 system.cpu.branchPred.BTBHits 7371197 # Number of BTB hits
281 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
282 system.cpu.branchPred.BTBHitPct 68.556233 # BTB Hit Percentage
283 system.cpu.branchPred.usedRAS 1990414 # Number of times the RAS was used to get a target.
284 system.cpu.branchPred.RASInCorrect 2895 # Number of incorrect RAS predictions.
285 system.cpu.dtb.fetch_hits 0 # ITB hits
286 system.cpu.dtb.fetch_misses 0 # ITB misses
287 system.cpu.dtb.fetch_acv 0 # ITB acv
288 system.cpu.dtb.fetch_accesses 0 # ITB accesses
289 system.cpu.dtb.read_hits 22632838 # DTB read hits
290 system.cpu.dtb.read_misses 226204 # DTB read misses
291 system.cpu.dtb.read_acv 19 # DTB read access violations
292 system.cpu.dtb.read_accesses 22859042 # DTB read accesses
293 system.cpu.dtb.write_hits 15863725 # DTB write hits
294 system.cpu.dtb.write_misses 44788 # DTB write misses
295 system.cpu.dtb.write_acv 4 # DTB write access violations
296 system.cpu.dtb.write_accesses 15908513 # DTB write accesses
297 system.cpu.dtb.data_hits 38496563 # DTB hits
298 system.cpu.dtb.data_misses 270992 # DTB misses
299 system.cpu.dtb.data_acv 23 # DTB access violations
300 system.cpu.dtb.data_accesses 38767555 # DTB accesses
301 system.cpu.itb.fetch_hits 13910081 # ITB hits
302 system.cpu.itb.fetch_misses 31577 # ITB misses
303 system.cpu.itb.fetch_acv 0 # ITB acv
304 system.cpu.itb.fetch_accesses 13941658 # ITB accesses
305 system.cpu.itb.read_hits 0 # DTB read hits
306 system.cpu.itb.read_misses 0 # DTB read misses
307 system.cpu.itb.read_acv 0 # DTB read access violations
308 system.cpu.itb.read_accesses 0 # DTB read accesses
309 system.cpu.itb.write_hits 0 # DTB write hits
310 system.cpu.itb.write_misses 0 # DTB write misses
311 system.cpu.itb.write_acv 0 # DTB write access violations
312 system.cpu.itb.write_accesses 0 # DTB write accesses
313 system.cpu.itb.data_hits 0 # DTB hits
314 system.cpu.itb.data_misses 0 # DTB misses
315 system.cpu.itb.data_acv 0 # DTB access violations
316 system.cpu.itb.data_accesses 0 # DTB accesses
317 system.cpu.workload.num_syscalls 4583 # Number of system calls
318 system.cpu.numCycles 44524349 # number of cpu cycles simulated
319 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
320 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
321 system.cpu.fetch.icacheStallCycles 15777207 # Number of cycles fetch is stalled on an Icache miss
322 system.cpu.fetch.Insts 106088567 # Number of instructions fetch has processed
323 system.cpu.fetch.Branches 16618538 # Number of branches that fetch encountered
324 system.cpu.fetch.predictedBranches 9361611 # Number of branches that fetch has predicted taken
325 system.cpu.fetch.Cycles 27200271 # Number of cycles fetch has run and was not squashing or blocked
326 system.cpu.fetch.SquashCycles 960062 # Number of cycles fetch has spent squashing
327 system.cpu.fetch.TlbCycles 179 # Number of cycles fetch has spent waiting for tlb
328 system.cpu.fetch.MiscStallCycles 5019 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
329 system.cpu.fetch.PendingTrapStallCycles 332851 # Number of stall cycles due to pending traps
330 system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
331 system.cpu.fetch.CacheLines 13910081 # Number of cache lines fetched
332 system.cpu.fetch.IcacheSquashes 206082 # Number of outstanding Icache misses that were squashed
333 system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
334 system.cpu.fetch.rateDist::samples 43795615 # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::mean 2.422356 # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::stdev 3.133763 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::0 24068312 54.96% 54.96% # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::1 1538186 3.51% 58.47% # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::2 1404705 3.21% 61.68% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::3 1522843 3.48% 65.15% # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::4 4236021 9.67% 74.82% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::5 1845751 4.21% 79.04% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::6 684777 1.56% 80.60% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::7 1069219 2.44% 83.04% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::8 7425801 16.96% 100.00% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::total 43795615 # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.branchRate 0.373246 # Number of branch fetches per cycle
352 system.cpu.fetch.rate 2.382709 # Number of inst fetches per cycle
353 system.cpu.decode.IdleCycles 15090251 # Number of cycles decode is idle
354 system.cpu.decode.BlockedCycles 9271065 # Number of cycles decode is blocked
355 system.cpu.decode.RunCycles 18462331 # Number of cycles decode is running
356 system.cpu.decode.UnblockCycles 590423 # Number of cycles decode is unblocking
357 system.cpu.decode.SquashCycles 381545 # Number of cycles decode is squashing
358 system.cpu.decode.BranchResolved 3739004 # Number of times decode resolved a branch
359 system.cpu.decode.BranchMispred 100344 # Number of times decode detected a branch misprediction
360 system.cpu.decode.DecodedInsts 103984343 # Number of instructions handled by decode
361 system.cpu.decode.SquashedInsts 314766 # Number of squashed instructions handled by decode
362 system.cpu.rename.SquashCycles 381545 # Number of cycles rename is squashing
363 system.cpu.rename.IdleCycles 15473555 # Number of cycles rename is idle
364 system.cpu.rename.BlockCycles 6415386 # Number of cycles rename is blocking
365 system.cpu.rename.serializeStallCycles 96680 # count of cycles rename stalled for serializing inst
366 system.cpu.rename.RunCycles 18647393 # Number of cycles rename is running
367 system.cpu.rename.UnblockCycles 2781056 # Number of cycles rename is unblocking
368 system.cpu.rename.RenamedInsts 102842787 # Number of instructions processed by rename
369 system.cpu.rename.ROBFullEvents 3945 # Number of times rename has blocked due to ROB full
370 system.cpu.rename.IQFullEvents 148156 # Number of times rename has blocked due to IQ full
371 system.cpu.rename.LQFullEvents 330502 # Number of times rename has blocked due to LQ full
372 system.cpu.rename.SQFullEvents 2246834 # Number of times rename has blocked due to SQ full
373 system.cpu.rename.RenamedOperands 61884966 # Number of destination operands rename has renamed
374 system.cpu.rename.RenameLookups 124097859 # Number of register rename lookups that rename has made
375 system.cpu.rename.int_rename_lookups 123771677 # Number of integer rename lookups
376 system.cpu.rename.fp_rename_lookups 326181 # Number of floating rename lookups
377 system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
378 system.cpu.rename.UndoneMaps 9338085 # Number of HB maps that are undone due to squashing
379 system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed
380 system.cpu.rename.tempSerializingInsts 5827 # count of temporary serializing insts renamed
381 system.cpu.rename.skidInsts 2465534 # count of insts added to the skid buffer
382 system.cpu.memDep0.insertedLoads 23256981 # Number of loads inserted to the mem dependence unit.
383 system.cpu.memDep0.insertedStores 16451468 # Number of stores inserted to the mem dependence unit.
384 system.cpu.memDep0.conflictingLoads 1256796 # Number of conflicting loads.
385 system.cpu.memDep0.conflictingStores 554193 # Number of conflicting stores.
386 system.cpu.iq.iqInstsAdded 91273922 # Number of instructions added to the IQ (excludes non-spec)
387 system.cpu.iq.iqNonSpecInstsAdded 5644 # Number of non-speculative instructions added to the IQ
388 system.cpu.iq.iqInstsIssued 89085619 # Number of instructions issued
389 system.cpu.iq.iqSquashedInstsIssued 78698 # Number of squashed instructions issued
390 system.cpu.iq.iqSquashedInstsExamined 11197079 # Number of squashed instructions iterated over during squash; mainly for profiling
391 system.cpu.iq.iqSquashedOperandsExamined 4703509 # Number of squashed operands that are examined and possibly removed from graph
392 system.cpu.iq.iqSquashedNonSpecRemoved 1061 # Number of squashed non-spec instructions that were removed
393 system.cpu.iq.issued_per_cycle::samples 43795615 # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::mean 2.034122 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::stdev 2.247476 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::0 17182377 39.23% 39.23% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::1 5792116 13.23% 52.46% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::2 5098261 11.64% 64.10% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::3 4417263 10.09% 74.19% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::4 4344645 9.92% 84.11% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::5 2649252 6.05% 90.15% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::6 1946446 4.44% 94.60% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::7 1380364 3.15% 97.75% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::8 984891 2.25% 100.00% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::total 43795615 # Number of insts issued each cycle
410 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
411 system.cpu.iq.fu_full::IntAlu 244209 9.65% 9.65% # attempts to use FU when none available
412 system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
413 system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
414 system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
415 system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
440 system.cpu.iq.fu_full::MemRead 1174646 46.40% 56.05% # attempts to use FU when none available
441 system.cpu.iq.fu_full::MemWrite 1112477 43.95% 100.00% # attempts to use FU when none available
442 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
444 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
445 system.cpu.iq.FU_type_0::IntAlu 49643458 55.73% 55.73% # Type of FU issued
446 system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.78% # Type of FU issued
447 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued
448 system.cpu.iq.FU_type_0::FloatAdd 121526 0.14% 55.91% # Type of FU issued
449 system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.91% # Type of FU issued
450 system.cpu.iq.FU_type_0::FloatCvt 121394 0.14% 56.05% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.05% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatDiv 39070 0.04% 56.09% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued
474 system.cpu.iq.FU_type_0::MemRead 23048961 25.87% 81.96% # Type of FU issued
475 system.cpu.iq.FU_type_0::MemWrite 16066967 18.04% 100.00% # Type of FU issued
476 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
477 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
478 system.cpu.iq.FU_type_0::total 89085619 # Type of FU issued
479 system.cpu.iq.rate 2.000829 # Inst issue rate
480 system.cpu.iq.fu_busy_cnt 2531332 # FU busy when requested
481 system.cpu.iq.fu_busy_rate 0.028415 # FU busy rate (busy events/executed inst)
482 system.cpu.iq.int_inst_queue_reads 223962824 # Number of integer instruction queue reads
483 system.cpu.iq.int_inst_queue_writes 102066580 # Number of integer instruction queue writes
484 system.cpu.iq.int_inst_queue_wakeup_accesses 87151859 # Number of integer instruction queue wakeup accesses
485 system.cpu.iq.fp_inst_queue_reads 614059 # Number of floating instruction queue reads
486 system.cpu.iq.fp_inst_queue_writes 431019 # Number of floating instruction queue writes
487 system.cpu.iq.fp_inst_queue_wakeup_accesses 300727 # Number of floating instruction queue wakeup accesses
488 system.cpu.iq.int_alu_accesses 91309756 # Number of integer alu accesses
489 system.cpu.iq.fp_alu_accesses 307195 # Number of floating point alu accesses
490 system.cpu.iew.lsq.thread0.forwLoads 1661224 # Number of loads that had data forwarded from stores
491 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
492 system.cpu.iew.lsq.thread0.squashedLoads 2980343 # Number of loads squashed
493 system.cpu.iew.lsq.thread0.ignoredResponses 6431 # Number of memory responses ignored because the instruction is squashed
494 system.cpu.iew.lsq.thread0.memOrderViolation 21452 # Number of memory ordering violations
495 system.cpu.iew.lsq.thread0.squashedStores 1838091 # Number of stores squashed
496 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
497 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
498 system.cpu.iew.lsq.thread0.rescheduledLoads 2952 # Number of loads that were rescheduled
499 system.cpu.iew.lsq.thread0.cacheBlocked 325709 # Number of times an access to memory failed due to the cache being blocked
500 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
501 system.cpu.iew.iewSquashCycles 381545 # Number of cycles IEW is squashing
502 system.cpu.iew.iewBlockCycles 1215876 # Number of cycles IEW is blocking
503 system.cpu.iew.iewUnblockCycles 4878836 # Number of cycles IEW is unblocking
504 system.cpu.iew.iewDispatchedInsts 100803158 # Number of instructions dispatched to IQ
505 system.cpu.iew.iewDispSquashedInsts 157110 # Number of squashed instructions skipped by dispatch
506 system.cpu.iew.iewDispLoadInsts 23256981 # Number of dispatched load instructions
507 system.cpu.iew.iewDispStoreInsts 16451468 # Number of dispatched store instructions
508 system.cpu.iew.iewDispNonSpecInsts 5576 # Number of dispatched non-speculative instructions
509 system.cpu.iew.iewIQFullEvents 3364 # Number of times the IQ has become full, causing a stall
510 system.cpu.iew.iewLSQFullEvents 4856172 # Number of times the LSQ has become full, causing a stall
511 system.cpu.iew.memOrderViolationEvents 21452 # Number of memory order violations
512 system.cpu.iew.predictedTakenIncorrect 149650 # Number of branches that were predicted taken incorrectly
513 system.cpu.iew.predictedNotTakenIncorrect 157694 # Number of branches that were predicted not taken incorrectly
514 system.cpu.iew.branchMispredicts 307344 # Number of branch mispredicts detected at execute
515 system.cpu.iew.iewExecutedInsts 88311132 # Number of executed instructions
516 system.cpu.iew.iewExecLoadInsts 22859779 # Number of load instructions executed
517 system.cpu.iew.iewExecSquashedInsts 774487 # Number of squashed instructions skipped in execute
518 system.cpu.iew.exec_swp 0 # number of swp insts executed
519 system.cpu.iew.exec_nop 9523592 # number of nop insts executed
520 system.cpu.iew.exec_refs 38768607 # number of memory reference insts executed
521 system.cpu.iew.exec_branches 15170240 # Number of branches executed
522 system.cpu.iew.exec_stores 15908828 # Number of stores executed
523 system.cpu.iew.exec_rate 1.983435 # Inst execution rate
524 system.cpu.iew.wb_sent 87867079 # cumulative count of insts sent to commit
525 system.cpu.iew.wb_count 87452586 # cumulative count of insts written-back
526 system.cpu.iew.wb_producers 33893139 # num instructions producing a value
527 system.cpu.iew.wb_consumers 44339625 # num instructions consuming a value
528 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
529 system.cpu.iew.wb_rate 1.964152 # insts written-back per cycle
530 system.cpu.iew.wb_fanout 0.764398 # average fanout of values written-back
531 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
532 system.cpu.commit.commitSquashedInsts 9260506 # The number of squashed insts skipped by commit
533 system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
534 system.cpu.commit.branchMispredicts 262230 # The number of times a branch was mispredicted
535 system.cpu.commit.committed_per_cycle::samples 42432313 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::mean 2.081920 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::stdev 2.885099 # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::0 20891279 49.23% 49.23% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::1 6327574 14.91% 64.15% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::2 2939948 6.93% 71.08% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::3 1761291 4.15% 75.23% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::4 1656008 3.90% 79.13% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::5 1140180 2.69% 81.82% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::6 1204228 2.84% 84.65% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::7 795411 1.87% 86.53% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::8 5716394 13.47% 100.00% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::total 42432313 # Number of insts commited each cycle
552 system.cpu.commit.committedInsts 88340672 # Number of instructions committed
553 system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
554 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
555 system.cpu.commit.refs 34890015 # Number of memory references committed
556 system.cpu.commit.loads 20276638 # Number of loads committed
557 system.cpu.commit.membars 0 # Number of memory barriers committed
558 system.cpu.commit.branches 13754477 # Number of branches committed
559 system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
560 system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
561 system.cpu.commit.function_calls 1661057 # Number of function calls committed.
562 system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction
563 system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction
564 system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction
565 system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction
566 system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction
567 system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction
568 system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction
569 system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction
592 system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction
593 system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction
594 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
595 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
596 system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
597 system.cpu.commit.bw_lim_events 5716394 # number cycles where commit BW limit reached
598 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
599 system.cpu.rob.rob_reads 132999755 # The number of ROB reads
600 system.cpu.rob.rob_writes 196569210 # The number of ROB writes
601 system.cpu.timesIdled 47704 # Number of times that the entire CPU went into an idle state and unscheduled itself
602 system.cpu.idleCycles 728734 # Total number of cycles that the CPU has spent unscheduled due to idling
603 system.cpu.committedInsts 79591756 # Number of Instructions Simulated
604 system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
605 system.cpu.cpi 0.559409 # CPI: Cycles Per Instruction
606 system.cpu.cpi_total 0.559409 # CPI: Total CPI of All Threads
607 system.cpu.ipc 1.787601 # IPC: Instructions Per Cycle
608 system.cpu.ipc_total 1.787601 # IPC: Total IPC of All Threads
609 system.cpu.int_regfile_reads 116880103 # number of integer regfile reads
610 system.cpu.int_regfile_writes 57914968 # number of integer regfile writes
611 system.cpu.fp_regfile_reads 255764 # number of floating regfile reads
612 system.cpu.fp_regfile_writes 241194 # number of floating regfile writes
613 system.cpu.misc_regfile_reads 38207 # number of misc regfile reads
614 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
615 system.cpu.toL2Bus.throughput 1351038673 # Throughput (bytes/s)
616 system.cpu.toL2Bus.trans_dist::ReadReq 157664 # Transaction distribution
617 system.cpu.toL2Bus.trans_dist::ReadResp 157663 # Transaction distribution
618 system.cpu.toL2Bus.trans_dist::Writeback 168884 # Transaction distribution
619 system.cpu.toL2Bus.trans_dist::ReadExReq 143407 # Transaction distribution
620 system.cpu.toL2Bus.trans_dist::ReadExResp 143407 # Transaction distribution
621 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191277 # Packet count per connected master and slave (bytes)
622 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579748 # Packet count per connected master and slave (bytes)
623 system.cpu.toL2Bus.pkt_count::total 771025 # Packet count per connected master and slave (bytes)
624 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6120832 # Cumulative packet size per connected master and slave (bytes)
625 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956224 # Cumulative packet size per connected master and slave (bytes)
626 system.cpu.toL2Bus.tot_pkt_size::total 30077056 # Cumulative packet size per connected master and slave (bytes)
627 system.cpu.toL2Bus.data_through_bus 30077056 # Total data (bytes)
628 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
629 system.cpu.toL2Bus.reqLayer0.occupancy 403861500 # Layer occupancy (ticks)
630 system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%)
631 system.cpu.toL2Bus.respLayer0.occupancy 144811965 # Layer occupancy (ticks)
632 system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
633 system.cpu.toL2Bus.respLayer1.occupancy 321850746 # Layer occupancy (ticks)
634 system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
635 system.cpu.icache.tags.replacements 93590 # number of replacements
636 system.cpu.icache.tags.tagsinuse 1918.549362 # Cycle average of tags in use
637 system.cpu.icache.tags.total_refs 13801419 # Total number of references to valid blocks.
638 system.cpu.icache.tags.sampled_refs 95638 # Sample count of references to valid blocks.
639 system.cpu.icache.tags.avg_refs 144.308946 # Average number of references to valid blocks.
640 system.cpu.icache.tags.warmup_cycle 18781387250 # Cycle when the warmup percentage was hit.
641 system.cpu.icache.tags.occ_blocks::cpu.inst 1918.549362 # Average occupied blocks per requestor
642 system.cpu.icache.tags.occ_percent::cpu.inst 0.936792 # Average percentage of cache occupancy
643 system.cpu.icache.tags.occ_percent::total 0.936792 # Average percentage of cache occupancy
644 system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
645 system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
646 system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
647 system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
648 system.cpu.icache.tags.age_task_id_blocks_1024::3 1479 # Occupied blocks per task id
649 system.cpu.icache.tags.age_task_id_blocks_1024::4 377 # Occupied blocks per task id
650 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
651 system.cpu.icache.tags.tag_accesses 27915798 # Number of tag accesses
652 system.cpu.icache.tags.data_accesses 27915798 # Number of data accesses
653 system.cpu.icache.ReadReq_hits::cpu.inst 13801419 # number of ReadReq hits
654 system.cpu.icache.ReadReq_hits::total 13801419 # number of ReadReq hits
655 system.cpu.icache.demand_hits::cpu.inst 13801419 # number of demand (read+write) hits
656 system.cpu.icache.demand_hits::total 13801419 # number of demand (read+write) hits
657 system.cpu.icache.overall_hits::cpu.inst 13801419 # number of overall hits
658 system.cpu.icache.overall_hits::total 13801419 # number of overall hits
659 system.cpu.icache.ReadReq_misses::cpu.inst 108661 # number of ReadReq misses
660 system.cpu.icache.ReadReq_misses::total 108661 # number of ReadReq misses
661 system.cpu.icache.demand_misses::cpu.inst 108661 # number of demand (read+write) misses
662 system.cpu.icache.demand_misses::total 108661 # number of demand (read+write) misses
663 system.cpu.icache.overall_misses::cpu.inst 108661 # number of overall misses
664 system.cpu.icache.overall_misses::total 108661 # number of overall misses
665 system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007129462 # number of ReadReq miss cycles
666 system.cpu.icache.ReadReq_miss_latency::total 2007129462 # number of ReadReq miss cycles
667 system.cpu.icache.demand_miss_latency::cpu.inst 2007129462 # number of demand (read+write) miss cycles
668 system.cpu.icache.demand_miss_latency::total 2007129462 # number of demand (read+write) miss cycles
669 system.cpu.icache.overall_miss_latency::cpu.inst 2007129462 # number of overall miss cycles
670 system.cpu.icache.overall_miss_latency::total 2007129462 # number of overall miss cycles
671 system.cpu.icache.ReadReq_accesses::cpu.inst 13910080 # number of ReadReq accesses(hits+misses)
672 system.cpu.icache.ReadReq_accesses::total 13910080 # number of ReadReq accesses(hits+misses)
673 system.cpu.icache.demand_accesses::cpu.inst 13910080 # number of demand (read+write) accesses
674 system.cpu.icache.demand_accesses::total 13910080 # number of demand (read+write) accesses
675 system.cpu.icache.overall_accesses::cpu.inst 13910080 # number of overall (read+write) accesses
676 system.cpu.icache.overall_accesses::total 13910080 # number of overall (read+write) accesses
677 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007812 # miss rate for ReadReq accesses
678 system.cpu.icache.ReadReq_miss_rate::total 0.007812 # miss rate for ReadReq accesses
679 system.cpu.icache.demand_miss_rate::cpu.inst 0.007812 # miss rate for demand accesses
680 system.cpu.icache.demand_miss_rate::total 0.007812 # miss rate for demand accesses
681 system.cpu.icache.overall_miss_rate::cpu.inst 0.007812 # miss rate for overall accesses
682 system.cpu.icache.overall_miss_rate::total 0.007812 # miss rate for overall accesses
683 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18471.479758 # average ReadReq miss latency
684 system.cpu.icache.ReadReq_avg_miss_latency::total 18471.479758 # average ReadReq miss latency
685 system.cpu.icache.demand_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency
686 system.cpu.icache.demand_avg_miss_latency::total 18471.479758 # average overall miss latency
687 system.cpu.icache.overall_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency
688 system.cpu.icache.overall_avg_miss_latency::total 18471.479758 # average overall miss latency
689 system.cpu.icache.blocked_cycles::no_mshrs 421 # number of cycles access was blocked
690 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
691 system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
692 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
693 system.cpu.icache.avg_blocked_cycles::no_mshrs 52.625000 # average number of cycles each access was blocked
694 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
695 system.cpu.icache.fast_writes 0 # number of fast writes performed
696 system.cpu.icache.cache_copies 0 # number of cache copies performed
697 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13022 # number of ReadReq MSHR hits
698 system.cpu.icache.ReadReq_mshr_hits::total 13022 # number of ReadReq MSHR hits
699 system.cpu.icache.demand_mshr_hits::cpu.inst 13022 # number of demand (read+write) MSHR hits
700 system.cpu.icache.demand_mshr_hits::total 13022 # number of demand (read+write) MSHR hits
701 system.cpu.icache.overall_mshr_hits::cpu.inst 13022 # number of overall MSHR hits
702 system.cpu.icache.overall_mshr_hits::total 13022 # number of overall MSHR hits
703 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95639 # number of ReadReq MSHR misses
704 system.cpu.icache.ReadReq_mshr_misses::total 95639 # number of ReadReq MSHR misses
705 system.cpu.icache.demand_mshr_misses::cpu.inst 95639 # number of demand (read+write) MSHR misses
706 system.cpu.icache.demand_mshr_misses::total 95639 # number of demand (read+write) MSHR misses
707 system.cpu.icache.overall_mshr_misses::cpu.inst 95639 # number of overall MSHR misses
708 system.cpu.icache.overall_mshr_misses::total 95639 # number of overall MSHR misses
709 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1547349535 # number of ReadReq MSHR miss cycles
710 system.cpu.icache.ReadReq_mshr_miss_latency::total 1547349535 # number of ReadReq MSHR miss cycles
711 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1547349535 # number of demand (read+write) MSHR miss cycles
712 system.cpu.icache.demand_mshr_miss_latency::total 1547349535 # number of demand (read+write) MSHR miss cycles
713 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1547349535 # number of overall MSHR miss cycles
714 system.cpu.icache.overall_mshr_miss_latency::total 1547349535 # number of overall MSHR miss cycles
715 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for ReadReq accesses
716 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006876 # mshr miss rate for ReadReq accesses
717 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for demand accesses
718 system.cpu.icache.demand_mshr_miss_rate::total 0.006876 # mshr miss rate for demand accesses
719 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for overall accesses
720 system.cpu.icache.overall_mshr_miss_rate::total 0.006876 # mshr miss rate for overall accesses
721 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16179.064346 # average ReadReq mshr miss latency
722 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16179.064346 # average ReadReq mshr miss latency
723 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16179.064346 # average overall mshr miss latency
724 system.cpu.icache.demand_avg_mshr_miss_latency::total 16179.064346 # average overall mshr miss latency
725 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16179.064346 # average overall mshr miss latency
726 system.cpu.icache.overall_avg_mshr_miss_latency::total 16179.064346 # average overall mshr miss latency
727 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
728 system.cpu.l2cache.tags.replacements 132342 # number of replacements
729 system.cpu.l2cache.tags.tagsinuse 30650.396196 # Cycle average of tags in use
730 system.cpu.l2cache.tags.total_refs 161877 # Total number of references to valid blocks.
731 system.cpu.l2cache.tags.sampled_refs 164409 # Sample count of references to valid blocks.
732 system.cpu.l2cache.tags.avg_refs 0.984599 # Average number of references to valid blocks.
733 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
734 system.cpu.l2cache.tags.occ_blocks::writebacks 26717.381554 # Average occupied blocks per requestor
735 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2107.778355 # Average occupied blocks per requestor
736 system.cpu.l2cache.tags.occ_blocks::cpu.data 1825.236287 # Average occupied blocks per requestor
737 system.cpu.l2cache.tags.occ_percent::writebacks 0.815350 # Average percentage of cache occupancy
738 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064324 # Average percentage of cache occupancy
739 system.cpu.l2cache.tags.occ_percent::cpu.data 0.055702 # Average percentage of cache occupancy
740 system.cpu.l2cache.tags.occ_percent::total 0.935376 # Average percentage of cache occupancy
741 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id
742 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
743 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3055 # Occupied blocks per task id
744 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28591 # Occupied blocks per task id
745 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 187 # Occupied blocks per task id
746 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58 # Occupied blocks per task id
747 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978607 # Percentage of cache occupancy per task id
748 system.cpu.l2cache.tags.tag_accesses 4067456 # Number of tag accesses
749 system.cpu.l2cache.tags.data_accesses 4067456 # Number of data accesses
750 system.cpu.l2cache.ReadReq_hits::cpu.inst 88024 # number of ReadReq hits
751 system.cpu.l2cache.ReadReq_hits::cpu.data 34179 # number of ReadReq hits
752 system.cpu.l2cache.ReadReq_hits::total 122203 # number of ReadReq hits
753 system.cpu.l2cache.Writeback_hits::writebacks 168884 # number of Writeback hits
754 system.cpu.l2cache.Writeback_hits::total 168884 # number of Writeback hits
755 system.cpu.l2cache.ReadExReq_hits::cpu.data 12621 # number of ReadExReq hits
756 system.cpu.l2cache.ReadExReq_hits::total 12621 # number of ReadExReq hits
757 system.cpu.l2cache.demand_hits::cpu.inst 88024 # number of demand (read+write) hits
758 system.cpu.l2cache.demand_hits::cpu.data 46800 # number of demand (read+write) hits
759 system.cpu.l2cache.demand_hits::total 134824 # number of demand (read+write) hits
760 system.cpu.l2cache.overall_hits::cpu.inst 88024 # number of overall hits
761 system.cpu.l2cache.overall_hits::cpu.data 46800 # number of overall hits
762 system.cpu.l2cache.overall_hits::total 134824 # number of overall hits
763 system.cpu.l2cache.ReadReq_misses::cpu.inst 7615 # number of ReadReq misses
764 system.cpu.l2cache.ReadReq_misses::cpu.data 27846 # number of ReadReq misses
765 system.cpu.l2cache.ReadReq_misses::total 35461 # number of ReadReq misses
766 system.cpu.l2cache.ReadExReq_misses::cpu.data 130786 # number of ReadExReq misses
767 system.cpu.l2cache.ReadExReq_misses::total 130786 # number of ReadExReq misses
768 system.cpu.l2cache.demand_misses::cpu.inst 7615 # number of demand (read+write) misses
769 system.cpu.l2cache.demand_misses::cpu.data 158632 # number of demand (read+write) misses
770 system.cpu.l2cache.demand_misses::total 166247 # number of demand (read+write) misses
771 system.cpu.l2cache.overall_misses::cpu.inst 7615 # number of overall misses
772 system.cpu.l2cache.overall_misses::cpu.data 158632 # number of overall misses
773 system.cpu.l2cache.overall_misses::total 166247 # number of overall misses
774 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 570946000 # number of ReadReq miss cycles
775 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2619731250 # number of ReadReq miss cycles
776 system.cpu.l2cache.ReadReq_miss_latency::total 3190677250 # number of ReadReq miss cycles
777 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13063717250 # number of ReadExReq miss cycles
778 system.cpu.l2cache.ReadExReq_miss_latency::total 13063717250 # number of ReadExReq miss cycles
779 system.cpu.l2cache.demand_miss_latency::cpu.inst 570946000 # number of demand (read+write) miss cycles
780 system.cpu.l2cache.demand_miss_latency::cpu.data 15683448500 # number of demand (read+write) miss cycles
781 system.cpu.l2cache.demand_miss_latency::total 16254394500 # number of demand (read+write) miss cycles
782 system.cpu.l2cache.overall_miss_latency::cpu.inst 570946000 # number of overall miss cycles
783 system.cpu.l2cache.overall_miss_latency::cpu.data 15683448500 # number of overall miss cycles
784 system.cpu.l2cache.overall_miss_latency::total 16254394500 # number of overall miss cycles
785 system.cpu.l2cache.ReadReq_accesses::cpu.inst 95639 # number of ReadReq accesses(hits+misses)
786 system.cpu.l2cache.ReadReq_accesses::cpu.data 62025 # number of ReadReq accesses(hits+misses)
787 system.cpu.l2cache.ReadReq_accesses::total 157664 # number of ReadReq accesses(hits+misses)
788 system.cpu.l2cache.Writeback_accesses::writebacks 168884 # number of Writeback accesses(hits+misses)
789 system.cpu.l2cache.Writeback_accesses::total 168884 # number of Writeback accesses(hits+misses)
790 system.cpu.l2cache.ReadExReq_accesses::cpu.data 143407 # number of ReadExReq accesses(hits+misses)
791 system.cpu.l2cache.ReadExReq_accesses::total 143407 # number of ReadExReq accesses(hits+misses)
792 system.cpu.l2cache.demand_accesses::cpu.inst 95639 # number of demand (read+write) accesses
793 system.cpu.l2cache.demand_accesses::cpu.data 205432 # number of demand (read+write) accesses
794 system.cpu.l2cache.demand_accesses::total 301071 # number of demand (read+write) accesses
795 system.cpu.l2cache.overall_accesses::cpu.inst 95639 # number of overall (read+write) accesses
796 system.cpu.l2cache.overall_accesses::cpu.data 205432 # number of overall (read+write) accesses
797 system.cpu.l2cache.overall_accesses::total 301071 # number of overall (read+write) accesses
798 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.079622 # miss rate for ReadReq accesses
799 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448948 # miss rate for ReadReq accesses
800 system.cpu.l2cache.ReadReq_miss_rate::total 0.224915 # miss rate for ReadReq accesses
801 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911992 # miss rate for ReadExReq accesses
802 system.cpu.l2cache.ReadExReq_miss_rate::total 0.911992 # miss rate for ReadExReq accesses
803 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.079622 # miss rate for demand accesses
804 system.cpu.l2cache.demand_miss_rate::cpu.data 0.772187 # miss rate for demand accesses
805 system.cpu.l2cache.demand_miss_rate::total 0.552185 # miss rate for demand accesses
806 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.079622 # miss rate for overall accesses
807 system.cpu.l2cache.overall_miss_rate::cpu.data 0.772187 # miss rate for overall accesses
808 system.cpu.l2cache.overall_miss_rate::total 0.552185 # miss rate for overall accesses
809 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74976.493762 # average ReadReq miss latency
810 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 94079.266322 # average ReadReq miss latency
811 system.cpu.l2cache.ReadReq_avg_miss_latency::total 89977.080455 # average ReadReq miss latency
812 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99886.205328 # average ReadExReq miss latency
813 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99886.205328 # average ReadExReq miss latency
814 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74976.493762 # average overall miss latency
815 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98866.864819 # average overall miss latency
816 system.cpu.l2cache.demand_avg_miss_latency::total 97772.558302 # average overall miss latency
817 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74976.493762 # average overall miss latency
818 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98866.864819 # average overall miss latency
819 system.cpu.l2cache.overall_avg_miss_latency::total 97772.558302 # average overall miss latency
820 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
821 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
822 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
823 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
824 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
825 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
826 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
827 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
828 system.cpu.l2cache.writebacks::writebacks 114023 # number of writebacks
829 system.cpu.l2cache.writebacks::total 114023 # number of writebacks
830 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7615 # number of ReadReq MSHR misses
831 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27846 # number of ReadReq MSHR misses
832 system.cpu.l2cache.ReadReq_mshr_misses::total 35461 # number of ReadReq MSHR misses
833 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130786 # number of ReadExReq MSHR misses
834 system.cpu.l2cache.ReadExReq_mshr_misses::total 130786 # number of ReadExReq MSHR misses
835 system.cpu.l2cache.demand_mshr_misses::cpu.inst 7615 # number of demand (read+write) MSHR misses
836 system.cpu.l2cache.demand_mshr_misses::cpu.data 158632 # number of demand (read+write) MSHR misses
837 system.cpu.l2cache.demand_mshr_misses::total 166247 # number of demand (read+write) MSHR misses
838 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7615 # number of overall MSHR misses
839 system.cpu.l2cache.overall_mshr_misses::cpu.data 158632 # number of overall MSHR misses
840 system.cpu.l2cache.overall_mshr_misses::total 166247 # number of overall MSHR misses
841 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 474721500 # number of ReadReq MSHR miss cycles
842 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2276772250 # number of ReadReq MSHR miss cycles
843 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2751493750 # number of ReadReq MSHR miss cycles
844 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11463934250 # number of ReadExReq MSHR miss cycles
845 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11463934250 # number of ReadExReq MSHR miss cycles
846 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 474721500 # number of demand (read+write) MSHR miss cycles
847 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13740706500 # number of demand (read+write) MSHR miss cycles
848 system.cpu.l2cache.demand_mshr_miss_latency::total 14215428000 # number of demand (read+write) MSHR miss cycles
849 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 474721500 # number of overall MSHR miss cycles
850 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13740706500 # number of overall MSHR miss cycles
851 system.cpu.l2cache.overall_mshr_miss_latency::total 14215428000 # number of overall MSHR miss cycles
852 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079622 # mshr miss rate for ReadReq accesses
853 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448948 # mshr miss rate for ReadReq accesses
854 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224915 # mshr miss rate for ReadReq accesses
855 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911992 # mshr miss rate for ReadExReq accesses
856 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911992 # mshr miss rate for ReadExReq accesses
857 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079622 # mshr miss rate for demand accesses
858 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772187 # mshr miss rate for demand accesses
859 system.cpu.l2cache.demand_mshr_miss_rate::total 0.552185 # mshr miss rate for demand accesses
860 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079622 # mshr miss rate for overall accesses
861 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772187 # mshr miss rate for overall accesses
862 system.cpu.l2cache.overall_mshr_miss_rate::total 0.552185 # mshr miss rate for overall accesses
863 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62340.315167 # average ReadReq mshr miss latency
864 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81762.991094 # average ReadReq mshr miss latency
865 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77592.108232 # average ReadReq mshr miss latency
866 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87654.139205 # average ReadExReq mshr miss latency
867 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87654.139205 # average ReadExReq mshr miss latency
868 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62340.315167 # average overall mshr miss latency
869 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86620.016768 # average overall mshr miss latency
870 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85507.876834 # average overall mshr miss latency
871 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62340.315167 # average overall mshr miss latency
872 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86620.016768 # average overall mshr miss latency
873 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85507.876834 # average overall mshr miss latency
874 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
875 system.cpu.dcache.tags.replacements 201336 # number of replacements
876 system.cpu.dcache.tags.tagsinuse 4071.830097 # Cycle average of tags in use
877 system.cpu.dcache.tags.total_refs 34080339 # Total number of references to valid blocks.
878 system.cpu.dcache.tags.sampled_refs 205432 # Sample count of references to valid blocks.
879 system.cpu.dcache.tags.avg_refs 165.895961 # Average number of references to valid blocks.
880 system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit.
881 system.cpu.dcache.tags.occ_blocks::cpu.data 4071.830097 # Average occupied blocks per requestor
882 system.cpu.dcache.tags.occ_percent::cpu.data 0.994099 # Average percentage of cache occupancy
883 system.cpu.dcache.tags.occ_percent::total 0.994099 # Average percentage of cache occupancy
884 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
885 system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
886 system.cpu.dcache.tags.age_task_id_blocks_1024::1 2800 # Occupied blocks per task id
887 system.cpu.dcache.tags.age_task_id_blocks_1024::2 1220 # Occupied blocks per task id
888 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
889 system.cpu.dcache.tags.tag_accesses 71000880 # Number of tag accesses
890 system.cpu.dcache.tags.data_accesses 71000880 # Number of data accesses
891 system.cpu.dcache.ReadReq_hits::cpu.data 20516147 # number of ReadReq hits
892 system.cpu.dcache.ReadReq_hits::total 20516147 # number of ReadReq hits
893 system.cpu.dcache.WriteReq_hits::cpu.data 13564136 # number of WriteReq hits
894 system.cpu.dcache.WriteReq_hits::total 13564136 # number of WriteReq hits
895 system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits
896 system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits
897 system.cpu.dcache.demand_hits::cpu.data 34080283 # number of demand (read+write) hits
898 system.cpu.dcache.demand_hits::total 34080283 # number of demand (read+write) hits
899 system.cpu.dcache.overall_hits::cpu.data 34080283 # number of overall hits
900 system.cpu.dcache.overall_hits::total 34080283 # number of overall hits
901 system.cpu.dcache.ReadReq_misses::cpu.data 268143 # number of ReadReq misses
902 system.cpu.dcache.ReadReq_misses::total 268143 # number of ReadReq misses
903 system.cpu.dcache.WriteReq_misses::cpu.data 1049241 # number of WriteReq misses
904 system.cpu.dcache.WriteReq_misses::total 1049241 # number of WriteReq misses
905 system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
906 system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
907 system.cpu.dcache.demand_misses::cpu.data 1317384 # number of demand (read+write) misses
908 system.cpu.dcache.demand_misses::total 1317384 # number of demand (read+write) misses
909 system.cpu.dcache.overall_misses::cpu.data 1317384 # number of overall misses
910 system.cpu.dcache.overall_misses::total 1317384 # number of overall misses
911 system.cpu.dcache.ReadReq_miss_latency::cpu.data 16930688495 # number of ReadReq miss cycles
912 system.cpu.dcache.ReadReq_miss_latency::total 16930688495 # number of ReadReq miss cycles
913 system.cpu.dcache.WriteReq_miss_latency::cpu.data 85479699625 # number of WriteReq miss cycles
914 system.cpu.dcache.WriteReq_miss_latency::total 85479699625 # number of WriteReq miss cycles
915 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
916 system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
917 system.cpu.dcache.demand_miss_latency::cpu.data 102410388120 # number of demand (read+write) miss cycles
918 system.cpu.dcache.demand_miss_latency::total 102410388120 # number of demand (read+write) miss cycles
919 system.cpu.dcache.overall_miss_latency::cpu.data 102410388120 # number of overall miss cycles
920 system.cpu.dcache.overall_miss_latency::total 102410388120 # number of overall miss cycles
921 system.cpu.dcache.ReadReq_accesses::cpu.data 20784290 # number of ReadReq accesses(hits+misses)
922 system.cpu.dcache.ReadReq_accesses::total 20784290 # number of ReadReq accesses(hits+misses)
923 system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
924 system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
925 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses)
926 system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses)
927 system.cpu.dcache.demand_accesses::cpu.data 35397667 # number of demand (read+write) accesses
928 system.cpu.dcache.demand_accesses::total 35397667 # number of demand (read+write) accesses
929 system.cpu.dcache.overall_accesses::cpu.data 35397667 # number of overall (read+write) accesses
930 system.cpu.dcache.overall_accesses::total 35397667 # number of overall (read+write) accesses
931 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012901 # miss rate for ReadReq accesses
932 system.cpu.dcache.ReadReq_miss_rate::total 0.012901 # miss rate for ReadReq accesses
933 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071800 # miss rate for WriteReq accesses
934 system.cpu.dcache.WriteReq_miss_rate::total 0.071800 # miss rate for WriteReq accesses
935 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017544 # miss rate for LoadLockedReq accesses
936 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017544 # miss rate for LoadLockedReq accesses
937 system.cpu.dcache.demand_miss_rate::cpu.data 0.037217 # miss rate for demand accesses
938 system.cpu.dcache.demand_miss_rate::total 0.037217 # miss rate for demand accesses
939 system.cpu.dcache.overall_miss_rate::cpu.data 0.037217 # miss rate for overall accesses
940 system.cpu.dcache.overall_miss_rate::total 0.037217 # miss rate for overall accesses
941 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63140.520152 # average ReadReq miss latency
942 system.cpu.dcache.ReadReq_avg_miss_latency::total 63140.520152 # average ReadReq miss latency
943 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81468.127556 # average WriteReq miss latency
944 system.cpu.dcache.WriteReq_avg_miss_latency::total 81468.127556 # average WriteReq miss latency
945 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
946 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
947 system.cpu.dcache.demand_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency
948 system.cpu.dcache.demand_avg_miss_latency::total 77737.689330 # average overall miss latency
949 system.cpu.dcache.overall_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency
950 system.cpu.dcache.overall_avg_miss_latency::total 77737.689330 # average overall miss latency
951 system.cpu.dcache.blocked_cycles::no_mshrs 6284356 # number of cycles access was blocked
952 system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked
953 system.cpu.dcache.blocked::no_mshrs 146253 # number of cycles access was blocked
954 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
955 system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.969074 # average number of cycles each access was blocked
956 system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked
957 system.cpu.dcache.fast_writes 0 # number of fast writes performed
958 system.cpu.dcache.cache_copies 0 # number of cache copies performed
959 system.cpu.dcache.writebacks::writebacks 168884 # number of writebacks
960 system.cpu.dcache.writebacks::total 168884 # number of writebacks
961 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206118 # number of ReadReq MSHR hits
962 system.cpu.dcache.ReadReq_mshr_hits::total 206118 # number of ReadReq MSHR hits
963 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905835 # number of WriteReq MSHR hits
964 system.cpu.dcache.WriteReq_mshr_hits::total 905835 # number of WriteReq MSHR hits
965 system.cpu.dcache.demand_mshr_hits::cpu.data 1111953 # number of demand (read+write) MSHR hits
966 system.cpu.dcache.demand_mshr_hits::total 1111953 # number of demand (read+write) MSHR hits
967 system.cpu.dcache.overall_mshr_hits::cpu.data 1111953 # number of overall MSHR hits
968 system.cpu.dcache.overall_mshr_hits::total 1111953 # number of overall MSHR hits
969 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62025 # number of ReadReq MSHR misses
970 system.cpu.dcache.ReadReq_mshr_misses::total 62025 # number of ReadReq MSHR misses
971 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses
972 system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses
973 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
974 system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
975 system.cpu.dcache.demand_mshr_misses::cpu.data 205431 # number of demand (read+write) MSHR misses
976 system.cpu.dcache.demand_mshr_misses::total 205431 # number of demand (read+write) MSHR misses
977 system.cpu.dcache.overall_mshr_misses::cpu.data 205431 # number of overall MSHR misses
978 system.cpu.dcache.overall_mshr_misses::total 205431 # number of overall MSHR misses
979 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3026595754 # number of ReadReq MSHR miss cycles
980 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3026595754 # number of ReadReq MSHR miss cycles
981 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13337681700 # number of WriteReq MSHR miss cycles
982 system.cpu.dcache.WriteReq_mshr_miss_latency::total 13337681700 # number of WriteReq MSHR miss cycles
983 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
984 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
985 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16364277454 # number of demand (read+write) MSHR miss cycles
986 system.cpu.dcache.demand_mshr_miss_latency::total 16364277454 # number of demand (read+write) MSHR miss cycles
987 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16364277454 # number of overall MSHR miss cycles
988 system.cpu.dcache.overall_mshr_miss_latency::total 16364277454 # number of overall MSHR miss cycles
989 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses
990 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses
991 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
992 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
993 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017544 # mshr miss rate for LoadLockedReq accesses
994 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017544 # mshr miss rate for LoadLockedReq accesses
995 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses
996 system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses
997 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses
998 system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses
999 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587 # average ReadReq mshr miss latency
1000 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587 # average ReadReq mshr miss latency
1001 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153 # average WriteReq mshr miss latency
1002 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153 # average WriteReq mshr miss latency
1003 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
1004 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
1005 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency
1006 system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency
1007 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency
1008 system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency
1009 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1011 ---------- End Simulation Statistics ----------
projects / gem5.git / blob