tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=cpu membus physmem
  12 boot_osflags=a
  13 init_param=0
  14 kernel=
  15 load_addr_mask=1099511627775
  16 mem_mode=atomic
  17 memories=system.physmem
  18 num_work_ids=16
  19 physmem=system.physmem
  20 readfile=
  21 symbolfile=
  22 work_begin_ckpt_count=0
  23 work_begin_cpu_id_exit=-1
  24 work_begin_exit_count=0
  25 work_cpus_ckpt_count=0
  26 work_end_ckpt_count=0
  27 work_end_exit_count=0
  28 work_item_id=-1
  29 system_port=system.membus.port[0]
  30
  31 [system.cpu]
  32 type=TimingSimpleCPU
  33 children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
  34 checker=Null
  35 clock=500
  36 cpu_id=0
  37 defer_registration=false
  38 do_checkpoint_insts=true
  39 do_quiesce=true
  40 do_statistics_insts=true
  41 dtb=system.cpu.dtb
  42 function_trace=false
  43 function_trace_start=0
  44 interrupts=system.cpu.interrupts
  45 itb=system.cpu.itb
  46 max_insts_all_threads=0
  47 max_insts_any_thread=0
  48 max_loads_all_threads=0
  49 max_loads_any_thread=0
  50 numThreads=1
  51 phase=0
  52 profile=0
  53 progress_interval=0
  54 system=system
  55 tracer=system.cpu.tracer
  56 workload=system.cpu.workload
  57 dcache_port=system.cpu.dcache.cpu_side
  58 icache_port=system.cpu.icache.cpu_side
  59
  60 [system.cpu.dcache]
  61 type=BaseCache
  62 addr_range=0:18446744073709551615
  63 assoc=2
  64 block_size=64
  65 forward_snoops=true
  66 hash_delay=1
  67 is_top_level=true
  68 latency=1000
  69 max_miss_count=0
  70 mshrs=10
  71 prefetch_on_access=false
  72 prefetcher=Null
  73 prioritizeRequests=false
  74 repl=Null
  75 size=262144
  76 subblock_size=0
  77 system=system
  78 tgts_per_mshr=5
  79 trace_addr=0
  80 two_queue=false
  81 write_buffers=8
  82 cpu_side=system.cpu.dcache_port
  83 mem_side=system.cpu.toL2Bus.port[1]
  84
  85 [system.cpu.dtb]
  86 type=AlphaTLB
  87 size=64
  88
  89 [system.cpu.icache]
  90 type=BaseCache
  91 addr_range=0:18446744073709551615
  92 assoc=2
  93 block_size=64
  94 forward_snoops=true
  95 hash_delay=1
  96 is_top_level=true
  97 latency=1000
  98 max_miss_count=0
  99 mshrs=10
 100 prefetch_on_access=false
 101 prefetcher=Null
 102 prioritizeRequests=false
 103 repl=Null
 104 size=131072
 105 subblock_size=0
 106 system=system
 107 tgts_per_mshr=5
 108 trace_addr=0
 109 two_queue=false
 110 write_buffers=8
 111 cpu_side=system.cpu.icache_port
 112 mem_side=system.cpu.toL2Bus.port[0]
 113
 114 [system.cpu.interrupts]
 115 type=AlphaInterrupts
 116
 117 [system.cpu.itb]
 118 type=AlphaTLB
 119 size=48
 120
 121 [system.cpu.l2cache]
 122 type=BaseCache
 123 addr_range=0:18446744073709551615
 124 assoc=2
 125 block_size=64
 126 forward_snoops=true
 127 hash_delay=1
 128 is_top_level=false
 129 latency=10000
 130 max_miss_count=0
 131 mshrs=10
 132 prefetch_on_access=false
 133 prefetcher=Null
 134 prioritizeRequests=false
 135 repl=Null
 136 size=2097152
 137 subblock_size=0
 138 system=system
 139 tgts_per_mshr=5
 140 trace_addr=0
 141 two_queue=false
 142 write_buffers=8
 143 cpu_side=system.cpu.toL2Bus.port[2]
 144 mem_side=system.membus.port[2]
 145
 146 [system.cpu.toL2Bus]
 147 type=Bus
 148 block_size=64
 149 bus_id=0
 150 clock=1000
 151 header_cycles=1
 152 use_default_range=false
 153 width=64
 154 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 155
 156 [system.cpu.tracer]
 157 type=ExeTracer
 158
 159 [system.cpu.workload]
 160 type=LiveProcess
 161 cmd=vortex lendian.raw
 162 cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
 163 egid=100
 164 env=
 165 errout=cerr
 166 euid=100
 167 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 168 gid=100
 169 input=cin
 170 max_stack_size=67108864
 171 output=cout
 172 pid=100
 173 ppid=99
 174 simpoint=0
 175 system=system
 176 uid=100
 177
 178 [system.membus]
 179 type=Bus
 180 block_size=64
 181 bus_id=0
 182 clock=1000
 183 header_cycles=1
 184 use_default_range=false
 185 width=64
 186 port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 187
 188 [system.physmem]
 189 type=PhysicalMemory
 190 file=
 191 latency=30000
 192 latency_var=0
 193 null=false
 194 range=0:134217727
 195 zero=false
 196 port=system.membus.port[1]
 197