2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.056961 # Number of seconds simulated
4 sim_ticks 56960656500 # Number of ticks simulated
5 final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 189048 # Simulator instruction rate (inst/s)
8 host_op_rate 241764 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 151847358 # Simulator tick rate (ticks/s)
10 host_mem_usage 327812 # Number of bytes of host memory used
11 host_seconds 375.12 # Real time elapsed on the host
12 sim_insts 70915128 # Number of instructions simulated
13 sim_ops 90690084 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 128278 # Number of read requests accepted
40 system.physmem.writeReqs 86211 # Number of write requests accepted
41 system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 8061 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 8314 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 8140 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 8284 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 8402 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 8056 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 7915 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 8035 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 7586 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 7763 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 7871 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 7867 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 7968 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 7962 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 5394 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 5465 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 5335 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 5367 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 5560 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 5259 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 5181 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 5155 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 5101 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 5703 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 56960624500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 128278 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 86211 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes
217 system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads
218 system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads
219 system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads
230 system.physmem.totQLat 1678352000 # Total ticks spent queuing
231 system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM
232 system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers
233 system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst
234 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
235 system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst
236 system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s
237 system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s
238 system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s
239 system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s
240 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
241 system.physmem.busUtil 1.88 # Data bus utilization in percentage
242 system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
243 system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
244 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
245 system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
246 system.physmem.readRowHits 111810 # Number of row buffer hits during reads
247 system.physmem.writeRowHits 63793 # Number of row buffer hits during writes
248 system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads
249 system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
250 system.physmem.avgGap 265564.32 # Average gap between requests
251 system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined
252 system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ)
253 system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ)
254 system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ)
255 system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ)
256 system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ)
257 system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ)
258 system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ)
259 system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ)
260 system.physmem_0.averagePower 708.261877 # Core power per rank (mW)
261 system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states
262 system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states
263 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
264 system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states
265 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
266 system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ)
267 system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ)
268 system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ)
269 system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ)
270 system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ)
271 system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ)
272 system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ)
273 system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ)
274 system.physmem_1.averagePower 706.217322 # Core power per rank (mW)
275 system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states
276 system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states
277 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
278 system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states
279 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
280 system.cpu.branchPred.lookups 14800638 # Number of BP lookups
281 system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted
282 system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect
283 system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups
284 system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits
285 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
286 system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage
287 system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target.
288 system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
289 system.cpu_clk_domain.clock 500 # Clock period in ticks
290 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
291 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
292 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
293 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
297 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
298 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
299 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
300 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
301 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
302 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
303 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
304 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
305 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
306 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
307 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
308 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
309 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
310 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
311 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
312 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
313 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
314 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
315 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
316 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
317 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
318 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
319 system.cpu.dtb.walker.walks 0 # Table walker walks requested
320 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
321 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
322 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
323 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
324 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
326 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
327 system.cpu.dtb.inst_hits 0 # ITB inst hits
328 system.cpu.dtb.inst_misses 0 # ITB inst misses
329 system.cpu.dtb.read_hits 0 # DTB read hits
330 system.cpu.dtb.read_misses 0 # DTB read misses
331 system.cpu.dtb.write_hits 0 # DTB write hits
332 system.cpu.dtb.write_misses 0 # DTB write misses
333 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
334 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
335 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
336 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
337 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
338 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
339 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
340 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
341 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
342 system.cpu.dtb.read_accesses 0 # DTB read accesses
343 system.cpu.dtb.write_accesses 0 # DTB write accesses
344 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
345 system.cpu.dtb.hits 0 # DTB hits
346 system.cpu.dtb.misses 0 # DTB misses
347 system.cpu.dtb.accesses 0 # DTB accesses
348 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
349 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
350 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
351 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
352 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
353 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
354 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
355 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
356 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
357 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
358 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
359 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
360 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
361 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
362 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
363 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
364 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
365 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
366 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
367 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
368 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
369 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
370 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
372 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
373 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
374 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
375 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
376 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
377 system.cpu.itb.walker.walks 0 # Table walker walks requested
378 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
379 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
380 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
381 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
382 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
383 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
384 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
385 system.cpu.itb.inst_hits 0 # ITB inst hits
386 system.cpu.itb.inst_misses 0 # ITB inst misses
387 system.cpu.itb.read_hits 0 # DTB read hits
388 system.cpu.itb.read_misses 0 # DTB read misses
389 system.cpu.itb.write_hits 0 # DTB write hits
390 system.cpu.itb.write_misses 0 # DTB write misses
391 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
392 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
393 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
394 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
395 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
396 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
397 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
398 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
399 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
400 system.cpu.itb.read_accesses 0 # DTB read accesses
401 system.cpu.itb.write_accesses 0 # DTB write accesses
402 system.cpu.itb.inst_accesses 0 # ITB inst accesses
403 system.cpu.itb.hits 0 # DTB hits
404 system.cpu.itb.misses 0 # DTB misses
405 system.cpu.itb.accesses 0 # DTB accesses
406 system.cpu.workload.num_syscalls 1946 # Number of system calls
407 system.cpu.numCycles 113921313 # number of cpu cycles simulated
408 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
409 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
410 system.cpu.committedInsts 70915128 # Number of instructions committed
411 system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed
412 system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit
413 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
414 system.cpu.cpi 1.606446 # CPI: cycles per instruction
415 system.cpu.ipc 0.622492 # IPC: instructions per cycle
416 system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked
417 system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped
418 system.cpu.dcache.tags.replacements 156436 # number of replacements
419 system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use
420 system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks.
421 system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks.
422 system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks.
423 system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit.
424 system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor
425 system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
426 system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
427 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
428 system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
429 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id
430 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id
431 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
432 system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses
433 system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses
434 system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits
435 system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits
436 system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits
437 system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits
438 system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits
439 system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits
440 system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
441 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
442 system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
443 system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
444 system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits
445 system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits
446 system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits
447 system.cpu.dcache.overall_hits::total 42592421 # number of overall hits
448 system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses
449 system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses
450 system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses
451 system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses
452 system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses
453 system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses
454 system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses
455 system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses
456 system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses
457 system.cpu.dcache.overall_misses::total 303842 # number of overall misses
458 system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles
459 system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles
460 system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles
461 system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles
462 system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles
463 system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles
464 system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles
465 system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles
466 system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses)
467 system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses)
468 system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
469 system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
470 system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses)
471 system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses)
472 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
473 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
474 system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
475 system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
476 system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses
477 system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses
478 system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses
479 system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses
480 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses
481 system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses
482 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
483 system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
484 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses
485 system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses
486 system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses
487 system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses
488 system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses
489 system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses
490 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency
491 system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency
492 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency
493 system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency
494 system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency
495 system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency
496 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency
497 system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency
498 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
499 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
501 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
502 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
503 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504 system.cpu.dcache.fast_writes 0 # number of fast writes performed
505 system.cpu.dcache.cache_copies 0 # number of cache copies performed
506 system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks
507 system.cpu.dcache.writebacks::total 128377 # number of writebacks
508 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits
509 system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits
510 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits
511 system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits
512 system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits
513 system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits
514 system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits
515 system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits
516 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses
517 system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses
518 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses
519 system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses
520 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses
521 system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses
522 system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses
523 system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses
524 system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses
525 system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses
526 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles
527 system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles
528 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles
529 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles
530 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles
531 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles
532 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles
533 system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles
534 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles
535 system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles
536 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
537 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
538 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
539 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
540 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses
541 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses
542 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
543 system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
544 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
545 system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
546 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency
547 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency
548 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency
549 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency
550 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency
551 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency
552 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency
553 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency
554 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency
555 system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency
556 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
557 system.cpu.icache.tags.replacements 42868 # number of replacements
558 system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use
559 system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks.
560 system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks.
561 system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks.
562 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
563 system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor
564 system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy
565 system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy
566 system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
567 system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
568 system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id
569 system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
570 system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id
571 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
572 system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses
573 system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses
574 system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits
575 system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits
576 system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits
577 system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits
578 system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits
579 system.cpu.icache.overall_hits::total 24941232 # number of overall hits
580 system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses
581 system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses
582 system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses
583 system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses
584 system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses
585 system.cpu.icache.overall_misses::total 44911 # number of overall misses
586 system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles
587 system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles
588 system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles
589 system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles
590 system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles
591 system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles
592 system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses)
593 system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses)
594 system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses
595 system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses
596 system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses
597 system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses
598 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses
599 system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses
600 system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses
601 system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses
602 system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses
603 system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses
604 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency
605 system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency
606 system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency
607 system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency
608 system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency
609 system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency
610 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
611 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
612 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
613 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
614 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
615 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
616 system.cpu.icache.fast_writes 0 # number of fast writes performed
617 system.cpu.icache.cache_copies 0 # number of cache copies performed
618 system.cpu.icache.writebacks::writebacks 42868 # number of writebacks
619 system.cpu.icache.writebacks::total 42868 # number of writebacks
620 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44911 # number of ReadReq MSHR misses
621 system.cpu.icache.ReadReq_mshr_misses::total 44911 # number of ReadReq MSHR misses
622 system.cpu.icache.demand_mshr_misses::cpu.inst 44911 # number of demand (read+write) MSHR misses
623 system.cpu.icache.demand_mshr_misses::total 44911 # number of demand (read+write) MSHR misses
624 system.cpu.icache.overall_mshr_misses::cpu.inst 44911 # number of overall MSHR misses
625 system.cpu.icache.overall_mshr_misses::total 44911 # number of overall MSHR misses
626 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 851815000 # number of ReadReq MSHR miss cycles
627 system.cpu.icache.ReadReq_mshr_miss_latency::total 851815000 # number of ReadReq MSHR miss cycles
628 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 851815000 # number of demand (read+write) MSHR miss cycles
629 system.cpu.icache.demand_mshr_miss_latency::total 851815000 # number of demand (read+write) MSHR miss cycles
630 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 851815000 # number of overall MSHR miss cycles
631 system.cpu.icache.overall_mshr_miss_latency::total 851815000 # number of overall MSHR miss cycles
632 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses
633 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses
634 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses
635 system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses
636 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses
637 system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses
638 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18966.734208 # average ReadReq mshr miss latency
639 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18966.734208 # average ReadReq mshr miss latency
640 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency
641 system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency
642 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency
643 system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency
644 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
645 system.cpu.l2cache.tags.replacements 96386 # number of replacements
646 system.cpu.l2cache.tags.tagsinuse 29871.418055 # Cycle average of tags in use
647 system.cpu.l2cache.tags.total_refs 162162 # Total number of references to valid blocks.
648 system.cpu.l2cache.tags.sampled_refs 127539 # Sample count of references to valid blocks.
649 system.cpu.l2cache.tags.avg_refs 1.271470 # Average number of references to valid blocks.
650 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
651 system.cpu.l2cache.tags.occ_blocks::writebacks 26782.423909 # Average occupied blocks per requestor
652 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.670582 # Average occupied blocks per requestor
653 system.cpu.l2cache.tags.occ_blocks::cpu.data 1657.323564 # Average occupied blocks per requestor
654 system.cpu.l2cache.tags.occ_percent::writebacks 0.817335 # Average percentage of cache occupancy
655 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043691 # Average percentage of cache occupancy
656 system.cpu.l2cache.tags.occ_percent::cpu.data 0.050578 # Average percentage of cache occupancy
657 system.cpu.l2cache.tags.occ_percent::total 0.911603 # Average percentage of cache occupancy
658 system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id
659 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
660 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id
661 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id
662 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id
663 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id
664 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id
665 system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses
666 system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses
667 system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits
668 system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits
669 system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits
670 system.cpu.l2cache.WritebackClean_hits::total 39288 # number of WritebackClean hits
671 system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
672 system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
673 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40441 # number of ReadCleanReq hits
674 system.cpu.l2cache.ReadCleanReq_hits::total 40441 # number of ReadCleanReq hits
675 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31897 # number of ReadSharedReq hits
676 system.cpu.l2cache.ReadSharedReq_hits::total 31897 # number of ReadSharedReq hits
677 system.cpu.l2cache.demand_hits::cpu.inst 40441 # number of demand (read+write) hits
678 system.cpu.l2cache.demand_hits::cpu.data 36648 # number of demand (read+write) hits
679 system.cpu.l2cache.demand_hits::total 77089 # number of demand (read+write) hits
680 system.cpu.l2cache.overall_hits::cpu.inst 40441 # number of overall hits
681 system.cpu.l2cache.overall_hits::cpu.data 36648 # number of overall hits
682 system.cpu.l2cache.overall_hits::total 77089 # number of overall hits
683 system.cpu.l2cache.ReadExReq_misses::cpu.data 102277 # number of ReadExReq misses
684 system.cpu.l2cache.ReadExReq_misses::total 102277 # number of ReadExReq misses
685 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses
686 system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses
687 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21607 # number of ReadSharedReq misses
688 system.cpu.l2cache.ReadSharedReq_misses::total 21607 # number of ReadSharedReq misses
689 system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses
690 system.cpu.l2cache.demand_misses::cpu.data 123884 # number of demand (read+write) misses
691 system.cpu.l2cache.demand_misses::total 128354 # number of demand (read+write) misses
692 system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses
693 system.cpu.l2cache.overall_misses::cpu.data 123884 # number of overall misses
694 system.cpu.l2cache.overall_misses::total 128354 # number of overall misses
695 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277973500 # number of ReadExReq miss cycles
696 system.cpu.l2cache.ReadExReq_miss_latency::total 8277973500 # number of ReadExReq miss cycles
697 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 355961000 # number of ReadCleanReq miss cycles
698 system.cpu.l2cache.ReadCleanReq_miss_latency::total 355961000 # number of ReadCleanReq miss cycles
699 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1870485000 # number of ReadSharedReq miss cycles
700 system.cpu.l2cache.ReadSharedReq_miss_latency::total 1870485000 # number of ReadSharedReq miss cycles
701 system.cpu.l2cache.demand_miss_latency::cpu.inst 355961000 # number of demand (read+write) miss cycles
702 system.cpu.l2cache.demand_miss_latency::cpu.data 10148458500 # number of demand (read+write) miss cycles
703 system.cpu.l2cache.demand_miss_latency::total 10504419500 # number of demand (read+write) miss cycles
704 system.cpu.l2cache.overall_miss_latency::cpu.inst 355961000 # number of overall miss cycles
705 system.cpu.l2cache.overall_miss_latency::cpu.data 10148458500 # number of overall miss cycles
706 system.cpu.l2cache.overall_miss_latency::total 10504419500 # number of overall miss cycles
707 system.cpu.l2cache.WritebackDirty_accesses::writebacks 128377 # number of WritebackDirty accesses(hits+misses)
708 system.cpu.l2cache.WritebackDirty_accesses::total 128377 # number of WritebackDirty accesses(hits+misses)
709 system.cpu.l2cache.WritebackClean_accesses::writebacks 39288 # number of WritebackClean accesses(hits+misses)
710 system.cpu.l2cache.WritebackClean_accesses::total 39288 # number of WritebackClean accesses(hits+misses)
711 system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses)
712 system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses)
713 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44911 # number of ReadCleanReq accesses(hits+misses)
714 system.cpu.l2cache.ReadCleanReq_accesses::total 44911 # number of ReadCleanReq accesses(hits+misses)
715 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53504 # number of ReadSharedReq accesses(hits+misses)
716 system.cpu.l2cache.ReadSharedReq_accesses::total 53504 # number of ReadSharedReq accesses(hits+misses)
717 system.cpu.l2cache.demand_accesses::cpu.inst 44911 # number of demand (read+write) accesses
718 system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses
719 system.cpu.l2cache.demand_accesses::total 205443 # number of demand (read+write) accesses
720 system.cpu.l2cache.overall_accesses::cpu.inst 44911 # number of overall (read+write) accesses
721 system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses
722 system.cpu.l2cache.overall_accesses::total 205443 # number of overall (read+write) accesses
723 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955610 # miss rate for ReadExReq accesses
724 system.cpu.l2cache.ReadExReq_miss_rate::total 0.955610 # miss rate for ReadExReq accesses
725 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses
726 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses
727 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses
728 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses
729 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses
730 system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses
731 system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses
732 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses
733 system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses
734 system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses
735 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency
736 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency
737 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency
738 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency
739 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency
740 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency
741 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency
742 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency
743 system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency
744 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency
745 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency
746 system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency
747 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
748 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
749 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
750 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
751 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
752 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
753 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
754 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
755 system.cpu.l2cache.writebacks::writebacks 86211 # number of writebacks
756 system.cpu.l2cache.writebacks::total 86211 # number of writebacks
757 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
758 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
759 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
760 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
761 system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
762 system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
763 system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
764 system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
765 system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
766 system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
767 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
768 system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
769 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses
770 system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses
771 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses
772 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses
773 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses
774 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses
775 system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses
776 system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses
777 system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses
778 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses
779 system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses
780 system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses
781 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles
782 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles
783 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles
784 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles
785 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles
786 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles
787 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles
788 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles
789 system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles
790 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles
791 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles
792 system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles
793 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
794 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
795 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses
796 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses
797 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses
798 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses
799 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses
800 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses
801 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses
802 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses
803 system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses
804 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses
805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses
806 system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses
807 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency
808 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency
809 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency
810 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency
811 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency
812 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency
813 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency
814 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency
815 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency
816 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency
817 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency
818 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency
819 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
820 system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter.
821 system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
822 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
823 system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter.
824 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
825 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
826 system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution
827 system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution
828 system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution
829 system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution
830 system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution
831 system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution
832 system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution
833 system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution
834 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes)
835 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes)
836 system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes)
837 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes)
838 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes)
839 system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes)
840 system.cpu.toL2Bus.snoops 96386 # Total snoops (count)
841 system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram
842 system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram
843 system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram
844 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
845 system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram
846 system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram
847 system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
848 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
849 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
850 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
851 system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram
852 system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks)
853 system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
854 system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks)
855 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
856 system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks)
857 system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
858 system.membus.trans_dist::ReadResp 26001 # Transaction distribution
859 system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution
860 system.membus.trans_dist::CleanEvict 6908 # Transaction distribution
861 system.membus.trans_dist::ReadExReq 102277 # Transaction distribution
862 system.membus.trans_dist::ReadExResp 102277 # Transaction distribution
863 system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution
864 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes)
865 system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes)
866 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes)
867 system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes)
868 system.membus.snoops 0 # Total snoops (count)
869 system.membus.snoop_fanout::samples 221397 # Request fanout histogram
870 system.membus.snoop_fanout::mean 0 # Request fanout histogram
871 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
872 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
873 system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram
874 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
875 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
876 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
877 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
878 system.membus.snoop_fanout::total 221397 # Request fanout histogram
879 system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks)
880 system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
881 system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks)
882 system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
884 ---------- End Simulation Statistics ----------
projects / gem5.git / blob