2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.057717 # Number of seconds simulated
4 sim_ticks 57716694500 # Number of ticks simulated
5 final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 194770 # Simulator instruction rate (inst/s)
8 host_op_rate 249082 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 158520150 # Simulator tick rate (ticks/s)
10 host_mem_usage 322420 # Number of bytes of host memory used
11 host_seconds 364.10 # Real time elapsed on the host
12 sim_insts 70915128 # Number of instructions simulated
13 sim_ops 90690084 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 324096 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 8247488 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 324096 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 324096 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 5064 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 128867 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 5615290 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 137280765 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 142896056 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 5615290 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 5615290 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 93092511 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 93092511 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 93092511 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 5615290 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 137280765 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 235988567 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 128867 # Number of read requests accepted
40 system.physmem.writeReqs 83953 # Number of write requests accepted
41 system.physmem.readBursts 128867 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 8247040 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 5371776 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 8247488 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 8159 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 8373 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 8230 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 8170 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 8318 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 8449 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 7972 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 8072 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 7639 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 7818 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 7829 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 7882 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 7878 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 5185 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 5518 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 5200 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 5254 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 57716659500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 128867 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 83953 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 116721 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 12117 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 639 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 4066 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 5054 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 5149 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 5174 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 5175 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 5177 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 5199 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 5195 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 5335 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 5261 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 5300 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 5730 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 5307 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 5162 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 38389 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 354.703274 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 215.932875 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 335.531195 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 12049 31.39% 31.39% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 8167 21.27% 52.66% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 4156 10.83% 63.49% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 2841 7.40% 70.89% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 2531 6.59% 77.48% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 1630 4.25% 81.73% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 1300 3.39% 85.11% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 1165 3.03% 88.15% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 4550 11.85% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 38389 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 24.991854 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 361.399783 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
218 system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
219 system.physmem.wrPerTurnAround::mean 16.278898 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::gmean 16.261929 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::stdev 0.774840 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::16 4519 87.65% 87.65% # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::17 7 0.14% 87.78% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::18 495 9.60% 97.38% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::19 111 2.15% 99.53% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::20 19 0.37% 99.90% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
230 system.physmem.totQLat 1645819000 # Total ticks spent queuing
231 system.physmem.totMemAccLat 4061944000 # Total ticks spent from burst creation until serviced by the DRAM
232 system.physmem.totBusLat 644300000 # Total ticks spent in databus transfers
233 system.physmem.avgQLat 12772.15 # Average queueing delay per DRAM burst
234 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
235 system.physmem.avgMemAccLat 31522.15 # Average memory access latency per DRAM burst
236 system.physmem.avgRdBW 142.89 # Average DRAM read bandwidth in MiByte/s
237 system.physmem.avgWrBW 93.07 # Average achieved write bandwidth in MiByte/s
238 system.physmem.avgRdBWSys 142.90 # Average system read bandwidth in MiByte/s
239 system.physmem.avgWrBWSys 93.09 # Average system write bandwidth in MiByte/s
240 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
241 system.physmem.busUtil 1.84 # Data bus utilization in percentage
242 system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads
243 system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
244 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
245 system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing
246 system.physmem.readRowHits 112172 # Number of row buffer hits during reads
247 system.physmem.writeRowHits 62224 # Number of row buffer hits during writes
248 system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
249 system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes
250 system.physmem.avgGap 271199.41 # Average gap between requests
251 system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
252 system.physmem_0.actEnergy 151063920 # Energy for activate commands per rank (pJ)
253 system.physmem_0.preEnergy 82425750 # Energy for precharge commands per rank (pJ)
254 system.physmem_0.readEnergy 512577000 # Energy for read commands per rank (pJ)
255 system.physmem_0.writeEnergy 272309040 # Energy for write commands per rank (pJ)
256 system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
257 system.physmem_0.actBackEnergy 11829284955 # Energy for active background per rank (pJ)
258 system.physmem_0.preBackEnergy 24250601250 # Energy for precharge background per rank (pJ)
259 system.physmem_0.totalEnergy 40867708635 # Total energy per rank (pJ)
260 system.physmem_0.averagePower 708.132582 # Core power per rank (mW)
261 system.physmem_0.memoryStateTime::IDLE 40213391000 # Time in different power states
262 system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states
263 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
264 system.physmem_0.memoryStateTime::ACT 15571447750 # Time in different power states
265 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
266 system.physmem_1.actEnergy 139058640 # Energy for activate commands per rank (pJ)
267 system.physmem_1.preEnergy 75875250 # Energy for precharge commands per rank (pJ)
268 system.physmem_1.readEnergy 492008400 # Energy for read commands per rank (pJ)
269 system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ)
270 system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
271 system.physmem_1.actBackEnergy 11209873365 # Energy for active background per rank (pJ)
272 system.physmem_1.preBackEnergy 24793944750 # Energy for precharge background per rank (pJ)
273 system.physmem_1.totalEnergy 40751686725 # Total energy per rank (pJ)
274 system.physmem_1.averagePower 706.122220 # Core power per rank (mW)
275 system.physmem_1.memoryStateTime::IDLE 41121510500 # Time in different power states
276 system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states
277 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
278 system.physmem_1.memoryStateTime::ACT 14663764500 # Time in different power states
279 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
280 system.cpu.branchPred.lookups 14827145 # Number of BP lookups
281 system.cpu.branchPred.condPredicted 9920468 # Number of conditional branches predicted
282 system.cpu.branchPred.condIncorrect 395132 # Number of conditional branches incorrect
283 system.cpu.branchPred.BTBLookups 9565987 # Number of BTB lookups
284 system.cpu.branchPred.BTBHits 6746821 # Number of BTB hits
285 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
286 system.cpu.branchPred.BTBHitPct 70.529272 # BTB Hit Percentage
287 system.cpu.branchPred.usedRAS 1718856 # Number of times the RAS was used to get a target.
288 system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
289 system.cpu_clk_domain.clock 500 # Clock period in ticks
290 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
291 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
292 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
293 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
297 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
298 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
299 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
300 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
301 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
302 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
303 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
304 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
305 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
306 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
307 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
308 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
309 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
310 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
311 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
312 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
313 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
314 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
315 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
316 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
317 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
318 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
319 system.cpu.dtb.walker.walks 0 # Table walker walks requested
320 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
321 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
322 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
323 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
324 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
326 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
327 system.cpu.dtb.inst_hits 0 # ITB inst hits
328 system.cpu.dtb.inst_misses 0 # ITB inst misses
329 system.cpu.dtb.read_hits 0 # DTB read hits
330 system.cpu.dtb.read_misses 0 # DTB read misses
331 system.cpu.dtb.write_hits 0 # DTB write hits
332 system.cpu.dtb.write_misses 0 # DTB write misses
333 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
334 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
335 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
336 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
337 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
338 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
339 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
340 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
341 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
342 system.cpu.dtb.read_accesses 0 # DTB read accesses
343 system.cpu.dtb.write_accesses 0 # DTB write accesses
344 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
345 system.cpu.dtb.hits 0 # DTB hits
346 system.cpu.dtb.misses 0 # DTB misses
347 system.cpu.dtb.accesses 0 # DTB accesses
348 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
349 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
350 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
351 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
352 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
353 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
354 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
355 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
356 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
357 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
358 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
359 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
360 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
361 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
362 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
363 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
364 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
365 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
366 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
367 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
368 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
369 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
370 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
372 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
373 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
374 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
375 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
376 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
377 system.cpu.itb.walker.walks 0 # Table walker walks requested
378 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
379 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
380 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
381 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
382 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
383 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
384 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
385 system.cpu.itb.inst_hits 0 # ITB inst hits
386 system.cpu.itb.inst_misses 0 # ITB inst misses
387 system.cpu.itb.read_hits 0 # DTB read hits
388 system.cpu.itb.read_misses 0 # DTB read misses
389 system.cpu.itb.write_hits 0 # DTB write hits
390 system.cpu.itb.write_misses 0 # DTB write misses
391 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
392 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
393 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
394 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
395 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
396 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
397 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
398 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
399 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
400 system.cpu.itb.read_accesses 0 # DTB read accesses
401 system.cpu.itb.write_accesses 0 # DTB write accesses
402 system.cpu.itb.inst_accesses 0 # ITB inst accesses
403 system.cpu.itb.hits 0 # DTB hits
404 system.cpu.itb.misses 0 # DTB misses
405 system.cpu.itb.accesses 0 # DTB accesses
406 system.cpu.workload.num_syscalls 1946 # Number of system calls
407 system.cpu.numCycles 115433389 # number of cpu cycles simulated
408 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
409 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
410 system.cpu.committedInsts 70915128 # Number of instructions committed
411 system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed
412 system.cpu.discardedOps 1146778 # Number of ops (including micro ops) which were discarded before commit
413 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
414 system.cpu.cpi 1.627768 # CPI: cycles per instruction
415 system.cpu.ipc 0.614338 # IPC: instructions per cycle
416 system.cpu.tickCycles 96895866 # Number of cycles that the object actually ticked
417 system.cpu.idleCycles 18537523 # Total number of cycles that the object has spent stopped
418 system.cpu.dcache.tags.replacements 156436 # number of replacements
419 system.cpu.dcache.tags.tagsinuse 4067.344190 # Cycle average of tags in use
420 system.cpu.dcache.tags.total_refs 42626825 # Total number of references to valid blocks.
421 system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks.
422 system.cpu.dcache.tags.avg_refs 265.534753 # Average number of references to valid blocks.
423 system.cpu.dcache.tags.warmup_cycle 829717250 # Cycle when the warmup percentage was hit.
424 system.cpu.dcache.tags.occ_blocks::cpu.data 4067.344190 # Average occupied blocks per requestor
425 system.cpu.dcache.tags.occ_percent::cpu.data 0.993004 # Average percentage of cache occupancy
426 system.cpu.dcache.tags.occ_percent::total 0.993004 # Average percentage of cache occupancy
427 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
428 system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
429 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
430 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2911 # Occupied blocks per task id
431 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
432 system.cpu.dcache.tags.tag_accesses 86020072 # Number of tag accesses
433 system.cpu.dcache.tags.data_accesses 86020072 # Number of data accesses
434 system.cpu.dcache.ReadReq_hits::cpu.data 22868301 # number of ReadReq hits
435 system.cpu.dcache.ReadReq_hits::total 22868301 # number of ReadReq hits
436 system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits
437 system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits
438 system.cpu.dcache.SoftPFReq_hits::cpu.data 84507 # number of SoftPFReq hits
439 system.cpu.dcache.SoftPFReq_hits::total 84507 # number of SoftPFReq hits
440 system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
441 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
442 system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
443 system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
444 system.cpu.dcache.demand_hits::cpu.data 42510480 # number of demand (read+write) hits
445 system.cpu.dcache.demand_hits::total 42510480 # number of demand (read+write) hits
446 system.cpu.dcache.overall_hits::cpu.data 42594987 # number of overall hits
447 system.cpu.dcache.overall_hits::total 42594987 # number of overall hits
448 system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses
449 system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses
450 system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses
451 system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses
452 system.cpu.dcache.SoftPFReq_misses::cpu.data 43690 # number of SoftPFReq misses
453 system.cpu.dcache.SoftPFReq_misses::total 43690 # number of SoftPFReq misses
454 system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses
455 system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses
456 system.cpu.dcache.overall_misses::cpu.data 302945 # number of overall misses
457 system.cpu.dcache.overall_misses::total 302945 # number of overall misses
458 system.cpu.dcache.ReadReq_miss_latency::cpu.data 1474342937 # number of ReadReq miss cycles
459 system.cpu.dcache.ReadReq_miss_latency::total 1474342937 # number of ReadReq miss cycles
460 system.cpu.dcache.WriteReq_miss_latency::cpu.data 16908501000 # number of WriteReq miss cycles
461 system.cpu.dcache.WriteReq_miss_latency::total 16908501000 # number of WriteReq miss cycles
462 system.cpu.dcache.demand_miss_latency::cpu.data 18382843937 # number of demand (read+write) miss cycles
463 system.cpu.dcache.demand_miss_latency::total 18382843937 # number of demand (read+write) miss cycles
464 system.cpu.dcache.overall_miss_latency::cpu.data 18382843937 # number of overall miss cycles
465 system.cpu.dcache.overall_miss_latency::total 18382843937 # number of overall miss cycles
466 system.cpu.dcache.ReadReq_accesses::cpu.data 22919834 # number of ReadReq accesses(hits+misses)
467 system.cpu.dcache.ReadReq_accesses::total 22919834 # number of ReadReq accesses(hits+misses)
468 system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
469 system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
470 system.cpu.dcache.SoftPFReq_accesses::cpu.data 128197 # number of SoftPFReq accesses(hits+misses)
471 system.cpu.dcache.SoftPFReq_accesses::total 128197 # number of SoftPFReq accesses(hits+misses)
472 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
473 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
474 system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
475 system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
476 system.cpu.dcache.demand_accesses::cpu.data 42769735 # number of demand (read+write) accesses
477 system.cpu.dcache.demand_accesses::total 42769735 # number of demand (read+write) accesses
478 system.cpu.dcache.overall_accesses::cpu.data 42897932 # number of overall (read+write) accesses
479 system.cpu.dcache.overall_accesses::total 42897932 # number of overall (read+write) accesses
480 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses
481 system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses
482 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
483 system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
484 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340804 # miss rate for SoftPFReq accesses
485 system.cpu.dcache.SoftPFReq_miss_rate::total 0.340804 # miss rate for SoftPFReq accesses
486 system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses
487 system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses
488 system.cpu.dcache.overall_miss_rate::cpu.data 0.007062 # miss rate for overall accesses
489 system.cpu.dcache.overall_miss_rate::total 0.007062 # miss rate for overall accesses
490 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774 # average ReadReq miss latency
491 system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774 # average ReadReq miss latency
492 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974 # average WriteReq miss latency
493 system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974 # average WriteReq miss latency
494 system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077 # average overall miss latency
495 system.cpu.dcache.demand_avg_miss_latency::total 70906.420077 # average overall miss latency
496 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543 # average overall miss latency
497 system.cpu.dcache.overall_avg_miss_latency::total 60680.466543 # average overall miss latency
498 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
499 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
501 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
502 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
503 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504 system.cpu.dcache.fast_writes 0 # number of fast writes performed
505 system.cpu.dcache.cache_copies 0 # number of cache copies performed
506 system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks
507 system.cpu.dcache.writebacks::total 128445 # number of writebacks
508 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22036 # number of ReadReq MSHR hits
509 system.cpu.dcache.ReadReq_mshr_hits::total 22036 # number of ReadReq MSHR hits
510 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100688 # number of WriteReq MSHR hits
511 system.cpu.dcache.WriteReq_mshr_hits::total 100688 # number of WriteReq MSHR hits
512 system.cpu.dcache.demand_mshr_hits::cpu.data 122724 # number of demand (read+write) MSHR hits
513 system.cpu.dcache.demand_mshr_hits::total 122724 # number of demand (read+write) MSHR hits
514 system.cpu.dcache.overall_mshr_hits::cpu.data 122724 # number of overall MSHR hits
515 system.cpu.dcache.overall_mshr_hits::total 122724 # number of overall MSHR hits
516 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29497 # number of ReadReq MSHR misses
517 system.cpu.dcache.ReadReq_mshr_misses::total 29497 # number of ReadReq MSHR misses
518 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
519 system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
520 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24001 # number of SoftPFReq MSHR misses
521 system.cpu.dcache.SoftPFReq_mshr_misses::total 24001 # number of SoftPFReq MSHR misses
522 system.cpu.dcache.demand_mshr_misses::cpu.data 136531 # number of demand (read+write) MSHR misses
523 system.cpu.dcache.demand_mshr_misses::total 136531 # number of demand (read+write) MSHR misses
524 system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses
525 system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses
526 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558577313 # number of ReadReq MSHR miss cycles
527 system.cpu.dcache.ReadReq_mshr_miss_latency::total 558577313 # number of ReadReq MSHR miss cycles
528 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8440191000 # number of WriteReq MSHR miss cycles
529 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8440191000 # number of WriteReq MSHR miss cycles
530 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682073500 # number of SoftPFReq MSHR miss cycles
531 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682073500 # number of SoftPFReq MSHR miss cycles
532 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8998768313 # number of demand (read+write) MSHR miss cycles
533 system.cpu.dcache.demand_mshr_miss_latency::total 8998768313 # number of demand (read+write) MSHR miss cycles
534 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10680841813 # number of overall MSHR miss cycles
535 system.cpu.dcache.overall_mshr_miss_latency::total 10680841813 # number of overall MSHR miss cycles
536 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses
537 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses
538 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
539 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
540 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187220 # mshr miss rate for SoftPFReq accesses
541 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187220 # mshr miss rate for SoftPFReq accesses
542 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
543 system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
544 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
545 system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
546 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941 # average ReadReq mshr miss latency
547 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941 # average ReadReq mshr miss latency
548 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917 # average WriteReq mshr miss latency
549 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917 # average WriteReq mshr miss latency
550 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689 # average SoftPFReq mshr miss latency
551 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689 # average SoftPFReq mshr miss latency
552 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998 # average overall mshr miss latency
553 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998 # average overall mshr miss latency
554 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663 # average overall mshr miss latency
555 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663 # average overall mshr miss latency
556 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
557 system.cpu.icache.tags.replacements 42847 # number of replacements
558 system.cpu.icache.tags.tagsinuse 1854.482229 # Cycle average of tags in use
559 system.cpu.icache.tags.total_refs 25082964 # Total number of references to valid blocks.
560 system.cpu.icache.tags.sampled_refs 44889 # Sample count of references to valid blocks.
561 system.cpu.icache.tags.avg_refs 558.777518 # Average number of references to valid blocks.
562 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
563 system.cpu.icache.tags.occ_blocks::cpu.inst 1854.482229 # Average occupied blocks per requestor
564 system.cpu.icache.tags.occ_percent::cpu.inst 0.905509 # Average percentage of cache occupancy
565 system.cpu.icache.tags.occ_percent::total 0.905509 # Average percentage of cache occupancy
566 system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
567 system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
568 system.cpu.icache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
569 system.cpu.icache.tags.age_task_id_blocks_1024::3 916 # Occupied blocks per task id
570 system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
571 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
572 system.cpu.icache.tags.tag_accesses 50300597 # Number of tag accesses
573 system.cpu.icache.tags.data_accesses 50300597 # Number of data accesses
574 system.cpu.icache.ReadReq_hits::cpu.inst 25082964 # number of ReadReq hits
575 system.cpu.icache.ReadReq_hits::total 25082964 # number of ReadReq hits
576 system.cpu.icache.demand_hits::cpu.inst 25082964 # number of demand (read+write) hits
577 system.cpu.icache.demand_hits::total 25082964 # number of demand (read+write) hits
578 system.cpu.icache.overall_hits::cpu.inst 25082964 # number of overall hits
579 system.cpu.icache.overall_hits::total 25082964 # number of overall hits
580 system.cpu.icache.ReadReq_misses::cpu.inst 44890 # number of ReadReq misses
581 system.cpu.icache.ReadReq_misses::total 44890 # number of ReadReq misses
582 system.cpu.icache.demand_misses::cpu.inst 44890 # number of demand (read+write) misses
583 system.cpu.icache.demand_misses::total 44890 # number of demand (read+write) misses
584 system.cpu.icache.overall_misses::cpu.inst 44890 # number of overall misses
585 system.cpu.icache.overall_misses::total 44890 # number of overall misses
586 system.cpu.icache.ReadReq_miss_latency::cpu.inst 936252739 # number of ReadReq miss cycles
587 system.cpu.icache.ReadReq_miss_latency::total 936252739 # number of ReadReq miss cycles
588 system.cpu.icache.demand_miss_latency::cpu.inst 936252739 # number of demand (read+write) miss cycles
589 system.cpu.icache.demand_miss_latency::total 936252739 # number of demand (read+write) miss cycles
590 system.cpu.icache.overall_miss_latency::cpu.inst 936252739 # number of overall miss cycles
591 system.cpu.icache.overall_miss_latency::total 936252739 # number of overall miss cycles
592 system.cpu.icache.ReadReq_accesses::cpu.inst 25127854 # number of ReadReq accesses(hits+misses)
593 system.cpu.icache.ReadReq_accesses::total 25127854 # number of ReadReq accesses(hits+misses)
594 system.cpu.icache.demand_accesses::cpu.inst 25127854 # number of demand (read+write) accesses
595 system.cpu.icache.demand_accesses::total 25127854 # number of demand (read+write) accesses
596 system.cpu.icache.overall_accesses::cpu.inst 25127854 # number of overall (read+write) accesses
597 system.cpu.icache.overall_accesses::total 25127854 # number of overall (read+write) accesses
598 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001786 # miss rate for ReadReq accesses
599 system.cpu.icache.ReadReq_miss_rate::total 0.001786 # miss rate for ReadReq accesses
600 system.cpu.icache.demand_miss_rate::cpu.inst 0.001786 # miss rate for demand accesses
601 system.cpu.icache.demand_miss_rate::total 0.001786 # miss rate for demand accesses
602 system.cpu.icache.overall_miss_rate::cpu.inst 0.001786 # miss rate for overall accesses
603 system.cpu.icache.overall_miss_rate::total 0.001786 # miss rate for overall accesses
604 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20856.599220 # average ReadReq miss latency
605 system.cpu.icache.ReadReq_avg_miss_latency::total 20856.599220 # average ReadReq miss latency
606 system.cpu.icache.demand_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency
607 system.cpu.icache.demand_avg_miss_latency::total 20856.599220 # average overall miss latency
608 system.cpu.icache.overall_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency
609 system.cpu.icache.overall_avg_miss_latency::total 20856.599220 # average overall miss latency
610 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
611 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
612 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
613 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
614 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
615 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
616 system.cpu.icache.fast_writes 0 # number of fast writes performed
617 system.cpu.icache.cache_copies 0 # number of cache copies performed
618 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44890 # number of ReadReq MSHR misses
619 system.cpu.icache.ReadReq_mshr_misses::total 44890 # number of ReadReq MSHR misses
620 system.cpu.icache.demand_mshr_misses::cpu.inst 44890 # number of demand (read+write) MSHR misses
621 system.cpu.icache.demand_mshr_misses::total 44890 # number of demand (read+write) MSHR misses
622 system.cpu.icache.overall_mshr_misses::cpu.inst 44890 # number of overall MSHR misses
623 system.cpu.icache.overall_mshr_misses::total 44890 # number of overall MSHR misses
624 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 867000761 # number of ReadReq MSHR miss cycles
625 system.cpu.icache.ReadReq_mshr_miss_latency::total 867000761 # number of ReadReq MSHR miss cycles
626 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 867000761 # number of demand (read+write) MSHR miss cycles
627 system.cpu.icache.demand_mshr_miss_latency::total 867000761 # number of demand (read+write) MSHR miss cycles
628 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 867000761 # number of overall MSHR miss cycles
629 system.cpu.icache.overall_mshr_miss_latency::total 867000761 # number of overall MSHR miss cycles
630 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for ReadReq accesses
631 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001786 # mshr miss rate for ReadReq accesses
632 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for demand accesses
633 system.cpu.icache.demand_mshr_miss_rate::total 0.001786 # mshr miss rate for demand accesses
634 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for overall accesses
635 system.cpu.icache.overall_mshr_miss_rate::total 0.001786 # mshr miss rate for overall accesses
636 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19313.895322 # average ReadReq mshr miss latency
637 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19313.895322 # average ReadReq mshr miss latency
638 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19313.895322 # average overall mshr miss latency
639 system.cpu.icache.demand_avg_mshr_miss_latency::total 19313.895322 # average overall mshr miss latency
640 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19313.895322 # average overall mshr miss latency
641 system.cpu.icache.overall_avg_mshr_miss_latency::total 19313.895322 # average overall mshr miss latency
642 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
643 system.cpu.l2cache.tags.replacements 95728 # number of replacements
644 system.cpu.l2cache.tags.tagsinuse 29864.649447 # Cycle average of tags in use
645 system.cpu.l2cache.tags.total_refs 99882 # Total number of references to valid blocks.
646 system.cpu.l2cache.tags.sampled_refs 126846 # Sample count of references to valid blocks.
647 system.cpu.l2cache.tags.avg_refs 0.787427 # Average number of references to valid blocks.
648 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
649 system.cpu.l2cache.tags.occ_blocks::writebacks 26742.608070 # Average occupied blocks per requestor
650 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.046569 # Average occupied blocks per requestor
651 system.cpu.l2cache.tags.occ_blocks::cpu.data 1562.994808 # Average occupied blocks per requestor
652 system.cpu.l2cache.tags.occ_percent::writebacks 0.816120 # Average percentage of cache occupancy
653 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047578 # Average percentage of cache occupancy
654 system.cpu.l2cache.tags.occ_percent::cpu.data 0.047699 # Average percentage of cache occupancy
655 system.cpu.l2cache.tags.occ_percent::total 0.911397 # Average percentage of cache occupancy
656 system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
657 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
658 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1812 # Occupied blocks per task id
659 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12771 # Occupied blocks per task id
660 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15838 # Occupied blocks per task id
661 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 578 # Occupied blocks per task id
662 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
663 system.cpu.l2cache.tags.tag_accesses 2904816 # Number of tag accesses
664 system.cpu.l2cache.tags.data_accesses 2904816 # Number of data accesses
665 system.cpu.l2cache.ReadReq_hits::cpu.inst 39815 # number of ReadReq hits
666 system.cpu.l2cache.ReadReq_hits::cpu.data 31912 # number of ReadReq hits
667 system.cpu.l2cache.ReadReq_hits::total 71727 # number of ReadReq hits
668 system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits
669 system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits
670 system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits
671 system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits
672 system.cpu.l2cache.demand_hits::cpu.inst 39815 # number of demand (read+write) hits
673 system.cpu.l2cache.demand_hits::cpu.data 36666 # number of demand (read+write) hits
674 system.cpu.l2cache.demand_hits::total 76481 # number of demand (read+write) hits
675 system.cpu.l2cache.overall_hits::cpu.inst 39815 # number of overall hits
676 system.cpu.l2cache.overall_hits::cpu.data 36666 # number of overall hits
677 system.cpu.l2cache.overall_hits::total 76481 # number of overall hits
678 system.cpu.l2cache.ReadReq_misses::cpu.inst 5075 # number of ReadReq misses
679 system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses
680 system.cpu.l2cache.ReadReq_misses::total 26661 # number of ReadReq misses
681 system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses
682 system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses
683 system.cpu.l2cache.demand_misses::cpu.inst 5075 # number of demand (read+write) misses
684 system.cpu.l2cache.demand_misses::cpu.data 123866 # number of demand (read+write) misses
685 system.cpu.l2cache.demand_misses::total 128941 # number of demand (read+write) misses
686 system.cpu.l2cache.overall_misses::cpu.inst 5075 # number of overall misses
687 system.cpu.l2cache.overall_misses::cpu.data 123866 # number of overall misses
688 system.cpu.l2cache.overall_misses::total 128941 # number of overall misses
689 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 404023750 # number of ReadReq miss cycles
690 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1851742250 # number of ReadReq miss cycles
691 system.cpu.l2cache.ReadReq_miss_latency::total 2255766000 # number of ReadReq miss cycles
692 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8283203500 # number of ReadExReq miss cycles
693 system.cpu.l2cache.ReadExReq_miss_latency::total 8283203500 # number of ReadExReq miss cycles
694 system.cpu.l2cache.demand_miss_latency::cpu.inst 404023750 # number of demand (read+write) miss cycles
695 system.cpu.l2cache.demand_miss_latency::cpu.data 10134945750 # number of demand (read+write) miss cycles
696 system.cpu.l2cache.demand_miss_latency::total 10538969500 # number of demand (read+write) miss cycles
697 system.cpu.l2cache.overall_miss_latency::cpu.inst 404023750 # number of overall miss cycles
698 system.cpu.l2cache.overall_miss_latency::cpu.data 10134945750 # number of overall miss cycles
699 system.cpu.l2cache.overall_miss_latency::total 10538969500 # number of overall miss cycles
700 system.cpu.l2cache.ReadReq_accesses::cpu.inst 44890 # number of ReadReq accesses(hits+misses)
701 system.cpu.l2cache.ReadReq_accesses::cpu.data 53498 # number of ReadReq accesses(hits+misses)
702 system.cpu.l2cache.ReadReq_accesses::total 98388 # number of ReadReq accesses(hits+misses)
703 system.cpu.l2cache.Writeback_accesses::writebacks 128445 # number of Writeback accesses(hits+misses)
704 system.cpu.l2cache.Writeback_accesses::total 128445 # number of Writeback accesses(hits+misses)
705 system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
706 system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
707 system.cpu.l2cache.demand_accesses::cpu.inst 44890 # number of demand (read+write) accesses
708 system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses
709 system.cpu.l2cache.demand_accesses::total 205422 # number of demand (read+write) accesses
710 system.cpu.l2cache.overall_accesses::cpu.inst 44890 # number of overall (read+write) accesses
711 system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses
712 system.cpu.l2cache.overall_accesses::total 205422 # number of overall (read+write) accesses
713 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113054 # miss rate for ReadReq accesses
714 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403492 # miss rate for ReadReq accesses
715 system.cpu.l2cache.ReadReq_miss_rate::total 0.270978 # miss rate for ReadReq accesses
716 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955584 # miss rate for ReadExReq accesses
717 system.cpu.l2cache.ReadExReq_miss_rate::total 0.955584 # miss rate for ReadExReq accesses
718 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113054 # miss rate for demand accesses
719 system.cpu.l2cache.demand_miss_rate::cpu.data 0.771597 # miss rate for demand accesses
720 system.cpu.l2cache.demand_miss_rate::total 0.627688 # miss rate for demand accesses
721 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113054 # miss rate for overall accesses
722 system.cpu.l2cache.overall_miss_rate::cpu.data 0.771597 # miss rate for overall accesses
723 system.cpu.l2cache.overall_miss_rate::total 0.627688 # miss rate for overall accesses
724 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79610.591133 # average ReadReq miss latency
725 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85784.408876 # average ReadReq miss latency
726 system.cpu.l2cache.ReadReq_avg_miss_latency::total 84609.204456 # average ReadReq miss latency
727 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80985.564138 # average ReadExReq miss latency
728 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80985.564138 # average ReadExReq miss latency
729 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79610.591133 # average overall miss latency
730 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81821.853858 # average overall miss latency
731 system.cpu.l2cache.demand_avg_miss_latency::total 81734.820577 # average overall miss latency
732 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79610.591133 # average overall miss latency
733 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81821.853858 # average overall miss latency
734 system.cpu.l2cache.overall_avg_miss_latency::total 81734.820577 # average overall miss latency
735 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
736 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
738 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
739 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
740 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
742 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
743 system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks
744 system.cpu.l2cache.writebacks::total 83953 # number of writebacks
745 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
746 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
747 system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
748 system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
749 system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits
750 system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
751 system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
752 system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits
753 system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
754 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5065 # number of ReadReq MSHR misses
755 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses
756 system.cpu.l2cache.ReadReq_mshr_misses::total 26588 # number of ReadReq MSHR misses
757 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
758 system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
759 system.cpu.l2cache.demand_mshr_misses::cpu.inst 5065 # number of demand (read+write) MSHR misses
760 system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses
761 system.cpu.l2cache.demand_mshr_misses::total 128868 # number of demand (read+write) MSHR misses
762 system.cpu.l2cache.overall_mshr_misses::cpu.inst 5065 # number of overall MSHR misses
763 system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses
764 system.cpu.l2cache.overall_mshr_misses::total 128868 # number of overall MSHR misses
765 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339808000 # number of ReadReq MSHR miss cycles
766 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1578466750 # number of ReadReq MSHR miss cycles
767 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1918274750 # number of ReadReq MSHR miss cycles
768 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7004628000 # number of ReadExReq MSHR miss cycles
769 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7004628000 # number of ReadExReq MSHR miss cycles
770 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339808000 # number of demand (read+write) MSHR miss cycles
771 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8583094750 # number of demand (read+write) MSHR miss cycles
772 system.cpu.l2cache.demand_mshr_miss_latency::total 8922902750 # number of demand (read+write) MSHR miss cycles
773 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339808000 # number of overall MSHR miss cycles
774 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8583094750 # number of overall MSHR miss cycles
775 system.cpu.l2cache.overall_mshr_miss_latency::total 8922902750 # number of overall MSHR miss cycles
776 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for ReadReq accesses
777 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402314 # mshr miss rate for ReadReq accesses
778 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270236 # mshr miss rate for ReadReq accesses
779 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses
780 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses
781 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for demand accesses
782 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for demand accesses
783 system.cpu.l2cache.demand_mshr_miss_rate::total 0.627333 # mshr miss rate for demand accesses
784 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for overall accesses
785 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for overall accesses
786 system.cpu.l2cache.overall_mshr_miss_rate::total 0.627333 # mshr miss rate for overall accesses
787 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315 # average ReadReq mshr miss latency
788 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890 # average ReadReq mshr miss latency
789 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138 # average ReadReq mshr miss latency
790 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968 # average ReadExReq mshr miss latency
791 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968 # average ReadExReq mshr miss latency
792 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency
793 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency
794 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency
795 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency
796 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency
797 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency
798 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
799 system.cpu.toL2Bus.trans_dist::ReadReq 98388 # Transaction distribution
800 system.cpu.toL2Bus.trans_dist::ReadResp 98387 # Transaction distribution
801 system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution
802 system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
803 system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
804 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89779 # Packet count per connected master and slave (bytes)
805 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449509 # Packet count per connected master and slave (bytes)
806 system.cpu.toL2Bus.pkt_count::total 539288 # Packet count per connected master and slave (bytes)
807 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2872896 # Cumulative packet size per connected master and slave (bytes)
808 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494528 # Cumulative packet size per connected master and slave (bytes)
809 system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes)
810 system.cpu.toL2Bus.snoops 0 # Total snoops (count)
811 system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram
812 system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
813 system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
814 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
815 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
816 system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram
817 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
818 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
819 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
820 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
821 system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram
822 system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks)
823 system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
824 system.cpu.toL2Bus.respLayer0.occupancy 68292739 # Layer occupancy (ticks)
825 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
826 system.cpu.toL2Bus.respLayer1.occupancy 268237687 # Layer occupancy (ticks)
827 system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
828 system.membus.trans_dist::ReadReq 26587 # Transaction distribution
829 system.membus.trans_dist::ReadResp 26587 # Transaction distribution
830 system.membus.trans_dist::Writeback 83953 # Transaction distribution
831 system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
832 system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
833 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341687 # Packet count per connected master and slave (bytes)
834 system.membus.pkt_count::total 341687 # Packet count per connected master and slave (bytes)
835 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620480 # Cumulative packet size per connected master and slave (bytes)
836 system.membus.pkt_size::total 13620480 # Cumulative packet size per connected master and slave (bytes)
837 system.membus.snoops 0 # Total snoops (count)
838 system.membus.snoop_fanout::samples 212820 # Request fanout histogram
839 system.membus.snoop_fanout::mean 0 # Request fanout histogram
840 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
841 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
842 system.membus.snoop_fanout::0 212820 100.00% 100.00% # Request fanout histogram
843 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
844 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
845 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
846 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
847 system.membus.snoop_fanout::total 212820 # Request fanout histogram
848 system.membus.reqLayer0.occupancy 578469000 # Layer occupancy (ticks)
849 system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
850 system.membus.respLayer1.occupancy 680054250 # Layer occupancy (ticks)
851 system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
853 ---------- End Simulation Statistics ----------
projects / gem5.git / blob