tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 mem_mode=timing
  22 mem_ranges=
  23 memories=system.physmem
  24 num_work_ids=16
  25 readfile=
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[0]
  35
  36 [system.clk_domain]
  37 type=SrcClockDomain
  38 clock=1000
  39 eventq_index=0
  40 voltage_domain=system.voltage_domain
  41
  42 [system.cpu]
  43 type=DerivO3CPU
  44 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  45 LFSTSize=1024
  46 LQEntries=32
  47 LSQCheckLoads=true
  48 LSQDepCheckShift=4
  49 SQEntries=32
  50 SSITSize=1024
  51 activity=0
  52 backComSize=5
  53 branchPred=system.cpu.branchPred
  54 cachePorts=200
  55 checker=Null
  56 clk_domain=system.cpu_clk_domain
  57 commitToDecodeDelay=1
  58 commitToFetchDelay=1
  59 commitToIEWDelay=1
  60 commitToRenameDelay=1
  61 commitWidth=8
  62 cpu_id=0
  63 decodeToFetchDelay=1
  64 decodeToRenameDelay=1
  65 decodeWidth=8
  66 dispatchWidth=8
  67 do_checkpoint_insts=true
  68 do_quiesce=true
  69 do_statistics_insts=true
  70 dtb=system.cpu.dtb
  71 eventq_index=0
  72 fetchBufferSize=64
  73 fetchToDecodeDelay=1
  74 fetchTrapLatency=1
  75 fetchWidth=8
  76 forwardComSize=5
  77 fuPool=system.cpu.fuPool
  78 function_trace=false
  79 function_trace_start=0
  80 iewToCommitDelay=1
  81 iewToDecodeDelay=1
  82 iewToFetchDelay=1
  83 iewToRenameDelay=1
  84 interrupts=system.cpu.interrupts
  85 isa=system.cpu.isa
  86 issueToExecuteDelay=1
  87 issueWidth=8
  88 itb=system.cpu.itb
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=false
  94 numIQEntries=64
  95 numPhysCCRegs=0
  96 numPhysFloatRegs=256
  97 numPhysIntRegs=256
  98 numROBEntries=192
  99 numRobs=1
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 simpoint_start_insts=
 109 smtCommitPolicy=RoundRobin
 110 smtFetchPolicy=SingleThread
 111 smtIQPolicy=Partitioned
 112 smtIQThreshold=100
 113 smtLSQPolicy=Partitioned
 114 smtLSQThreshold=100
 115 smtNumFetchingThreads=1
 116 smtROBPolicy=Partitioned
 117 smtROBThreshold=100
 118 squashWidth=8
 119 store_set_clear_period=250000
 120 switched_out=false
 121 system=system
 122 tracer=system.cpu.tracer
 123 trapLatency=13
 124 wbDepth=1
 125 wbWidth=8
 126 workload=system.cpu.workload
 127 dcache_port=system.cpu.dcache.cpu_side
 128 icache_port=system.cpu.icache.cpu_side
 129
 130 [system.cpu.branchPred]
 131 type=BranchPredictor
 132 BTBEntries=4096
 133 BTBTagSize=16
 134 RASSize=16
 135 choiceCtrBits=2
 136 choicePredictorSize=8192
 137 eventq_index=0
 138 globalCtrBits=2
 139 globalPredictorSize=8192
 140 instShiftAmt=2
 141 localCtrBits=2
 142 localHistoryTableSize=2048
 143 localPredictorSize=2048
 144 numThreads=1
 145 predType=tournament
 146
 147 [system.cpu.dcache]
 148 type=BaseCache
 149 children=tags
 150 addr_ranges=0:18446744073709551615
 151 assoc=2
 152 clk_domain=system.cpu_clk_domain
 153 eventq_index=0
 154 forward_snoops=true
 155 hit_latency=2
 156 is_top_level=true
 157 max_miss_count=0
 158 mshrs=4
 159 prefetch_on_access=false
 160 prefetcher=Null
 161 response_latency=2
 162 size=262144
 163 system=system
 164 tags=system.cpu.dcache.tags
 165 tgts_per_mshr=20
 166 two_queue=false
 167 write_buffers=8
 168 cpu_side=system.cpu.dcache_port
 169 mem_side=system.cpu.toL2Bus.slave[1]
 170
 171 [system.cpu.dcache.tags]
 172 type=LRU
 173 assoc=2
 174 block_size=64
 175 clk_domain=system.cpu_clk_domain
 176 eventq_index=0
 177 hit_latency=2
 178 size=262144
 179
 180 [system.cpu.dtb]
 181 type=ArmTLB
 182 children=walker
 183 eventq_index=0
 184 size=64
 185 walker=system.cpu.dtb.walker
 186
 187 [system.cpu.dtb.walker]
 188 type=ArmTableWalker
 189 clk_domain=system.cpu_clk_domain
 190 eventq_index=0
 191 num_squash_per_cycle=2
 192 sys=system
 193 port=system.cpu.toL2Bus.slave[3]
 194
 195 [system.cpu.fuPool]
 196 type=FUPool
 197 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 198 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 199 eventq_index=0
 200
 201 [system.cpu.fuPool.FUList0]
 202 type=FUDesc
 203 children=opList
 204 count=6
 205 eventq_index=0
 206 opList=system.cpu.fuPool.FUList0.opList
 207
 208 [system.cpu.fuPool.FUList0.opList]
 209 type=OpDesc
 210 eventq_index=0
 211 issueLat=1
 212 opClass=IntAlu
 213 opLat=1
 214
 215 [system.cpu.fuPool.FUList1]
 216 type=FUDesc
 217 children=opList0 opList1
 218 count=2
 219 eventq_index=0
 220 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 221
 222 [system.cpu.fuPool.FUList1.opList0]
 223 type=OpDesc
 224 eventq_index=0
 225 issueLat=1
 226 opClass=IntMult
 227 opLat=3
 228
 229 [system.cpu.fuPool.FUList1.opList1]
 230 type=OpDesc
 231 eventq_index=0
 232 issueLat=19
 233 opClass=IntDiv
 234 opLat=20
 235
 236 [system.cpu.fuPool.FUList2]
 237 type=FUDesc
 238 children=opList0 opList1 opList2
 239 count=4
 240 eventq_index=0
 241 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 242
 243 [system.cpu.fuPool.FUList2.opList0]
 244 type=OpDesc
 245 eventq_index=0
 246 issueLat=1
 247 opClass=FloatAdd
 248 opLat=2
 249
 250 [system.cpu.fuPool.FUList2.opList1]
 251 type=OpDesc
 252 eventq_index=0
 253 issueLat=1
 254 opClass=FloatCmp
 255 opLat=2
 256
 257 [system.cpu.fuPool.FUList2.opList2]
 258 type=OpDesc
 259 eventq_index=0
 260 issueLat=1
 261 opClass=FloatCvt
 262 opLat=2
 263
 264 [system.cpu.fuPool.FUList3]
 265 type=FUDesc
 266 children=opList0 opList1 opList2
 267 count=2
 268 eventq_index=0
 269 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 270
 271 [system.cpu.fuPool.FUList3.opList0]
 272 type=OpDesc
 273 eventq_index=0
 274 issueLat=1
 275 opClass=FloatMult
 276 opLat=4
 277
 278 [system.cpu.fuPool.FUList3.opList1]
 279 type=OpDesc
 280 eventq_index=0
 281 issueLat=12
 282 opClass=FloatDiv
 283 opLat=12
 284
 285 [system.cpu.fuPool.FUList3.opList2]
 286 type=OpDesc
 287 eventq_index=0
 288 issueLat=24
 289 opClass=FloatSqrt
 290 opLat=24
 291
 292 [system.cpu.fuPool.FUList4]
 293 type=FUDesc
 294 children=opList
 295 count=0
 296 eventq_index=0
 297 opList=system.cpu.fuPool.FUList4.opList
 298
 299 [system.cpu.fuPool.FUList4.opList]
 300 type=OpDesc
 301 eventq_index=0
 302 issueLat=1
 303 opClass=MemRead
 304 opLat=1
 305
 306 [system.cpu.fuPool.FUList5]
 307 type=FUDesc
 308 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 309 count=4
 310 eventq_index=0
 311 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 312
 313 [system.cpu.fuPool.FUList5.opList00]
 314 type=OpDesc
 315 eventq_index=0
 316 issueLat=1
 317 opClass=SimdAdd
 318 opLat=1
 319
 320 [system.cpu.fuPool.FUList5.opList01]
 321 type=OpDesc
 322 eventq_index=0
 323 issueLat=1
 324 opClass=SimdAddAcc
 325 opLat=1
 326
 327 [system.cpu.fuPool.FUList5.opList02]
 328 type=OpDesc
 329 eventq_index=0
 330 issueLat=1
 331 opClass=SimdAlu
 332 opLat=1
 333
 334 [system.cpu.fuPool.FUList5.opList03]
 335 type=OpDesc
 336 eventq_index=0
 337 issueLat=1
 338 opClass=SimdCmp
 339 opLat=1
 340
 341 [system.cpu.fuPool.FUList5.opList04]
 342 type=OpDesc
 343 eventq_index=0
 344 issueLat=1
 345 opClass=SimdCvt
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList05]
 349 type=OpDesc
 350 eventq_index=0
 351 issueLat=1
 352 opClass=SimdMisc
 353 opLat=1
 354
 355 [system.cpu.fuPool.FUList5.opList06]
 356 type=OpDesc
 357 eventq_index=0
 358 issueLat=1
 359 opClass=SimdMult
 360 opLat=1
 361
 362 [system.cpu.fuPool.FUList5.opList07]
 363 type=OpDesc
 364 eventq_index=0
 365 issueLat=1
 366 opClass=SimdMultAcc
 367 opLat=1
 368
 369 [system.cpu.fuPool.FUList5.opList08]
 370 type=OpDesc
 371 eventq_index=0
 372 issueLat=1
 373 opClass=SimdShift
 374 opLat=1
 375
 376 [system.cpu.fuPool.FUList5.opList09]
 377 type=OpDesc
 378 eventq_index=0
 379 issueLat=1
 380 opClass=SimdShiftAcc
 381 opLat=1
 382
 383 [system.cpu.fuPool.FUList5.opList10]
 384 type=OpDesc
 385 eventq_index=0
 386 issueLat=1
 387 opClass=SimdSqrt
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList5.opList11]
 391 type=OpDesc
 392 eventq_index=0
 393 issueLat=1
 394 opClass=SimdFloatAdd
 395 opLat=1
 396
 397 [system.cpu.fuPool.FUList5.opList12]
 398 type=OpDesc
 399 eventq_index=0
 400 issueLat=1
 401 opClass=SimdFloatAlu
 402 opLat=1
 403
 404 [system.cpu.fuPool.FUList5.opList13]
 405 type=OpDesc
 406 eventq_index=0
 407 issueLat=1
 408 opClass=SimdFloatCmp
 409 opLat=1
 410
 411 [system.cpu.fuPool.FUList5.opList14]
 412 type=OpDesc
 413 eventq_index=0
 414 issueLat=1
 415 opClass=SimdFloatCvt
 416 opLat=1
 417
 418 [system.cpu.fuPool.FUList5.opList15]
 419 type=OpDesc
 420 eventq_index=0
 421 issueLat=1
 422 opClass=SimdFloatDiv
 423 opLat=1
 424
 425 [system.cpu.fuPool.FUList5.opList16]
 426 type=OpDesc
 427 eventq_index=0
 428 issueLat=1
 429 opClass=SimdFloatMisc
 430 opLat=1
 431
 432 [system.cpu.fuPool.FUList5.opList17]
 433 type=OpDesc
 434 eventq_index=0
 435 issueLat=1
 436 opClass=SimdFloatMult
 437 opLat=1
 438
 439 [system.cpu.fuPool.FUList5.opList18]
 440 type=OpDesc
 441 eventq_index=0
 442 issueLat=1
 443 opClass=SimdFloatMultAcc
 444 opLat=1
 445
 446 [system.cpu.fuPool.FUList5.opList19]
 447 type=OpDesc
 448 eventq_index=0
 449 issueLat=1
 450 opClass=SimdFloatSqrt
 451 opLat=1
 452
 453 [system.cpu.fuPool.FUList6]
 454 type=FUDesc
 455 children=opList
 456 count=0
 457 eventq_index=0
 458 opList=system.cpu.fuPool.FUList6.opList
 459
 460 [system.cpu.fuPool.FUList6.opList]
 461 type=OpDesc
 462 eventq_index=0
 463 issueLat=1
 464 opClass=MemWrite
 465 opLat=1
 466
 467 [system.cpu.fuPool.FUList7]
 468 type=FUDesc
 469 children=opList0 opList1
 470 count=4
 471 eventq_index=0
 472 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 473
 474 [system.cpu.fuPool.FUList7.opList0]
 475 type=OpDesc
 476 eventq_index=0
 477 issueLat=1
 478 opClass=MemRead
 479 opLat=1
 480
 481 [system.cpu.fuPool.FUList7.opList1]
 482 type=OpDesc
 483 eventq_index=0
 484 issueLat=1
 485 opClass=MemWrite
 486 opLat=1
 487
 488 [system.cpu.fuPool.FUList8]
 489 type=FUDesc
 490 children=opList
 491 count=1
 492 eventq_index=0
 493 opList=system.cpu.fuPool.FUList8.opList
 494
 495 [system.cpu.fuPool.FUList8.opList]
 496 type=OpDesc
 497 eventq_index=0
 498 issueLat=3
 499 opClass=IprAccess
 500 opLat=3
 501
 502 [system.cpu.icache]
 503 type=BaseCache
 504 children=tags
 505 addr_ranges=0:18446744073709551615
 506 assoc=2
 507 clk_domain=system.cpu_clk_domain
 508 eventq_index=0
 509 forward_snoops=true
 510 hit_latency=2
 511 is_top_level=true
 512 max_miss_count=0
 513 mshrs=4
 514 prefetch_on_access=false
 515 prefetcher=Null
 516 response_latency=2
 517 size=131072
 518 system=system
 519 tags=system.cpu.icache.tags
 520 tgts_per_mshr=20
 521 two_queue=false
 522 write_buffers=8
 523 cpu_side=system.cpu.icache_port
 524 mem_side=system.cpu.toL2Bus.slave[0]
 525
 526 [system.cpu.icache.tags]
 527 type=LRU
 528 assoc=2
 529 block_size=64
 530 clk_domain=system.cpu_clk_domain
 531 eventq_index=0
 532 hit_latency=2
 533 size=131072
 534
 535 [system.cpu.interrupts]
 536 type=ArmInterrupts
 537 eventq_index=0
 538
 539 [system.cpu.isa]
 540 type=ArmISA
 541 eventq_index=0
 542 fpsid=1090793632
 543 id_isar0=34607377
 544 id_isar1=34677009
 545 id_isar2=555950401
 546 id_isar3=17899825
 547 id_isar4=268501314
 548 id_isar5=0
 549 id_mmfr0=3
 550 id_mmfr1=0
 551 id_mmfr2=19070976
 552 id_mmfr3=4027589137
 553 id_pfr0=49
 554 id_pfr1=1
 555 midr=890224640
 556
 557 [system.cpu.itb]
 558 type=ArmTLB
 559 children=walker
 560 eventq_index=0
 561 size=64
 562 walker=system.cpu.itb.walker
 563
 564 [system.cpu.itb.walker]
 565 type=ArmTableWalker
 566 clk_domain=system.cpu_clk_domain
 567 eventq_index=0
 568 num_squash_per_cycle=2
 569 sys=system
 570 port=system.cpu.toL2Bus.slave[2]
 571
 572 [system.cpu.l2cache]
 573 type=BaseCache
 574 children=tags
 575 addr_ranges=0:18446744073709551615
 576 assoc=8
 577 clk_domain=system.cpu_clk_domain
 578 eventq_index=0
 579 forward_snoops=true
 580 hit_latency=20
 581 is_top_level=false
 582 max_miss_count=0
 583 mshrs=20
 584 prefetch_on_access=false
 585 prefetcher=Null
 586 response_latency=20
 587 size=2097152
 588 system=system
 589 tags=system.cpu.l2cache.tags
 590 tgts_per_mshr=12
 591 two_queue=false
 592 write_buffers=8
 593 cpu_side=system.cpu.toL2Bus.master[0]
 594 mem_side=system.membus.slave[1]
 595
 596 [system.cpu.l2cache.tags]
 597 type=LRU
 598 assoc=8
 599 block_size=64
 600 clk_domain=system.cpu_clk_domain
 601 eventq_index=0
 602 hit_latency=20
 603 size=2097152
 604
 605 [system.cpu.toL2Bus]
 606 type=CoherentBus
 607 clk_domain=system.cpu_clk_domain
 608 eventq_index=0
 609 header_cycles=1
 610 system=system
 611 use_default_range=false
 612 width=32
 613 master=system.cpu.l2cache.cpu_side
 614 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 615
 616 [system.cpu.tracer]
 617 type=ExeTracer
 618 eventq_index=0
 619
 620 [system.cpu.workload]
 621 type=LiveProcess
 622 cmd=vortex lendian.raw
 623 cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 624 egid=100
 625 env=
 626 errout=cerr
 627 euid=100
 628 eventq_index=0
 629 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
 630 gid=100
 631 input=cin
 632 max_stack_size=67108864
 633 output=cout
 634 pid=100
 635 ppid=99
 636 simpoint=0
 637 system=system
 638 uid=100
 639
 640 [system.cpu_clk_domain]
 641 type=SrcClockDomain
 642 clock=500
 643 eventq_index=0
 644 voltage_domain=system.voltage_domain
 645
 646 [system.membus]
 647 type=CoherentBus
 648 clk_domain=system.clk_domain
 649 eventq_index=0
 650 header_cycles=1
 651 system=system
 652 use_default_range=false
 653 width=8
 654 master=system.physmem.port
 655 slave=system.system_port system.cpu.l2cache.mem_side
 656
 657 [system.physmem]
 658 type=SimpleDRAM
 659 activation_limit=4
 660 addr_mapping=RaBaChCo
 661 banks_per_rank=8
 662 burst_length=8
 663 channels=1
 664 clk_domain=system.clk_domain
 665 conf_table_reported=true
 666 device_bus_width=8
 667 device_rowbuffer_size=1024
 668 devices_per_rank=8
 669 eventq_index=0
 670 in_addr_map=true
 671 mem_sched_policy=frfcfs
 672 null=false
 673 page_policy=open
 674 range=0:134217727
 675 ranks_per_channel=2
 676 read_buffer_size=32
 677 static_backend_latency=10000
 678 static_frontend_latency=10000
 679 tBURST=5000
 680 tCL=13750
 681 tRAS=35000
 682 tRCD=13750
 683 tREFI=7800000
 684 tRFC=300000
 685 tRP=13750
 686 tRRD=6250
 687 tWTR=7500
 688 tXAW=40000
 689 write_buffer_size=32
 690 write_high_thresh_perc=70
 691 write_low_thresh_perc=0
 692 port=system.membus.master[0]
 693
 694 [system.voltage_domain]
 695 type=VoltageDomain
 696 eventq_index=0
 697 voltage=1.000000
 698