8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
16 clk_domain=system.clk_domain
20 load_addr_mask=1099511627775
24 memories=system.physmem
28 work_begin_ckpt_count=0
29 work_begin_cpu_id_exit=-1
30 work_begin_exit_count=0
31 work_cpus_ckpt_count=0
35 system_port=system.membus.slave[0]
41 voltage_domain=system.voltage_domain
45 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
54 branchPred=system.cpu.branchPred
57 clk_domain=system.cpu_clk_domain
68 do_checkpoint_insts=true
70 do_statistics_insts=true
71 dstage2_mmu=system.cpu.dstage2_mmu
79 fuPool=system.cpu.fuPool
81 function_trace_start=0
86 interrupts=system.cpu.interrupts
90 istage2_mmu=system.cpu.istage2_mmu
92 max_insts_all_threads=0
93 max_insts_any_thread=0
94 max_loads_all_threads=0
95 max_loads_any_thread=0
106 renameToDecodeDelay=1
111 simpoint_start_insts=
112 smtCommitPolicy=RoundRobin
113 smtFetchPolicy=SingleThread
114 smtIQPolicy=Partitioned
116 smtLSQPolicy=Partitioned
118 smtNumFetchingThreads=1
119 smtROBPolicy=Partitioned
123 store_set_clear_period=250000
126 tracer=system.cpu.tracer
130 workload=system.cpu.workload
131 dcache_port=system.cpu.dcache.cpu_side
132 icache_port=system.cpu.icache.cpu_side
134 [system.cpu.branchPred]
140 choicePredictorSize=8192
143 globalPredictorSize=8192
146 localHistoryTableSize=2048
147 localPredictorSize=2048
154 addr_ranges=0:18446744073709551615
156 clk_domain=system.cpu_clk_domain
163 prefetch_on_access=false
166 sequential_access=false
169 tags=system.cpu.dcache.tags
173 cpu_side=system.cpu.dcache_port
174 mem_side=system.cpu.toL2Bus.slave[1]
176 [system.cpu.dcache.tags]
180 clk_domain=system.cpu_clk_domain
183 sequential_access=false
186 [system.cpu.dstage2_mmu]
190 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
193 [system.cpu.dstage2_mmu.stage2_tlb]
199 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
201 [system.cpu.dstage2_mmu.stage2_tlb.walker]
203 clk_domain=system.cpu_clk_domain
206 num_squash_per_cycle=2
208 port=system.cpu.toL2Bus.slave[5]
216 walker=system.cpu.dtb.walker
218 [system.cpu.dtb.walker]
220 clk_domain=system.cpu_clk_domain
223 num_squash_per_cycle=2
225 port=system.cpu.toL2Bus.slave[3]
229 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
230 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
233 [system.cpu.fuPool.FUList0]
238 opList=system.cpu.fuPool.FUList0.opList
240 [system.cpu.fuPool.FUList0.opList]
247 [system.cpu.fuPool.FUList1]
249 children=opList0 opList1
252 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
254 [system.cpu.fuPool.FUList1.opList0]
261 [system.cpu.fuPool.FUList1.opList1]
268 [system.cpu.fuPool.FUList2]
270 children=opList0 opList1 opList2
273 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
275 [system.cpu.fuPool.FUList2.opList0]
282 [system.cpu.fuPool.FUList2.opList1]
289 [system.cpu.fuPool.FUList2.opList2]
296 [system.cpu.fuPool.FUList3]
298 children=opList0 opList1 opList2
301 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
303 [system.cpu.fuPool.FUList3.opList0]
310 [system.cpu.fuPool.FUList3.opList1]
317 [system.cpu.fuPool.FUList3.opList2]
324 [system.cpu.fuPool.FUList4]
329 opList=system.cpu.fuPool.FUList4.opList
331 [system.cpu.fuPool.FUList4.opList]
338 [system.cpu.fuPool.FUList5]
340 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
343 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
345 [system.cpu.fuPool.FUList5.opList00]
352 [system.cpu.fuPool.FUList5.opList01]
359 [system.cpu.fuPool.FUList5.opList02]
366 [system.cpu.fuPool.FUList5.opList03]
373 [system.cpu.fuPool.FUList5.opList04]
380 [system.cpu.fuPool.FUList5.opList05]
387 [system.cpu.fuPool.FUList5.opList06]
394 [system.cpu.fuPool.FUList5.opList07]
401 [system.cpu.fuPool.FUList5.opList08]
408 [system.cpu.fuPool.FUList5.opList09]
415 [system.cpu.fuPool.FUList5.opList10]
422 [system.cpu.fuPool.FUList5.opList11]
429 [system.cpu.fuPool.FUList5.opList12]
436 [system.cpu.fuPool.FUList5.opList13]
443 [system.cpu.fuPool.FUList5.opList14]
450 [system.cpu.fuPool.FUList5.opList15]
457 [system.cpu.fuPool.FUList5.opList16]
461 opClass=SimdFloatMisc
464 [system.cpu.fuPool.FUList5.opList17]
468 opClass=SimdFloatMult
471 [system.cpu.fuPool.FUList5.opList18]
475 opClass=SimdFloatMultAcc
478 [system.cpu.fuPool.FUList5.opList19]
482 opClass=SimdFloatSqrt
485 [system.cpu.fuPool.FUList6]
490 opList=system.cpu.fuPool.FUList6.opList
492 [system.cpu.fuPool.FUList6.opList]
499 [system.cpu.fuPool.FUList7]
501 children=opList0 opList1
504 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
506 [system.cpu.fuPool.FUList7.opList0]
513 [system.cpu.fuPool.FUList7.opList1]
520 [system.cpu.fuPool.FUList8]
525 opList=system.cpu.fuPool.FUList8.opList
527 [system.cpu.fuPool.FUList8.opList]
537 addr_ranges=0:18446744073709551615
539 clk_domain=system.cpu_clk_domain
546 prefetch_on_access=false
549 sequential_access=false
552 tags=system.cpu.icache.tags
556 cpu_side=system.cpu.icache_port
557 mem_side=system.cpu.toL2Bus.slave[0]
559 [system.cpu.icache.tags]
563 clk_domain=system.cpu_clk_domain
566 sequential_access=false
569 [system.cpu.interrupts]
579 id_aa64dfr0_el1=1052678
583 id_aa64mmfr0_el1=15728642
602 [system.cpu.istage2_mmu]
606 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
609 [system.cpu.istage2_mmu.stage2_tlb]
615 walker=system.cpu.istage2_mmu.stage2_tlb.walker
617 [system.cpu.istage2_mmu.stage2_tlb.walker]
619 clk_domain=system.cpu_clk_domain
622 num_squash_per_cycle=2
624 port=system.cpu.toL2Bus.slave[4]
632 walker=system.cpu.itb.walker
634 [system.cpu.itb.walker]
636 clk_domain=system.cpu_clk_domain
639 num_squash_per_cycle=2
641 port=system.cpu.toL2Bus.slave[2]
646 addr_ranges=0:18446744073709551615
648 clk_domain=system.cpu_clk_domain
655 prefetch_on_access=false
658 sequential_access=false
661 tags=system.cpu.l2cache.tags
665 cpu_side=system.cpu.toL2Bus.master[0]
666 mem_side=system.membus.slave[1]
668 [system.cpu.l2cache.tags]
672 clk_domain=system.cpu_clk_domain
675 sequential_access=false
680 clk_domain=system.cpu_clk_domain
684 use_default_range=false
686 master=system.cpu.l2cache.cpu_side
687 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
693 [system.cpu.workload]
695 cmd=vortex lendian.raw
696 cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
702 executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
705 max_stack_size=67108864
713 [system.cpu_clk_domain]
717 voltage_domain=system.voltage_domain
721 clk_domain=system.clk_domain
725 use_default_range=false
727 master=system.physmem.port
728 slave=system.system_port system.cpu.l2cache.mem_side
733 addr_mapping=RoRaBaChCo
737 clk_domain=system.clk_domain
738 conf_table_reported=true
740 device_rowbuffer_size=1024
744 max_accesses_per_row=16
745 mem_sched_policy=frfcfs
746 min_writes_per_switch=16
748 page_policy=open_adaptive
752 static_backend_latency=10000
753 static_frontend_latency=10000
769 write_high_thresh_perc=85
770 write_low_thresh_perc=50
771 port=system.membus.master[0]
773 [system.voltage_domain]