2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.033784 # Number of seconds simulated
4 sim_ticks 33784139000 # Number of ticks simulated
5 final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 118438 # Simulator instruction rate (inst/s)
8 host_op_rate 151468 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 56430150 # Simulator tick rate (ticks/s)
10 host_mem_usage 329476 # Number of bytes of host memory used
11 host_seconds 598.69 # Real time elapsed on the host
12 sim_insts 70907630 # Number of instructions simulated
13 sim_ops 90682585 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory
27 system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory
28 system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory
29 system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory
30 system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s)
35 system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s)
36 system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s)
37 system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s)
38 system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s)
41 system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s)
42 system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.readReqs 152888 # Number of read requests accepted
44 system.physmem.writeReqs 97288 # Number of write requests accepted
45 system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue
46 system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue
47 system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM
48 system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
49 system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM
50 system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side
51 system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side
52 system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
53 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55 system.physmem.perBankRdBursts::0 9124 # Per bank write bursts
56 system.physmem.perBankRdBursts::1 9348 # Per bank write bursts
57 system.physmem.perBankRdBursts::2 9757 # Per bank write bursts
58 system.physmem.perBankRdBursts::3 12566 # Per bank write bursts
59 system.physmem.perBankRdBursts::4 10929 # Per bank write bursts
60 system.physmem.perBankRdBursts::5 10090 # Per bank write bursts
61 system.physmem.perBankRdBursts::6 9786 # Per bank write bursts
62 system.physmem.perBankRdBursts::7 8974 # Per bank write bursts
63 system.physmem.perBankRdBursts::8 9178 # Per bank write bursts
64 system.physmem.perBankRdBursts::9 9832 # Per bank write bursts
65 system.physmem.perBankRdBursts::10 9165 # Per bank write bursts
66 system.physmem.perBankRdBursts::11 8819 # Per bank write bursts
67 system.physmem.perBankRdBursts::12 8693 # Per bank write bursts
68 system.physmem.perBankRdBursts::13 8672 # Per bank write bursts
69 system.physmem.perBankRdBursts::14 8813 # Per bank write bursts
70 system.physmem.perBankRdBursts::15 9022 # Per bank write bursts
71 system.physmem.perBankWrBursts::0 5950 # Per bank write bursts
72 system.physmem.perBankWrBursts::1 6192 # Per bank write bursts
73 system.physmem.perBankWrBursts::2 6162 # Per bank write bursts
74 system.physmem.perBankWrBursts::3 6171 # Per bank write bursts
75 system.physmem.perBankWrBursts::4 6089 # Per bank write bursts
76 system.physmem.perBankWrBursts::5 6262 # Per bank write bursts
77 system.physmem.perBankWrBursts::6 6013 # Per bank write bursts
78 system.physmem.perBankWrBursts::7 5971 # Per bank write bursts
79 system.physmem.perBankWrBursts::8 5978 # Per bank write bursts
80 system.physmem.perBankWrBursts::9 6080 # Per bank write bursts
81 system.physmem.perBankWrBursts::10 6215 # Per bank write bursts
82 system.physmem.perBankWrBursts::11 5915 # Per bank write bursts
83 system.physmem.perBankWrBursts::12 6050 # Per bank write bursts
84 system.physmem.perBankWrBursts::13 6057 # Per bank write bursts
85 system.physmem.perBankWrBursts::14 6142 # Per bank write bursts
86 system.physmem.perBankWrBursts::15 6018 # Per bank write bursts
87 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89 system.physmem.totGap 33784127500 # Total gap between requests
90 system.physmem.readPktSize::0 0 # Read request sizes (log2)
91 system.physmem.readPktSize::1 0 # Read request sizes (log2)
92 system.physmem.readPktSize::2 0 # Read request sizes (log2)
93 system.physmem.readPktSize::3 0 # Read request sizes (log2)
94 system.physmem.readPktSize::4 0 # Read request sizes (log2)
95 system.physmem.readPktSize::5 0 # Read request sizes (log2)
96 system.physmem.readPktSize::6 152888 # Read request sizes (log2)
97 system.physmem.writePktSize::0 0 # Write request sizes (log2)
98 system.physmem.writePktSize::1 0 # Write request sizes (log2)
99 system.physmem.writePktSize::2 0 # Write request sizes (log2)
100 system.physmem.writePktSize::3 0 # Write request sizes (log2)
101 system.physmem.writePktSize::4 0 # Write request sizes (log2)
102 system.physmem.writePktSize::5 0 # Write request sizes (log2)
103 system.physmem.writePktSize::6 97288 # Write request sizes (log2)
104 system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200 system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation
214 system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes
220 system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads
234 system.physmem.totQLat 6694958033 # Total ticks spent queuing
235 system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM
236 system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers
237 system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst
238 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
239 system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst
240 system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s
241 system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s
242 system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s
243 system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s
244 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
245 system.physmem.busUtil 3.70 # Data bus utilization in percentage
246 system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads
247 system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes
248 system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
249 system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
250 system.physmem.readRowHits 121417 # Number of row buffer hits during reads
251 system.physmem.writeRowHits 33065 # Number of row buffer hits during writes
252 system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
253 system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes
254 system.physmem.avgGap 135041.44 # Average gap between requests
255 system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined
256 system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ)
257 system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ)
258 system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ)
259 system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ)
260 system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ)
261 system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ)
262 system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ)
263 system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ)
264 system.physmem_0.averagePower 765.592889 # Core power per rank (mW)
265 system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states
266 system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states
267 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
268 system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states
269 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
270 system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ)
271 system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ)
272 system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ)
273 system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ)
274 system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ)
275 system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ)
276 system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ)
277 system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ)
278 system.physmem_1.averagePower 757.374848 # Core power per rank (mW)
279 system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states
280 system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states
281 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
282 system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states
283 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
284 system.cpu.branchPred.lookups 17214384 # Number of BP lookups
285 system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted
286 system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect
287 system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups
288 system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits
289 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
290 system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage
291 system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target.
292 system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions.
293 system.cpu_clk_domain.clock 500 # Clock period in ticks
294 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
295 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
296 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
297 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
298 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
299 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
300 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
301 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
302 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
303 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
304 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
305 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
306 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
307 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
308 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
309 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
310 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
311 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
312 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
313 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
314 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
315 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
316 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
317 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
318 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
319 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
320 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
321 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
322 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
323 system.cpu.dtb.walker.walks 0 # Table walker walks requested
324 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
325 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
326 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
327 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
328 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
329 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
330 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
331 system.cpu.dtb.inst_hits 0 # ITB inst hits
332 system.cpu.dtb.inst_misses 0 # ITB inst misses
333 system.cpu.dtb.read_hits 0 # DTB read hits
334 system.cpu.dtb.read_misses 0 # DTB read misses
335 system.cpu.dtb.write_hits 0 # DTB write hits
336 system.cpu.dtb.write_misses 0 # DTB write misses
337 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
338 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
339 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
340 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
341 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
342 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
343 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
344 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
345 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
346 system.cpu.dtb.read_accesses 0 # DTB read accesses
347 system.cpu.dtb.write_accesses 0 # DTB write accesses
348 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
349 system.cpu.dtb.hits 0 # DTB hits
350 system.cpu.dtb.misses 0 # DTB misses
351 system.cpu.dtb.accesses 0 # DTB accesses
352 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
353 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
354 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
355 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
356 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
357 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
358 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
359 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
360 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
361 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
362 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
363 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
364 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
365 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
366 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
367 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
368 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
369 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
370 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
371 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
372 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
373 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
374 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
375 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
376 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
377 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
378 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
379 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
380 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
381 system.cpu.itb.walker.walks 0 # Table walker walks requested
382 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
383 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
384 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
385 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
386 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
387 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
388 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
389 system.cpu.itb.inst_hits 0 # ITB inst hits
390 system.cpu.itb.inst_misses 0 # ITB inst misses
391 system.cpu.itb.read_hits 0 # DTB read hits
392 system.cpu.itb.read_misses 0 # DTB read misses
393 system.cpu.itb.write_hits 0 # DTB write hits
394 system.cpu.itb.write_misses 0 # DTB write misses
395 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
396 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
397 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
398 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
399 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
400 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
401 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
402 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
403 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
404 system.cpu.itb.read_accesses 0 # DTB read accesses
405 system.cpu.itb.write_accesses 0 # DTB write accesses
406 system.cpu.itb.inst_accesses 0 # ITB inst accesses
407 system.cpu.itb.hits 0 # DTB hits
408 system.cpu.itb.misses 0 # DTB misses
409 system.cpu.itb.accesses 0 # DTB accesses
410 system.cpu.workload.num_syscalls 1946 # Number of system calls
411 system.cpu.numCycles 67568279 # number of cpu cycles simulated
412 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
413 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
414 system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss
415 system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed
416 system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered
417 system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken
418 system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked
419 system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing
420 system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
421 system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
422 system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR
423 system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched
424 system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed
425 system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total)
426 system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total)
427 system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total)
431 system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total)
432 system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total)
433 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
434 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
435 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
436 system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total)
437 system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle
438 system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle
439 system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle
440 system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked
441 system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running
442 system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking
443 system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing
444 system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch
445 system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction
446 system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode
447 system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode
448 system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing
449 system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle
450 system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking
451 system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst
452 system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running
453 system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking
454 system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename
455 system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename
456 system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full
457 system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full
458 system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full
459 system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full
460 system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed
461 system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made
462 system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups
463 system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups
464 system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed
465 system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing
466 system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed
467 system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed
468 system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer
469 system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit.
470 system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit.
471 system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads.
472 system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores.
473 system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec)
474 system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ
475 system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued
476 system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued
477 system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling
478 system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph
479 system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed
480 system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle
481 system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle
482 system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle
490 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
491 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
492 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
493 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
494 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
495 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
496 system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle
497 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
498 system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available
499 system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available
500 system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available
501 system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available
502 system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available
503 system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available
504 system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available
505 system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available
506 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available
507 system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available
508 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available
521 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available
522 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available
523 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available
524 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available
525 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available
526 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available
527 system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available
528 system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available
529 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
530 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
531 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
532 system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued
533 system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued
534 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued
535 system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued
536 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued
537 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued
538 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued
539 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued
540 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued
541 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued
542 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued
555 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued
556 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued
557 system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued
558 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued
559 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued
560 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued
561 system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued
562 system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued
563 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
564 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
565 system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued
566 system.cpu.iq.rate 1.404756 # Inst issue rate
567 system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested
568 system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst)
569 system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads
570 system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes
571 system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses
572 system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads
573 system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes
574 system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses
575 system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses
576 system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses
577 system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores
578 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
579 system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed
580 system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed
581 system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations
582 system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed
583 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
584 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
585 system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled
586 system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked
587 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
588 system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing
589 system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking
590 system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking
591 system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ
592 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
593 system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions
594 system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions
595 system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions
596 system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall
597 system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall
598 system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations
599 system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly
600 system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly
601 system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute
602 system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions
603 system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed
604 system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute
605 system.cpu.iew.exec_swp 0 # number of swp insts executed
606 system.cpu.iew.exec_nop 9891 # number of nop insts executed
607 system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed
608 system.cpu.iew.exec_branches 14254152 # Number of branches executed
609 system.cpu.iew.exec_stores 20989921 # Number of stores executed
610 system.cpu.iew.exec_rate 1.391128 # Inst execution rate
611 system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit
612 system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back
613 system.cpu.iew.wb_producers 44980132 # num instructions producing a value
614 system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value
615 system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle
616 system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back
617 system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit
618 system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
619 system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted
620 system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle
621 system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle
622 system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle
630 system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle
631 system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle
632 system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle
633 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
634 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
635 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
636 system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle
637 system.cpu.commit.committedInsts 70913182 # Number of instructions committed
638 system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed
639 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
640 system.cpu.commit.refs 43422000 # Number of memory references committed
641 system.cpu.commit.loads 22866262 # Number of loads committed
642 system.cpu.commit.membars 15920 # Number of memory barriers committed
643 system.cpu.commit.branches 13741486 # Number of branches committed
644 system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
645 system.cpu.commit.int_insts 81528487 # Number of committed integer instructions.
646 system.cpu.commit.function_calls 1679850 # Number of function calls committed.
647 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
648 system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction
649 system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
650 system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
651 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
652 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
653 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
654 system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
655 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
656 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
657 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
658 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
659 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
660 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
661 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
662 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
663 system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
664 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
665 system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
666 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
667 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
668 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
669 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
670 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
671 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
672 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
673 system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
674 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
675 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
676 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
677 system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
678 system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction
679 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
680 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
681 system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction
682 system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached
683 system.cpu.rob.rob_reads 158892399 # The number of ROB reads
684 system.cpu.rob.rob_writes 195560325 # The number of ROB writes
685 system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself
686 system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling
687 system.cpu.committedInsts 70907630 # Number of Instructions Simulated
688 system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated
689 system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction
690 system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads
691 system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle
692 system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads
693 system.cpu.int_regfile_reads 102292430 # number of integer regfile reads
694 system.cpu.int_regfile_writes 56802415 # number of integer regfile writes
695 system.cpu.fp_regfile_reads 38 # number of floating regfile reads
696 system.cpu.fp_regfile_writes 22 # number of floating regfile writes
697 system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads
698 system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes
699 system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads
700 system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
701 system.cpu.dcache.tags.replacements 485025 # number of replacements
702 system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use
703 system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks.
704 system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks.
705 system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks.
706 system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit.
707 system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor
708 system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy
709 system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy
710 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
711 system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
712 system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id
713 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
714 system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses
715 system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses
716 system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits
717 system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits
718 system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits
719 system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits
720 system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits
721 system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits
722 system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits
723 system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits
724 system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
725 system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
726 system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits
727 system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits
728 system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits
729 system.cpu.dcache.overall_hits::total 40380955 # number of overall hits
730 system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses
731 system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses
732 system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses
733 system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses
734 system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses
735 system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses
736 system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses
737 system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses
738 system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses
739 system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses
740 system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses
741 system.cpu.dcache.overall_misses::total 1651921 # number of overall misses
742 system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles
743 system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles
744 system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles
745 system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles
746 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles
747 system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles
748 system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles
749 system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles
750 system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles
751 system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles
752 system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses)
753 system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses)
754 system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
755 system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
756 system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses)
757 system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses)
758 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses)
759 system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses)
760 system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
761 system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
762 system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses
763 system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses
764 system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses
765 system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses
766 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses
767 system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses
768 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses
769 system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses
770 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses
771 system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses
772 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses
773 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses
774 system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses
775 system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses
776 system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses
777 system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses
778 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency
779 system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency
780 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency
781 system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency
782 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency
783 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency
784 system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency
785 system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency
786 system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency
787 system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency
788 system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked
789 system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked
790 system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
791 system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked
792 system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked
793 system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked
794 system.cpu.dcache.fast_writes 0 # number of fast writes performed
795 system.cpu.dcache.cache_copies 0 # number of cache copies performed
796 system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks
797 system.cpu.dcache.writebacks::total 485025 # number of writebacks
798 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits
799 system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits
800 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits
801 system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits
802 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits
803 system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits
804 system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits
805 system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits
806 system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits
807 system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits
808 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses
809 system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses
810 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses
811 system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses
812 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses
813 system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses
814 system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses
815 system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses
816 system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses
817 system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses
818 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles
819 system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles
820 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles
821 system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles
822 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles
823 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles
824 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles
825 system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles
826 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles
827 system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles
828 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses
829 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses
830 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses
831 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses
832 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses
833 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses
834 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses
835 system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses
836 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses
837 system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses
838 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency
839 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency
840 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency
841 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency
842 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency
843 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency
844 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency
845 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency
846 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency
847 system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency
848 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
849 system.cpu.icache.tags.replacements 323129 # number of replacements
850 system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use
851 system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks.
852 system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks.
853 system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks.
854 system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit.
855 system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor
856 system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy
857 system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy
858 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
859 system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
860 system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
861 system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
862 system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id
863 system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
864 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
865 system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses
866 system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses
867 system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits
868 system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits
869 system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits
870 system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits
871 system.cpu.icache.overall_hits::cpu.inst 22445799 # number of overall hits
872 system.cpu.icache.overall_hits::total 22445799 # number of overall hits
873 system.cpu.icache.ReadReq_misses::cpu.inst 334748 # number of ReadReq misses
874 system.cpu.icache.ReadReq_misses::total 334748 # number of ReadReq misses
875 system.cpu.icache.demand_misses::cpu.inst 334748 # number of demand (read+write) misses
876 system.cpu.icache.demand_misses::total 334748 # number of demand (read+write) misses
877 system.cpu.icache.overall_misses::cpu.inst 334748 # number of overall misses
878 system.cpu.icache.overall_misses::total 334748 # number of overall misses
879 system.cpu.icache.ReadReq_miss_latency::cpu.inst 3612917411 # number of ReadReq miss cycles
880 system.cpu.icache.ReadReq_miss_latency::total 3612917411 # number of ReadReq miss cycles
881 system.cpu.icache.demand_miss_latency::cpu.inst 3612917411 # number of demand (read+write) miss cycles
882 system.cpu.icache.demand_miss_latency::total 3612917411 # number of demand (read+write) miss cycles
883 system.cpu.icache.overall_miss_latency::cpu.inst 3612917411 # number of overall miss cycles
884 system.cpu.icache.overall_miss_latency::total 3612917411 # number of overall miss cycles
885 system.cpu.icache.ReadReq_accesses::cpu.inst 22780547 # number of ReadReq accesses(hits+misses)
886 system.cpu.icache.ReadReq_accesses::total 22780547 # number of ReadReq accesses(hits+misses)
887 system.cpu.icache.demand_accesses::cpu.inst 22780547 # number of demand (read+write) accesses
888 system.cpu.icache.demand_accesses::total 22780547 # number of demand (read+write) accesses
889 system.cpu.icache.overall_accesses::cpu.inst 22780547 # number of overall (read+write) accesses
890 system.cpu.icache.overall_accesses::total 22780547 # number of overall (read+write) accesses
891 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014694 # miss rate for ReadReq accesses
892 system.cpu.icache.ReadReq_miss_rate::total 0.014694 # miss rate for ReadReq accesses
893 system.cpu.icache.demand_miss_rate::cpu.inst 0.014694 # miss rate for demand accesses
894 system.cpu.icache.demand_miss_rate::total 0.014694 # miss rate for demand accesses
895 system.cpu.icache.overall_miss_rate::cpu.inst 0.014694 # miss rate for overall accesses
896 system.cpu.icache.overall_miss_rate::total 0.014694 # miss rate for overall accesses
897 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10792.946966 # average ReadReq miss latency
898 system.cpu.icache.ReadReq_avg_miss_latency::total 10792.946966 # average ReadReq miss latency
899 system.cpu.icache.demand_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency
900 system.cpu.icache.demand_avg_miss_latency::total 10792.946966 # average overall miss latency
901 system.cpu.icache.overall_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency
902 system.cpu.icache.overall_avg_miss_latency::total 10792.946966 # average overall miss latency
903 system.cpu.icache.blocked_cycles::no_mshrs 264495 # number of cycles access was blocked
904 system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked
905 system.cpu.icache.blocked::no_mshrs 16626 # number of cycles access was blocked
906 system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
907 system.cpu.icache.avg_blocked_cycles::no_mshrs 15.908517 # average number of cycles each access was blocked
908 system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked
909 system.cpu.icache.fast_writes 0 # number of fast writes performed
910 system.cpu.icache.cache_copies 0 # number of cache copies performed
911 system.cpu.icache.writebacks::writebacks 323129 # number of writebacks
912 system.cpu.icache.writebacks::total 323129 # number of writebacks
913 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11096 # number of ReadReq MSHR hits
914 system.cpu.icache.ReadReq_mshr_hits::total 11096 # number of ReadReq MSHR hits
915 system.cpu.icache.demand_mshr_hits::cpu.inst 11096 # number of demand (read+write) MSHR hits
916 system.cpu.icache.demand_mshr_hits::total 11096 # number of demand (read+write) MSHR hits
917 system.cpu.icache.overall_mshr_hits::cpu.inst 11096 # number of overall MSHR hits
918 system.cpu.icache.overall_mshr_hits::total 11096 # number of overall MSHR hits
919 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323652 # number of ReadReq MSHR misses
920 system.cpu.icache.ReadReq_mshr_misses::total 323652 # number of ReadReq MSHR misses
921 system.cpu.icache.demand_mshr_misses::cpu.inst 323652 # number of demand (read+write) MSHR misses
922 system.cpu.icache.demand_mshr_misses::total 323652 # number of demand (read+write) MSHR misses
923 system.cpu.icache.overall_mshr_misses::cpu.inst 323652 # number of overall MSHR misses
924 system.cpu.icache.overall_mshr_misses::total 323652 # number of overall MSHR misses
925 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3313255946 # number of ReadReq MSHR miss cycles
926 system.cpu.icache.ReadReq_mshr_miss_latency::total 3313255946 # number of ReadReq MSHR miss cycles
927 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles
928 system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles
929 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles
930 system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles
931 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses
932 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses
933 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses
934 system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses
935 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses
936 system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # mshr miss rate for overall accesses
937 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10237.093996 # average ReadReq mshr miss latency
938 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10237.093996 # average ReadReq mshr miss latency
939 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency
940 system.cpu.icache.demand_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency
941 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency
942 system.cpu.icache.overall_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency
943 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
944 system.cpu.l2cache.prefetcher.num_hwpf_issued 821921 # number of hwpf issued
945 system.cpu.l2cache.prefetcher.pfIdentified 825508 # number of prefetch candidates identified
946 system.cpu.l2cache.prefetcher.pfBufferHit 3147 # number of redundant prefetches already in prefetch queue
947 system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
948 system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
949 system.cpu.l2cache.prefetcher.pfSpanPage 78532 # number of prefetches not generated due to page crossing
950 system.cpu.l2cache.tags.replacements 128137 # number of replacements
951 system.cpu.l2cache.tags.tagsinuse 15990.250829 # Cycle average of tags in use
952 system.cpu.l2cache.tags.total_refs 1182553 # Total number of references to valid blocks.
953 system.cpu.l2cache.tags.sampled_refs 144496 # Sample count of references to valid blocks.
954 system.cpu.l2cache.tags.avg_refs 8.183984 # Average number of references to valid blocks.
955 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
956 system.cpu.l2cache.tags.occ_blocks::writebacks 15899.758864 # Average occupied blocks per requestor
957 system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 90.491965 # Average occupied blocks per requestor
958 system.cpu.l2cache.tags.occ_percent::writebacks 0.970444 # Average percentage of cache occupancy
959 system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005523 # Average percentage of cache occupancy
960 system.cpu.l2cache.tags.occ_percent::total 0.975967 # Average percentage of cache occupancy
961 system.cpu.l2cache.tags.occ_task_id_blocks::1022 33 # Occupied blocks per task id
962 system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id
963 system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
964 system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
965 system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id
966 system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id
967 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
968 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # Occupied blocks per task id
969 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12114 # Occupied blocks per task id
970 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 551 # Occupied blocks per task id
971 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 772 # Occupied blocks per task id
972 system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002014 # Percentage of cache occupancy per task id
973 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id
974 system.cpu.l2cache.tags.tag_accesses 24991467 # Number of tag accesses
975 system.cpu.l2cache.tags.data_accesses 24991467 # Number of data accesses
976 system.cpu.l2cache.WritebackDirty_hits::writebacks 256728 # number of WritebackDirty hits
977 system.cpu.l2cache.WritebackDirty_hits::total 256728 # number of WritebackDirty hits
978 system.cpu.l2cache.WritebackClean_hits::writebacks 471596 # number of WritebackClean hits
979 system.cpu.l2cache.WritebackClean_hits::total 471596 # number of WritebackClean hits
980 system.cpu.l2cache.ReadExReq_hits::cpu.data 137032 # number of ReadExReq hits
981 system.cpu.l2cache.ReadExReq_hits::total 137032 # number of ReadExReq hits
982 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 311398 # number of ReadCleanReq hits
983 system.cpu.l2cache.ReadCleanReq_hits::total 311398 # number of ReadCleanReq hits
984 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300922 # number of ReadSharedReq hits
985 system.cpu.l2cache.ReadSharedReq_hits::total 300922 # number of ReadSharedReq hits
986 system.cpu.l2cache.demand_hits::cpu.inst 311398 # number of demand (read+write) hits
987 system.cpu.l2cache.demand_hits::cpu.data 437954 # number of demand (read+write) hits
988 system.cpu.l2cache.demand_hits::total 749352 # number of demand (read+write) hits
989 system.cpu.l2cache.overall_hits::cpu.inst 311398 # number of overall hits
990 system.cpu.l2cache.overall_hits::cpu.data 437954 # number of overall hits
991 system.cpu.l2cache.overall_hits::total 749352 # number of overall hits
992 system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses
993 system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses
994 system.cpu.l2cache.ReadExReq_misses::cpu.data 11535 # number of ReadExReq misses
995 system.cpu.l2cache.ReadExReq_misses::total 11535 # number of ReadExReq misses
996 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12242 # number of ReadCleanReq misses
997 system.cpu.l2cache.ReadCleanReq_misses::total 12242 # number of ReadCleanReq misses
998 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36048 # number of ReadSharedReq misses
999 system.cpu.l2cache.ReadSharedReq_misses::total 36048 # number of ReadSharedReq misses
1000 system.cpu.l2cache.demand_misses::cpu.inst 12242 # number of demand (read+write) misses
1001 system.cpu.l2cache.demand_misses::cpu.data 47583 # number of demand (read+write) misses
1002 system.cpu.l2cache.demand_misses::total 59825 # number of demand (read+write) misses
1003 system.cpu.l2cache.overall_misses::cpu.inst 12242 # number of overall misses
1004 system.cpu.l2cache.overall_misses::cpu.data 47583 # number of overall misses
1005 system.cpu.l2cache.overall_misses::total 59825 # number of overall misses
1006 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1188658000 # number of ReadExReq miss cycles
1007 system.cpu.l2cache.ReadExReq_miss_latency::total 1188658000 # number of ReadExReq miss cycles
1008 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 916670500 # number of ReadCleanReq miss cycles
1009 system.cpu.l2cache.ReadCleanReq_miss_latency::total 916670500 # number of ReadCleanReq miss cycles
1010 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2966913000 # number of ReadSharedReq miss cycles
1011 system.cpu.l2cache.ReadSharedReq_miss_latency::total 2966913000 # number of ReadSharedReq miss cycles
1012 system.cpu.l2cache.demand_miss_latency::cpu.inst 916670500 # number of demand (read+write) miss cycles
1013 system.cpu.l2cache.demand_miss_latency::cpu.data 4155571000 # number of demand (read+write) miss cycles
1014 system.cpu.l2cache.demand_miss_latency::total 5072241500 # number of demand (read+write) miss cycles
1015 system.cpu.l2cache.overall_miss_latency::cpu.inst 916670500 # number of overall miss cycles
1016 system.cpu.l2cache.overall_miss_latency::cpu.data 4155571000 # number of overall miss cycles
1017 system.cpu.l2cache.overall_miss_latency::total 5072241500 # number of overall miss cycles
1018 system.cpu.l2cache.WritebackDirty_accesses::writebacks 256728 # number of WritebackDirty accesses(hits+misses)
1019 system.cpu.l2cache.WritebackDirty_accesses::total 256728 # number of WritebackDirty accesses(hits+misses)
1020 system.cpu.l2cache.WritebackClean_accesses::writebacks 471596 # number of WritebackClean accesses(hits+misses)
1021 system.cpu.l2cache.WritebackClean_accesses::total 471596 # number of WritebackClean accesses(hits+misses)
1022 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses)
1023 system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses)
1024 system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses)
1025 system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses)
1026 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323640 # number of ReadCleanReq accesses(hits+misses)
1027 system.cpu.l2cache.ReadCleanReq_accesses::total 323640 # number of ReadCleanReq accesses(hits+misses)
1028 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336970 # number of ReadSharedReq accesses(hits+misses)
1029 system.cpu.l2cache.ReadSharedReq_accesses::total 336970 # number of ReadSharedReq accesses(hits+misses)
1030 system.cpu.l2cache.demand_accesses::cpu.inst 323640 # number of demand (read+write) accesses
1031 system.cpu.l2cache.demand_accesses::cpu.data 485537 # number of demand (read+write) accesses
1032 system.cpu.l2cache.demand_accesses::total 809177 # number of demand (read+write) accesses
1033 system.cpu.l2cache.overall_accesses::cpu.inst 323640 # number of overall (read+write) accesses
1034 system.cpu.l2cache.overall_accesses::cpu.data 485537 # number of overall (read+write) accesses
1035 system.cpu.l2cache.overall_accesses::total 809177 # number of overall (read+write) accesses
1036 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1037 system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1038 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077642 # miss rate for ReadExReq accesses
1039 system.cpu.l2cache.ReadExReq_miss_rate::total 0.077642 # miss rate for ReadExReq accesses
1040 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.037826 # miss rate for ReadCleanReq accesses
1041 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.037826 # miss rate for ReadCleanReq accesses
1042 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.106977 # miss rate for ReadSharedReq accesses
1043 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.106977 # miss rate for ReadSharedReq accesses
1044 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.037826 # miss rate for demand accesses
1045 system.cpu.l2cache.demand_miss_rate::cpu.data 0.098001 # miss rate for demand accesses
1046 system.cpu.l2cache.demand_miss_rate::total 0.073933 # miss rate for demand accesses
1047 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.037826 # miss rate for overall accesses
1048 system.cpu.l2cache.overall_miss_rate::cpu.data 0.098001 # miss rate for overall accesses
1049 system.cpu.l2cache.overall_miss_rate::total 0.073933 # miss rate for overall accesses
1050 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103047.941049 # average ReadExReq miss latency
1051 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103047.941049 # average ReadExReq miss latency
1052 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74879.145564 # average ReadCleanReq miss latency
1053 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74879.145564 # average ReadCleanReq miss latency
1054 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82304.510652 # average ReadSharedReq miss latency
1055 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82304.510652 # average ReadSharedReq miss latency
1056 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency
1057 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency
1058 system.cpu.l2cache.demand_avg_miss_latency::total 84784.646887 # average overall miss latency
1059 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency
1060 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency
1061 system.cpu.l2cache.overall_avg_miss_latency::total 84784.646887 # average overall miss latency
1062 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1063 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1064 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1065 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1066 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1067 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1068 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1069 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1070 system.cpu.l2cache.writebacks::writebacks 97288 # number of writebacks
1071 system.cpu.l2cache.writebacks::total 97288 # number of writebacks
1072 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3173 # number of ReadExReq MSHR hits
1073 system.cpu.l2cache.ReadExReq_mshr_hits::total 3173 # number of ReadExReq MSHR hits
1074 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 34 # number of ReadCleanReq MSHR hits
1075 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 34 # number of ReadCleanReq MSHR hits
1076 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 93 # number of ReadSharedReq MSHR hits
1077 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 93 # number of ReadSharedReq MSHR hits
1078 system.cpu.l2cache.demand_mshr_hits::cpu.inst 34 # number of demand (read+write) MSHR hits
1079 system.cpu.l2cache.demand_mshr_hits::cpu.data 3266 # number of demand (read+write) MSHR hits
1080 system.cpu.l2cache.demand_mshr_hits::total 3300 # number of demand (read+write) MSHR hits
1081 system.cpu.l2cache.overall_mshr_hits::cpu.inst 34 # number of overall MSHR hits
1082 system.cpu.l2cache.overall_mshr_hits::cpu.data 3266 # number of overall MSHR hits
1083 system.cpu.l2cache.overall_mshr_hits::total 3300 # number of overall MSHR hits
1084 system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112494 # number of HardPFReq MSHR misses
1085 system.cpu.l2cache.HardPFReq_mshr_misses::total 112494 # number of HardPFReq MSHR misses
1086 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses
1087 system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses
1088 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8362 # number of ReadExReq MSHR misses
1089 system.cpu.l2cache.ReadExReq_mshr_misses::total 8362 # number of ReadExReq MSHR misses
1090 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12208 # number of ReadCleanReq MSHR misses
1091 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12208 # number of ReadCleanReq MSHR misses
1092 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35955 # number of ReadSharedReq MSHR misses
1093 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35955 # number of ReadSharedReq MSHR misses
1094 system.cpu.l2cache.demand_mshr_misses::cpu.inst 12208 # number of demand (read+write) MSHR misses
1095 system.cpu.l2cache.demand_mshr_misses::cpu.data 44317 # number of demand (read+write) MSHR misses
1096 system.cpu.l2cache.demand_mshr_misses::total 56525 # number of demand (read+write) MSHR misses
1097 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12208 # number of overall MSHR misses
1098 system.cpu.l2cache.overall_mshr_misses::cpu.data 44317 # number of overall MSHR misses
1099 system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112494 # number of overall MSHR misses
1100 system.cpu.l2cache.overall_mshr_misses::total 169019 # number of overall MSHR misses
1101 system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of HardPFReq MSHR miss cycles
1102 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10322993748 # number of HardPFReq MSHR miss cycles
1103 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 147000 # number of UpgradeReq MSHR miss cycles
1104 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 147000 # number of UpgradeReq MSHR miss cycles
1105 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 658062000 # number of ReadExReq MSHR miss cycles
1106 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 658062000 # number of ReadExReq MSHR miss cycles
1107 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 841432500 # number of ReadCleanReq MSHR miss cycles
1108 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 841432500 # number of ReadCleanReq MSHR miss cycles
1109 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2745124500 # number of ReadSharedReq MSHR miss cycles
1110 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2745124500 # number of ReadSharedReq MSHR miss cycles
1111 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 841432500 # number of demand (read+write) MSHR miss cycles
1112 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3403186500 # number of demand (read+write) MSHR miss cycles
1113 system.cpu.l2cache.demand_mshr_miss_latency::total 4244619000 # number of demand (read+write) MSHR miss cycles
1114 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 841432500 # number of overall MSHR miss cycles
1115 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3403186500 # number of overall MSHR miss cycles
1116 system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of overall MSHR miss cycles
1117 system.cpu.l2cache.overall_mshr_miss_latency::total 14567612748 # number of overall MSHR miss cycles
1118 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1119 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1120 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1121 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1122 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses
1123 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses
1124 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses
1125 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses
1126 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.106701 # mshr miss rate for ReadSharedReq accesses
1127 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses
1128 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses
1129 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses
1130 system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses
1131 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses
1132 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses
1133 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1134 system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses
1135 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency
1136 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency
1137 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency
1138 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency
1139 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency
1140 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency
1141 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency
1142 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency
1143 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency
1144 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency
1145 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency
1146 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency
1147 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency
1148 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency
1149 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency
1150 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency
1151 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency
1152 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1153 system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter.
1154 system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1155 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1156 system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter.
1157 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1158 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1159 system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution
1160 system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution
1161 system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution
1162 system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution
1163 system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution
1164 system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution
1165 system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution
1166 system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution
1167 system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution
1168 system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution
1169 system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution
1170 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes)
1171 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes)
1172 system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes)
1173 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes)
1174 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes)
1175 system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes)
1176 system.cpu.toL2Bus.snoops 318345 # Total snoops (count)
1177 system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram
1178 system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram
1179 system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram
1180 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1181 system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram
1182 system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram
1183 system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram
1184 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1185 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1186 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1187 system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram
1188 system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks)
1189 system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%)
1190 system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks)
1191 system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
1192 system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks)
1193 system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
1194 system.membus.trans_dist::ReadResp 144525 # Transaction distribution
1195 system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution
1196 system.membus.trans_dist::CleanEvict 27973 # Transaction distribution
1197 system.membus.trans_dist::UpgradeReq 10 # Transaction distribution
1198 system.membus.trans_dist::ReadExReq 8362 # Transaction distribution
1199 system.membus.trans_dist::ReadExResp 8362 # Transaction distribution
1200 system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution
1201 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes)
1202 system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes)
1203 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes)
1204 system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes)
1205 system.membus.snoops 0 # Total snoops (count)
1206 system.membus.snoop_fanout::samples 278159 # Request fanout histogram
1207 system.membus.snoop_fanout::mean 0 # Request fanout histogram
1208 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1209 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1210 system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram
1211 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1212 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1213 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1214 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1215 system.membus.snoop_fanout::total 278159 # Request fanout histogram
1216 system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks)
1217 system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
1218 system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks)
1219 system.membus.respLayer1.utilization 2.4 # Layer utilization (%)
1221 ---------- End Simulation Statistics ----------
projects / gem5.git / blob