2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.025578 # Number of seconds simulated
4 sim_ticks 25577832000 # Number of ticks simulated
5 final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 133487 # Simulator instruction rate (inst/s)
8 host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 48151664 # Simulator tick rate (ticks/s)
10 host_mem_usage 268312 # Number of bytes of host memory used
11 host_seconds 531.19 # Real time elapsed on the host
12 sim_insts 70907629 # Number of instructions simulated
13 sim_ops 100626876 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 128779 # Total number of read requests seen
38 system.physmem.writeReqs 83944 # Total number of write requests seen
39 system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady
40 system.physmem.bytesRead 8241856 # Total number of bytes read from memory
41 system.physmem.bytesWritten 5372416 # Total number of bytes written to memory
42 system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize()
43 system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize()
44 system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
45 system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed
46 system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis
47 system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis
62 system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis
63 system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
78 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
80 system.physmem.totGap 25577735000 # Total gap between requests
81 system.physmem.readPktSize::0 0 # Categorize read packet sizes
82 system.physmem.readPktSize::1 0 # Categorize read packet sizes
83 system.physmem.readPktSize::2 0 # Categorize read packet sizes
84 system.physmem.readPktSize::3 0 # Categorize read packet sizes
85 system.physmem.readPktSize::4 0 # Categorize read packet sizes
86 system.physmem.readPktSize::5 0 # Categorize read packet sizes
87 system.physmem.readPktSize::6 128779 # Categorize read packet sizes
88 system.physmem.writePktSize::0 0 # Categorize write packet sizes
89 system.physmem.writePktSize::1 0 # Categorize write packet sizes
90 system.physmem.writePktSize::2 0 # Categorize write packet sizes
91 system.physmem.writePktSize::3 0 # Categorize write packet sizes
92 system.physmem.writePktSize::4 0 # Categorize write packet sizes
93 system.physmem.writePktSize::5 0 # Categorize write packet sizes
94 system.physmem.writePktSize::6 83944 # Categorize write packet sizes
95 system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
96 system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
127 system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
128 system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
159 system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
160 system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
161 system.physmem.totBusLat 643885000 # Total cycles spent in databus access
162 system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
163 system.physmem.avgQLat 24884.85 # Average queueing delay per request
164 system.physmem.avgBankLat 10873.20 # Average bank access latency per request
165 system.physmem.avgBusLat 5000.00 # Average bus latency per request
166 system.physmem.avgMemAccLat 40758.05 # Average memory access latency
167 system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
168 system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
169 system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
170 system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s
171 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172 system.physmem.busUtil 4.16 # Data bus utilization in percentage
173 system.physmem.avgRdQLen 0.21 # Average read queue length over time
174 system.physmem.avgWrQLen 9.73 # Average write queue length over time
175 system.physmem.readRowHits 116758 # Number of row buffer hits during reads
176 system.physmem.writeRowHits 52879 # Number of row buffer hits during writes
177 system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads
178 system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes
179 system.physmem.avgGap 120239.63 # Average gap between requests
180 system.cpu.branchPred.lookups 16629564 # Number of BP lookups
181 system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted
182 system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect
183 system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups
184 system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits
185 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
186 system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage
187 system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target.
188 system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions.
189 system.cpu.dtb.inst_hits 0 # ITB inst hits
190 system.cpu.dtb.inst_misses 0 # ITB inst misses
191 system.cpu.dtb.read_hits 0 # DTB read hits
192 system.cpu.dtb.read_misses 0 # DTB read misses
193 system.cpu.dtb.write_hits 0 # DTB write hits
194 system.cpu.dtb.write_misses 0 # DTB write misses
195 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
196 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
197 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
198 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
199 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
200 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
201 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
202 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
203 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
204 system.cpu.dtb.read_accesses 0 # DTB read accesses
205 system.cpu.dtb.write_accesses 0 # DTB write accesses
206 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
207 system.cpu.dtb.hits 0 # DTB hits
208 system.cpu.dtb.misses 0 # DTB misses
209 system.cpu.dtb.accesses 0 # DTB accesses
210 system.cpu.itb.inst_hits 0 # ITB inst hits
211 system.cpu.itb.inst_misses 0 # ITB inst misses
212 system.cpu.itb.read_hits 0 # DTB read hits
213 system.cpu.itb.read_misses 0 # DTB read misses
214 system.cpu.itb.write_hits 0 # DTB write hits
215 system.cpu.itb.write_misses 0 # DTB write misses
216 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
217 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
218 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
219 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
220 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
221 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
222 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
223 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
224 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
225 system.cpu.itb.read_accesses 0 # DTB read accesses
226 system.cpu.itb.write_accesses 0 # DTB write accesses
227 system.cpu.itb.inst_accesses 0 # ITB inst accesses
228 system.cpu.itb.hits 0 # DTB hits
229 system.cpu.itb.misses 0 # DTB misses
230 system.cpu.itb.accesses 0 # DTB accesses
231 system.cpu.workload.num_syscalls 1946 # Number of system calls
232 system.cpu.numCycles 51155665 # number of cpu cycles simulated
233 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
234 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
235 system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
236 system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
237 system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
238 system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
239 system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
240 system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
241 system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
242 system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243 system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
244 system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
245 system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
246 system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
247 system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
248 system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
249 system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
250 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
251 system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
252 system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
253 system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
254 system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
255 system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total)
256 system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total)
257 system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total)
258 system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total)
259 system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total)
260 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
261 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
262 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
263 system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
264 system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
265 system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
266 system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
267 system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
268 system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
269 system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
270 system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
271 system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
272 system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
273 system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
274 system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
275 system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
276 system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
277 system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
278 system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
279 system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
280 system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
281 system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
282 system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
283 system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
284 system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
285 system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
286 system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
287 system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
288 system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
289 system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
290 system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
291 system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
292 system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
293 system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
294 system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
295 system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
296 system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
297 system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
298 system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
299 system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
300 system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
301 system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
302 system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued
303 system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
304 system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
305 system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
306 system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
307 system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
308 system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
309 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
310 system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
311 system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
312 system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
313 system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
314 system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
315 system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
316 system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
317 system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
318 system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
319 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
320 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
321 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
322 system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
323 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
324 system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
325 system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
326 system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available
327 system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available
328 system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available
329 system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available
330 system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available
331 system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available
332 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
333 system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available
334 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available
335 system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available
336 system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available
337 system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available
338 system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available
339 system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available
340 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available
341 system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available
342 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available
343 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available
344 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available
345 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available
346 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available
347 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available
348 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available
349 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available
350 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available
351 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
352 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
353 system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
354 system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
355 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
356 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
357 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
358 system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued
359 system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued
360 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
361 system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued
362 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
363 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
364 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
365 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued
366 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued
367 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued
368 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued
369 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued
370 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued
371 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued
372 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued
373 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued
374 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued
375 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued
376 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued
377 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued
378 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued
379 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued
380 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued
381 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued
382 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued
383 system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued
384 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
385 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
386 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
387 system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued
388 system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued
389 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
390 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
391 system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
392 system.cpu.iq.rate 2.096836 # Inst issue rate
393 system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
394 system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
395 system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
396 system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
397 system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
398 system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
399 system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
400 system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
401 system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
402 system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
403 system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
404 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
405 system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed
406 system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed
407 system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations
408 system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed
409 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
410 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
411 system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
412 system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
413 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
414 system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
415 system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
416 system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
417 system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
418 system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
419 system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
420 system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
421 system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
422 system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
423 system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
424 system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
425 system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
426 system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
427 system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
428 system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
429 system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
430 system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
431 system.cpu.iew.exec_swp 0 # number of swp insts executed
432 system.cpu.iew.exec_nop 9761 # number of nop insts executed
433 system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
434 system.cpu.iew.exec_branches 14602542 # Number of branches executed
435 system.cpu.iew.exec_stores 21344564 # Number of stores executed
436 system.cpu.iew.exec_rate 2.076700 # Inst execution rate
437 system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
438 system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
439 system.cpu.iew.wb_producers 53282087 # num instructions producing a value
440 system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
441 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
442 system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
443 system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
444 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
445 system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
446 system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
447 system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
448 system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
449 system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
450 system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
451 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
452 system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
453 system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
454 system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
455 system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
456 system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
457 system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
458 system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
459 system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
460 system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
461 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
462 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
463 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
464 system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
465 system.cpu.commit.committedInsts 70913181 # Number of instructions committed
466 system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
467 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
468 system.cpu.commit.refs 47862846 # Number of memory references committed
469 system.cpu.commit.loads 27307108 # Number of loads committed
470 system.cpu.commit.membars 15920 # Number of memory barriers committed
471 system.cpu.commit.branches 13741505 # Number of branches committed
472 system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
473 system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
474 system.cpu.commit.function_calls 1679850 # Number of function calls committed.
475 system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
476 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
477 system.cpu.rob.rob_reads 149959530 # The number of ROB reads
478 system.cpu.rob.rob_writes 224865260 # The number of ROB writes
479 system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
480 system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
481 system.cpu.committedInsts 70907629 # Number of Instructions Simulated
482 system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
483 system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
484 system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction
485 system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
486 system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
487 system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
488 system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
489 system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
490 system.cpu.fp_regfile_reads 804 # number of floating regfile reads
491 system.cpu.fp_regfile_writes 688 # number of floating regfile writes
492 system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
493 system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
494 system.cpu.icache.replacements 28586 # number of replacements
495 system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
496 system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
497 system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
498 system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
499 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
500 system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
501 system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
502 system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
503 system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
504 system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits
505 system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits
506 system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits
507 system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits
508 system.cpu.icache.overall_hits::total 11645446 # number of overall hits
509 system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses
510 system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses
511 system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses
512 system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
513 system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
514 system.cpu.icache.overall_misses::total 34686 # number of overall misses
515 system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
516 system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
517 system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
518 system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
519 system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
520 system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
521 system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
522 system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
523 system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
524 system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses
525 system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses
526 system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses
527 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses
528 system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses
529 system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses
530 system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
531 system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
532 system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
533 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
534 system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
535 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
536 system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
537 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
538 system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
539 system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
540 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541 system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
542 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
543 system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked
544 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545 system.cpu.icache.fast_writes 0 # number of fast writes performed
546 system.cpu.icache.cache_copies 0 # number of cache copies performed
547 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits
548 system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits
549 system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits
550 system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits
551 system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits
552 system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits
553 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses
554 system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses
555 system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses
556 system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses
557 system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses
558 system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses
559 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
560 system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
561 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
562 system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
563 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
564 system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
565 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses
566 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses
567 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses
568 system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses
569 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses
570 system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses
571 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
572 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
573 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
574 system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
575 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
576 system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
577 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
578 system.cpu.l2cache.replacements 95649 # number of replacements
579 system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
580 system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks.
581 system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks.
582 system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks.
583 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
584 system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
585 system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
586 system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
587 system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy
588 system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy
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593 system.cpu.l2cache.ReadReq_hits::total 59285 # number of ReadReq hits
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595 system.cpu.l2cache.Writeback_hits::total 129109 # number of Writeback hits
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610 system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses
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612 system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses
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617 system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses
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622 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
623 system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
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625 system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
626 system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
627 system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
628 system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
629 system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
630 system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
631 system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
632 system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses)
633 system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses)
634 system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses)
635 system.cpu.l2cache.Writeback_accesses::writebacks 129109 # number of Writeback accesses(hits+misses)
636 system.cpu.l2cache.Writeback_accesses::total 129109 # number of Writeback accesses(hits+misses)
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638 system.cpu.l2cache.UpgradeReq_accesses::total 332 # number of UpgradeReq accesses(hits+misses)
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640 system.cpu.l2cache.ReadExReq_accesses::total 107042 # number of ReadExReq accesses(hits+misses)
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645 system.cpu.l2cache.overall_accesses::cpu.data 162424 # number of overall (read+write) accesses
646 system.cpu.l2cache.overall_accesses::total 192925 # number of overall (read+write) accesses
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648 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395833 # miss rate for ReadReq accesses
649 system.cpu.l2cache.ReadReq_miss_rate::total 0.309700 # miss rate for ReadReq accesses
650 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.939759 # miss rate for UpgradeReq accesses
651 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.939759 # miss rate for UpgradeReq accesses
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653 system.cpu.l2cache.ReadExReq_miss_rate::total 0.955298 # miss rate for ReadExReq accesses
654 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153306 # miss rate for demand accesses
655 system.cpu.l2cache.demand_miss_rate::cpu.data 0.764536 # miss rate for demand accesses
656 system.cpu.l2cache.demand_miss_rate::total 0.667902 # miss rate for demand accesses
657 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses
658 system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses
659 system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses
660 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
661 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
662 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
663 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency
664 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency
665 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
666 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
667 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
668 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
669 system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
670 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
671 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
672 system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
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674 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
676 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
677 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
680 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
681 system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks
682 system.cpu.l2cache.writebacks::total 83944 # number of writebacks
683 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
684 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
685 system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
686 system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
687 system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
688 system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
689 system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
690 system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
691 system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
692 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
693 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses
694 system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses
695 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses
696 system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses
697 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses
698 system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses
699 system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
700 system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses
701 system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses
702 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
703 system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
704 system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses
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706 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
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708 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles
709 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles
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711 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
712 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
713 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
714 system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
715 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
716 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
717 system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
718 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses
719 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses
720 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses
721 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses
722 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses
723 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses
724 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses
725 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses
726 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses
727 system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses
728 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses
729 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses
730 system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses
731 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
732 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
733 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
734 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency
735 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency
736 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
737 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
738 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
739 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
740 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
741 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
742 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
743 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
744 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
745 system.cpu.dcache.replacements 158328 # number of replacements
746 system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
747 system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
748 system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks.
749 system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
750 system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit.
751 system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
752 system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy
753 system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy
754 system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
755 system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
756 system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits
757 system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits
758 system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits
759 system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits
760 system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
761 system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
762 system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
763 system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
764 system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
765 system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
766 system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
767 system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
768 system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses
769 system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses
770 system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses
771 system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses
772 system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
773 system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
774 system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
775 system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
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777 system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
778 system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
779 system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
780 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles
781 system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles
782 system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
783 system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
784 system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
785 system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
786 system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses)
787 system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses)
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789 system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
790 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses)
791 system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses)
792 system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
793 system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
794 system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses
795 system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses
796 system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses
797 system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses
798 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses
799 system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses
800 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses
801 system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses
802 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses
803 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses
804 system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses
805 system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses
806 system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses
807 system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses
808 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
809 system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
810 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
811 system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
812 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency
813 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency
814 system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
815 system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
816 system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
817 system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
818 system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked
819 system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
820 system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked
821 system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
822 system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked
823 system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked
824 system.cpu.dcache.fast_writes 0 # number of fast writes performed
825 system.cpu.dcache.cache_copies 0 # number of cache copies performed
826 system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks
827 system.cpu.dcache.writebacks::total 129109 # number of writebacks
828 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
829 system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
830 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits
831 system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits
832 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits
833 system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
834 system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
835 system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
836 system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
837 system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
838 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
839 system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
840 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses
841 system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses
842 system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses
843 system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses
844 system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses
845 system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses
846 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
847 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
848 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
849 system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
850 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
851 system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
852 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
853 system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
854 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses
855 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses
856 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
857 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
858 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses
859 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
860 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
861 system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
862 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
863 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
864 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
865 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
866 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
867 system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
868 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
869 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
870 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
872 ---------- End Simulation Statistics ----------
projects / gem5.git / blob