tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=TimingSimpleCPU
  40 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
  41 checker=Null
  42 clk_domain=system.cpu_clk_domain
  43 cpu_id=0
  44 do_checkpoint_insts=true
  45 do_quiesce=true
  46 do_statistics_insts=true
  47 dtb=system.cpu.dtb
  48 function_trace=false
  49 function_trace_start=0
  50 interrupts=system.cpu.interrupts
  51 isa=system.cpu.isa
  52 itb=system.cpu.itb
  53 max_insts_all_threads=0
  54 max_insts_any_thread=0
  55 max_loads_all_threads=0
  56 max_loads_any_thread=0
  57 numThreads=1
  58 profile=0
  59 progress_interval=0
  60 simpoint_start_insts=
  61 switched_out=false
  62 system=system
  63 tracer=system.cpu.tracer
  64 workload=system.cpu.workload
  65 dcache_port=system.cpu.dcache.cpu_side
  66 icache_port=system.cpu.icache.cpu_side
  67
  68 [system.cpu.dcache]
  69 type=BaseCache
  70 children=tags
  71 addr_ranges=0:18446744073709551615
  72 assoc=2
  73 clk_domain=system.cpu_clk_domain
  74 forward_snoops=true
  75 hit_latency=2
  76 is_top_level=true
  77 max_miss_count=0
  78 mshrs=4
  79 prefetch_on_access=false
  80 prefetcher=Null
  81 response_latency=2
  82 size=262144
  83 system=system
  84 tags=system.cpu.dcache.tags
  85 tgts_per_mshr=20
  86 two_queue=false
  87 write_buffers=8
  88 cpu_side=system.cpu.dcache_port
  89 mem_side=system.cpu.toL2Bus.slave[1]
  90
  91 [system.cpu.dcache.tags]
  92 type=LRU
  93 assoc=2
  94 block_size=64
  95 clk_domain=system.cpu_clk_domain
  96 hit_latency=2
  97 size=262144
  98
  99 [system.cpu.dtb]
 100 type=ArmTLB
 101 children=walker
 102 size=64
 103 walker=system.cpu.dtb.walker
 104
 105 [system.cpu.dtb.walker]
 106 type=ArmTableWalker
 107 clk_domain=system.cpu_clk_domain
 108 num_squash_per_cycle=2
 109 sys=system
 110 port=system.cpu.toL2Bus.slave[3]
 111
 112 [system.cpu.icache]
 113 type=BaseCache
 114 children=tags
 115 addr_ranges=0:18446744073709551615
 116 assoc=2
 117 clk_domain=system.cpu_clk_domain
 118 forward_snoops=true
 119 hit_latency=2
 120 is_top_level=true
 121 max_miss_count=0
 122 mshrs=4
 123 prefetch_on_access=false
 124 prefetcher=Null
 125 response_latency=2
 126 size=131072
 127 system=system
 128 tags=system.cpu.icache.tags
 129 tgts_per_mshr=20
 130 two_queue=false
 131 write_buffers=8
 132 cpu_side=system.cpu.icache_port
 133 mem_side=system.cpu.toL2Bus.slave[0]
 134
 135 [system.cpu.icache.tags]
 136 type=LRU
 137 assoc=2
 138 block_size=64
 139 clk_domain=system.cpu_clk_domain
 140 hit_latency=2
 141 size=131072
 142
 143 [system.cpu.interrupts]
 144 type=ArmInterrupts
 145
 146 [system.cpu.isa]
 147 type=ArmISA
 148 fpsid=1090793632
 149 id_isar0=34607377
 150 id_isar1=34677009
 151 id_isar2=555950401
 152 id_isar3=17899825
 153 id_isar4=268501314
 154 id_isar5=0
 155 id_mmfr0=3
 156 id_mmfr1=0
 157 id_mmfr2=19070976
 158 id_mmfr3=4027589137
 159 id_pfr0=49
 160 id_pfr1=1
 161 midr=890224640
 162
 163 [system.cpu.itb]
 164 type=ArmTLB
 165 children=walker
 166 size=64
 167 walker=system.cpu.itb.walker
 168
 169 [system.cpu.itb.walker]
 170 type=ArmTableWalker
 171 clk_domain=system.cpu_clk_domain
 172 num_squash_per_cycle=2
 173 sys=system
 174 port=system.cpu.toL2Bus.slave[2]
 175
 176 [system.cpu.l2cache]
 177 type=BaseCache
 178 children=tags
 179 addr_ranges=0:18446744073709551615
 180 assoc=8
 181 clk_domain=system.cpu_clk_domain
 182 forward_snoops=true
 183 hit_latency=20
 184 is_top_level=false
 185 max_miss_count=0
 186 mshrs=20
 187 prefetch_on_access=false
 188 prefetcher=Null
 189 response_latency=20
 190 size=2097152
 191 system=system
 192 tags=system.cpu.l2cache.tags
 193 tgts_per_mshr=12
 194 two_queue=false
 195 write_buffers=8
 196 cpu_side=system.cpu.toL2Bus.master[0]
 197 mem_side=system.membus.slave[1]
 198
 199 [system.cpu.l2cache.tags]
 200 type=LRU
 201 assoc=8
 202 block_size=64
 203 clk_domain=system.cpu_clk_domain
 204 hit_latency=20
 205 size=2097152
 206
 207 [system.cpu.toL2Bus]
 208 type=CoherentBus
 209 clk_domain=system.cpu_clk_domain
 210 header_cycles=1
 211 system=system
 212 use_default_range=false
 213 width=32
 214 master=system.cpu.l2cache.cpu_side
 215 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 216
 217 [system.cpu.tracer]
 218 type=ExeTracer
 219
 220 [system.cpu.workload]
 221 type=LiveProcess
 222 cmd=vortex lendian.raw
 223 cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 224 egid=100
 225 env=
 226 errout=cerr
 227 euid=100
 228 executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 229 gid=100
 230 input=cin
 231 max_stack_size=67108864
 232 output=cout
 233 pid=100
 234 ppid=99
 235 simpoint=0
 236 system=system
 237 uid=100
 238
 239 [system.cpu_clk_domain]
 240 type=SrcClockDomain
 241 clock=500
 242 voltage_domain=system.voltage_domain
 243
 244 [system.membus]
 245 type=CoherentBus
 246 clk_domain=system.clk_domain
 247 header_cycles=1
 248 system=system
 249 use_default_range=false
 250 width=8
 251 master=system.physmem.port
 252 slave=system.system_port system.cpu.l2cache.mem_side
 253
 254 [system.physmem]
 255 type=SimpleMemory
 256 bandwidth=73.000000
 257 clk_domain=system.clk_domain
 258 conf_table_reported=true
 259 in_addr_map=true
 260 latency=30000
 261 latency_var=0
 262 null=false
 263 range=0:134217727
 264 port=system.membus.master[0]
 265
 266 [system.voltage_domain]
 267 type=VoltageDomain
 268 voltage=1.000000
 269