2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.132689 # Number of seconds simulated
4 sim_ticks 132689045000 # Number of ticks simulated
5 final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 525201 # Simulator instruction rate (inst/s)
8 host_op_rate 744748 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 990262559 # Simulator tick rate (ticks/s)
10 host_mem_usage 247408 # Number of bytes of host memory used
11 host_seconds 133.99 # Real time elapsed on the host
12 sim_insts 70373628 # Number of instructions simulated
13 sim_ops 99791654 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
37 system.membus.throughput 102119538 # Throughput (bytes/s)
38 system.membus.trans_dist::ReadReq 25532 # Transaction distribution
39 system.membus.trans_dist::ReadResp 25532 # Transaction distribution
40 system.membus.trans_dist::Writeback 83909 # Transaction distribution
41 system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
42 system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
43 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
44 system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
45 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
46 system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
47 system.membus.data_through_bus 13550144 # Total data (bytes)
48 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
49 system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
50 system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
51 system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks)
52 system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
53 system.cpu.dtb.inst_hits 0 # ITB inst hits
54 system.cpu.dtb.inst_misses 0 # ITB inst misses
55 system.cpu.dtb.read_hits 0 # DTB read hits
56 system.cpu.dtb.read_misses 0 # DTB read misses
57 system.cpu.dtb.write_hits 0 # DTB write hits
58 system.cpu.dtb.write_misses 0 # DTB write misses
59 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
60 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
61 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
62 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
63 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
64 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
65 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
66 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
67 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
68 system.cpu.dtb.read_accesses 0 # DTB read accesses
69 system.cpu.dtb.write_accesses 0 # DTB write accesses
70 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
71 system.cpu.dtb.hits 0 # DTB hits
72 system.cpu.dtb.misses 0 # DTB misses
73 system.cpu.dtb.accesses 0 # DTB accesses
74 system.cpu.itb.inst_hits 0 # ITB inst hits
75 system.cpu.itb.inst_misses 0 # ITB inst misses
76 system.cpu.itb.read_hits 0 # DTB read hits
77 system.cpu.itb.read_misses 0 # DTB read misses
78 system.cpu.itb.write_hits 0 # DTB write hits
79 system.cpu.itb.write_misses 0 # DTB write misses
80 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
81 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
82 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
83 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
84 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
85 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
86 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
87 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
88 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89 system.cpu.itb.read_accesses 0 # DTB read accesses
90 system.cpu.itb.write_accesses 0 # DTB write accesses
91 system.cpu.itb.inst_accesses 0 # ITB inst accesses
92 system.cpu.itb.hits 0 # DTB hits
93 system.cpu.itb.misses 0 # DTB misses
94 system.cpu.itb.accesses 0 # DTB accesses
95 system.cpu.workload.num_syscalls 1946 # Number of system calls
96 system.cpu.numCycles 265378090 # number of cpu cycles simulated
97 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
98 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
99 system.cpu.committedInsts 70373628 # Number of instructions committed
100 system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed
101 system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses
102 system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
103 system.cpu.num_func_calls 3311620 # number of times a function call or return occured
104 system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
105 system.cpu.num_int_insts 91472780 # number of integer instructions
106 system.cpu.num_fp_insts 56 # number of float instructions
107 system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read
108 system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
109 system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
110 system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
111 system.cpu.num_mem_refs 47862847 # number of memory refs
112 system.cpu.num_load_insts 27307108 # Number of load instructions
113 system.cpu.num_store_insts 20555739 # Number of store instructions
114 system.cpu.num_idle_cycles 0 # Number of idle cycles
115 system.cpu.num_busy_cycles 265378090 # Number of busy cycles
116 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
117 system.cpu.idle_fraction 0 # Percentage of idle cycles
118 system.cpu.icache.tags.replacements 16890 # number of replacements
119 system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
120 system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
121 system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
122 system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
123 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
124 system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
125 system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
126 system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy
127 system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
128 system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
129 system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
130 system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits
131 system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits
132 system.cpu.icache.overall_hits::total 78126161 # number of overall hits
133 system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
134 system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
135 system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
136 system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
137 system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
138 system.cpu.icache.overall_misses::total 18908 # number of overall misses
139 system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles
140 system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles
141 system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles
142 system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles
143 system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles
144 system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles
145 system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
146 system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
147 system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
148 system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses
149 system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses
150 system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses
151 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
152 system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
153 system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
154 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
155 system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
156 system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
157 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency
158 system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency
159 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
160 system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency
161 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
162 system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency
163 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
164 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
165 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
166 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
167 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
168 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
169 system.cpu.icache.fast_writes 0 # number of fast writes performed
170 system.cpu.icache.cache_copies 0 # number of cache copies performed
171 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
172 system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
173 system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses
174 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
175 system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
176 system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
177 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles
178 system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles
179 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles
180 system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles
181 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles
182 system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles
183 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
184 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
185 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
186 system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
187 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
188 system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
189 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency
190 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency
191 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
192 system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
193 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
194 system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
195 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
196 system.cpu.l2cache.tags.replacements 94693 # number of replacements
197 system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use
198 system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
199 system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
200 system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
201 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
202 system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
203 system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
204 system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
205 system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
206 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
207 system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
208 system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy
209 system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits
210 system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits
211 system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits
212 system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits
213 system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits
214 system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
215 system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
216 system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits
217 system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits
218 system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits
219 system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits
220 system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits
221 system.cpu.l2cache.overall_hits::total 51094 # number of overall hits
222 system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses
223 system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses
224 system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses
225 system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses
226 system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses
227 system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses
228 system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses
229 system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses
230 system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses
231 system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses
232 system.cpu.l2cache.overall_misses::total 127812 # number of overall misses
233 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles
234 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles
235 system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles
236 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles
237 system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles
238 system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles
239 system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles
240 system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles
241 system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles
242 system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles
243 system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles
244 system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
245 system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
246 system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
247 system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses)
248 system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses)
249 system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
250 system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
251 system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses
252 system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses
253 system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses
254 system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
255 system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
256 system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
257 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses
258 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses
259 system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses
260 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses
261 system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses
262 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses
263 system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses
264 system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses
265 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
266 system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
267 system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses
268 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency
269 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency
270 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency
271 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency
272 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency
273 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
274 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
275 system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency
276 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
277 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
278 system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency
279 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
280 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
281 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
282 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
283 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
284 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
285 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
286 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
287 system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks
288 system.cpu.l2cache.writebacks::total 83909 # number of writebacks
289 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses
290 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses
291 system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses
292 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
293 system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
294 system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses
295 system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses
296 system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses
297 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
298 system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
299 system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
300 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles
301 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles
302 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles
303 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles
304 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles
305 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles
306 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles
307 system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles
308 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles
309 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles
310 system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles
311 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
312 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
313 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
314 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses
315 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses
316 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses
317 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses
318 system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses
319 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
320 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
321 system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
322 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency
323 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency
324 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency
325 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency
326 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency
327 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
328 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
329 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
330 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
331 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
332 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
333 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
334 system.cpu.dcache.tags.replacements 155902 # number of replacements
335 system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use
336 system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks.
337 system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
338 system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks.
339 system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
340 system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
341 system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
342 system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy
343 system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
344 system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
345 system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
346 system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
347 system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
348 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
349 system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
350 system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
351 system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
352 system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
353 system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
354 system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
355 system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
356 system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
357 system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
358 system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
359 system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
360 system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
361 system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
362 system.cpu.dcache.overall_misses::total 159998 # number of overall misses
363 system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
364 system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
365 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
366 system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
367 system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
368 system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
369 system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
370 system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
371 system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
372 system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
373 system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
374 system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
375 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
376 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
377 system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
378 system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
379 system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
380 system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
381 system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
382 system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
383 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
384 system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
385 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
386 system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
387 system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
388 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
389 system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
390 system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
391 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
392 system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
393 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
394 system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
395 system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
396 system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
397 system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
398 system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
399 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
400 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
401 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
402 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
403 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
404 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
405 system.cpu.dcache.fast_writes 0 # number of fast writes performed
406 system.cpu.dcache.cache_copies 0 # number of cache copies performed
407 system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
408 system.cpu.dcache.writebacks::total 128239 # number of writebacks
409 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
410 system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
411 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
412 system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
413 system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
414 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
415 system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
416 system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
417 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
418 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
419 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
420 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
421 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
422 system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
423 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
424 system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
425 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
426 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
427 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
428 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
429 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
430 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
431 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
432 system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
433 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
434 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
435 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
436 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
437 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
438 system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
439 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
440 system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
441 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
442 system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s)
443 system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
444 system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
445 system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
446 system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
447 system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
448 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
449 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
450 system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
451 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
452 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
453 system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
454 system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
455 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
456 system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
457 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
458 system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
459 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
460 system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
461 system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
463 ---------- End Simulation Statistics ----------
projects / gem5.git / blob