stats: update stats for cache occupancy and clock domain changes
[gem5.git] / tests / long / se / 50.vortex / ref / sparc / linux / simple-timing / stats.txt
1
2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.202242 # Number of seconds simulated
4 sim_ticks 202242260000 # Number of ticks simulated
5 final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1441010 # Simulator instruction rate (inst/s)
8 host_op_rate 1459668 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2168416558 # Simulator tick rate (ticks/s)
10 host_mem_usage 246160 # Number of bytes of host memory used
11 host_seconds 93.27 # Real time elapsed on the host
12 sim_insts 134398962 # Number of instructions simulated
13 sim_ops 136139190 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
39 system.membus.throughput 67847660 # Throughput (bytes/s)
40 system.membus.trans_dist::ReadReq 30277 # Transaction distribution
41 system.membus.trans_dist::ReadResp 30277 # Transaction distribution
42 system.membus.trans_dist::Writeback 82868 # Transaction distribution
43 system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
44 system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
45 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
46 system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
47 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
48 system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
49 system.membus.data_through_bus 13721664 # Total data (bytes)
50 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51 system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
52 system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
53 system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
54 system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
55 system.cpu_clk_domain.clock 500 # Clock period in ticks
56 system.cpu.workload.num_syscalls 1946 # Number of system calls
57 system.cpu.numCycles 404484520 # number of cpu cycles simulated
58 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
59 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
60 system.cpu.committedInsts 134398962 # Number of instructions committed
61 system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
62 system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
63 system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
64 system.cpu.num_func_calls 1709332 # number of times a function call or return occured
65 system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
66 system.cpu.num_int_insts 115187746 # number of integer instructions
67 system.cpu.num_fp_insts 2326977 # number of float instructions
68 system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
69 system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written
70 system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
71 system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
72 system.cpu.num_mem_refs 58160248 # number of memory refs
73 system.cpu.num_load_insts 37275867 # Number of load instructions
74 system.cpu.num_store_insts 20884381 # Number of store instructions
75 system.cpu.num_idle_cycles 0 # Number of idle cycles
76 system.cpu.num_busy_cycles 404484520 # Number of busy cycles
77 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
78 system.cpu.idle_fraction 0 # Percentage of idle cycles
79 system.cpu.icache.tags.replacements 184976 # number of replacements
80 system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
81 system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
82 system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
83 system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
84 system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
85 system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
86 system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
87 system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
88 system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
89 system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
90 system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id
91 system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
92 system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id
93 system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id
94 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
95 system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses
96 system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses
97 system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
98 system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
99 system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
100 system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits
101 system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits
102 system.cpu.icache.overall_hits::total 134366547 # number of overall hits
103 system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
104 system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
105 system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses
106 system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
107 system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
108 system.cpu.icache.overall_misses::total 187024 # number of overall misses
109 system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles
110 system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles
111 system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles
112 system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles
113 system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles
114 system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles
115 system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
116 system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
117 system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
118 system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses
119 system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses
120 system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses
121 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
122 system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses
123 system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
124 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
125 system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
126 system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
127 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency
128 system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency
129 system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
130 system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency
131 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
132 system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency
133 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
134 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
135 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
136 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
137 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
138 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
139 system.cpu.icache.fast_writes 0 # number of fast writes performed
140 system.cpu.icache.cache_copies 0 # number of cache copies performed
141 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
142 system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses
143 system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
144 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
145 system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
146 system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
147 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles
148 system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles
149 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles
150 system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles
151 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles
152 system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles
153 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
154 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
155 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
156 system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
157 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
158 system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
159 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency
160 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency
161 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
162 system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
163 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
164 system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
165 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
166 system.cpu.l2cache.tags.replacements 98540 # number of replacements
167 system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use
168 system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
169 system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
170 system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
171 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
172 system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor
173 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
174 system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
175 system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
176 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
177 system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
178 system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy
179 system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id
180 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
181 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id
182 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id
183 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id
184 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id
185 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id
186 system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses
187 system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses
188 system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits
189 system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits
190 system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits
191 system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits
192 system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits
193 system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits
194 system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits
195 system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits
196 system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits
197 system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits
198 system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits
199 system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits
200 system.cpu.l2cache.overall_hits::total 206169 # number of overall hits
201 system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses
202 system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses
203 system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses
204 system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses
205 system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses
206 system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses
207 system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses
208 system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses
209 system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses
210 system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses
211 system.cpu.l2cache.overall_misses::total 131533 # number of overall misses
212 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles
213 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles
214 system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles
215 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles
216 system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles
217 system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles
218 system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles
219 system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles
220 system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles
221 system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles
222 system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles
223 system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
224 system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
225 system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
226 system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses)
227 system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses)
228 system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
229 system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
230 system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses
231 system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses
232 system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses
233 system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
234 system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses
235 system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses
236 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses
237 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses
238 system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses
239 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses
240 system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses
241 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses
242 system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses
243 system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses
244 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses
245 system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses
246 system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses
247 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency
248 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency
249 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency
250 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency
251 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency
252 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency
253 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
254 system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency
255 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency
256 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
257 system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency
258 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
259 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
260 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
261 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
262 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
263 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
264 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
265 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
266 system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks
267 system.cpu.l2cache.writebacks::total 82868 # number of writebacks
268 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses
269 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses
270 system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses
271 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses
272 system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses
273 system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses
274 system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses
275 system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses
276 system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses
277 system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses
278 system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses
279 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles
280 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles
281 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles
282 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles
283 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles
284 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles
285 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles
286 system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles
287 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles
288 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles
289 system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles
290 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses
291 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses
292 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses
293 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses
294 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses
295 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses
296 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses
297 system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses
298 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses
299 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses
300 system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses
301 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency
302 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency
303 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency
304 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency
305 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency
306 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
307 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
308 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
309 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
310 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
311 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
312 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
313 system.cpu.dcache.tags.replacements 146582 # number of replacements
314 system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use
315 system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
316 system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
317 system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
318 system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
319 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
320 system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
321 system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
322 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
323 system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
324 system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
325 system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
326 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
327 system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
328 system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
329 system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
330 system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
331 system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
332 system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
333 system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
334 system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
335 system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
336 system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
337 system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
338 system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
339 system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
340 system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
341 system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
342 system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
343 system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
344 system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
345 system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
346 system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
347 system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
348 system.cpu.dcache.overall_misses::total 150663 # number of overall misses
349 system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles
350 system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
351 system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles
352 system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
353 system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
354 system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
355 system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles
356 system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
357 system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles
358 system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
359 system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
360 system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
361 system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
362 system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
363 system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
364 system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
365 system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
366 system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
367 system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
368 system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
369 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
370 system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
371 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
372 system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
373 system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
374 system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
375 system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
376 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
377 system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
378 system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
379 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency
380 system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
381 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency
382 system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
383 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
384 system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
385 system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
386 system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
387 system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
388 system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
389 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
390 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
391 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
392 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
393 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
394 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
395 system.cpu.dcache.fast_writes 0 # number of fast writes performed
396 system.cpu.dcache.cache_copies 0 # number of cache copies performed
397 system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
398 system.cpu.dcache.writebacks::total 123970 # number of writebacks
399 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
400 system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
401 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
402 system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
403 system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
404 system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
405 system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
406 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
407 system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
408 system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
409 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
410 system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
411 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
412 system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
413 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
414 system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
415 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
416 system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
417 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
418 system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
419 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
420 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
421 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
422 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
423 system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
424 system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
425 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
426 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
427 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
428 system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
429 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
430 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
431 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
432 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
433 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
434 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
435 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
436 system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
437 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
438 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
439 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
440 system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s)
441 system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
442 system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
443 system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
444 system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
445 system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
446 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
447 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
448 system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
449 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
450 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
451 system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
452 system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
453 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
454 system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
455 system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
456 system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
457 system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
458 system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
459 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
460
461 ---------- End Simulation Statistics ----------