2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.017017 # Number of seconds simulated
4 sim_ticks 1017016979500 # Number of ticks simulated
5 final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 89946 # Simulator instruction rate (inst/s)
8 host_op_rate 89946 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50268200 # Simulator tick rate (ticks/s)
10 host_mem_usage 224748 # Number of bytes of host memory used
11 host_seconds 20231.82 # Real time elapsed on the host
12 sim_insts 1819780127 # Number of instructions simulated
13 sim_ops 1819780127 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller
38 system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller
39 system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
40 system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
41 system.physmem.bytesRead 125420224 # Total number of bytes read from memory
42 system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
43 system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize()
44 system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
45 system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q
46 system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
47 system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis
48 system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis
49 system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis
50 system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis
51 system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis
52 system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis
53 system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis
54 system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis
55 system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis
56 system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis
57 system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis
58 system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis
63 system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis
64 system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis
65 system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis
66 system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis
67 system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis
68 system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis
69 system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis
70 system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis
71 system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis
72 system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis
73 system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis
74 system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis
79 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
80 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
81 system.physmem.totGap 1017016906500 # Total gap between requests
82 system.physmem.readPktSize::0 0 # Categorize read packet sizes
83 system.physmem.readPktSize::1 0 # Categorize read packet sizes
84 system.physmem.readPktSize::2 0 # Categorize read packet sizes
85 system.physmem.readPktSize::3 0 # Categorize read packet sizes
86 system.physmem.readPktSize::4 0 # Categorize read packet sizes
87 system.physmem.readPktSize::5 0 # Categorize read packet sizes
88 system.physmem.readPktSize::6 1959691 # Categorize read packet sizes
89 system.physmem.writePktSize::0 0 # Categorize write packet sizes
90 system.physmem.writePktSize::1 0 # Categorize write packet sizes
91 system.physmem.writePktSize::2 0 # Categorize write packet sizes
92 system.physmem.writePktSize::3 0 # Categorize write packet sizes
93 system.physmem.writePktSize::4 0 # Categorize write packet sizes
94 system.physmem.writePktSize::5 0 # Categorize write packet sizes
95 system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
96 system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128 system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
160 system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation
161 system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation
162 system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation
163 system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation
164 system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation
165 system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation
166 system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation
167 system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation
168 system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation
169 system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation
170 system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation
171 system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation
293 system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays
294 system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests
295 system.physmem.totBusLat 9795575000 # Total cycles spent in databus access
296 system.physmem.totBankLat 54905317500 # Total cycles spent in bank access
297 system.physmem.avgQLat 17336.36 # Average queueing delay per request
298 system.physmem.avgBankLat 28025.57 # Average bank access latency per request
299 system.physmem.avgBusLat 5000.00 # Average bus latency per request
300 system.physmem.avgMemAccLat 50361.93 # Average memory access latency
301 system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s
302 system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s
303 system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s
304 system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s
305 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
306 system.physmem.busUtil 1.46 # Data bus utilization in percentage
307 system.physmem.avgRdQLen 0.10 # Average read queue length over time
308 system.physmem.avgWrQLen 10.57 # Average write queue length over time
309 system.physmem.readRowHits 900981 # Number of row buffer hits during reads
310 system.physmem.writeRowHits 351934 # Number of row buffer hits during writes
311 system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads
312 system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes
313 system.physmem.avgGap 341538.83 # Average gap between requests
314 system.membus.throughput 187387172 # Throughput (bytes/s)
315 system.membus.trans_dist::ReadReq 1178393 # Transaction distribution
316 system.membus.trans_dist::ReadResp 1178393 # Transaction distribution
317 system.membus.trans_dist::Writeback 1018058 # Transaction distribution
318 system.membus.trans_dist::ReadExReq 781298 # Transaction distribution
319 system.membus.trans_dist::ReadExResp 781298 # Transaction distribution
320 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes)
321 system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes)
322 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes)
323 system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes)
324 system.membus.data_through_bus 190575936 # Total data (bytes)
325 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
326 system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks)
327 system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
328 system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks)
329 system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
330 system.cpu.branchPred.lookups 326564713 # Number of BP lookups
331 system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted
332 system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect
333 system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups
334 system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits
335 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
336 system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage
337 system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
338 system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
339 system.cpu.dtb.fetch_hits 0 # ITB hits
340 system.cpu.dtb.fetch_misses 0 # ITB misses
341 system.cpu.dtb.fetch_acv 0 # ITB acv
342 system.cpu.dtb.fetch_accesses 0 # ITB accesses
343 system.cpu.dtb.read_hits 444840309 # DTB read hits
344 system.cpu.dtb.read_misses 4897078 # DTB read misses
345 system.cpu.dtb.read_acv 0 # DTB read access violations
346 system.cpu.dtb.read_accesses 449737387 # DTB read accesses
347 system.cpu.dtb.write_hits 160847153 # DTB write hits
348 system.cpu.dtb.write_misses 1701304 # DTB write misses
349 system.cpu.dtb.write_acv 0 # DTB write access violations
350 system.cpu.dtb.write_accesses 162548457 # DTB write accesses
351 system.cpu.dtb.data_hits 605687462 # DTB hits
352 system.cpu.dtb.data_misses 6598382 # DTB misses
353 system.cpu.dtb.data_acv 0 # DTB access violations
354 system.cpu.dtb.data_accesses 612285844 # DTB accesses
355 system.cpu.itb.fetch_hits 231947501 # ITB hits
356 system.cpu.itb.fetch_misses 22 # ITB misses
357 system.cpu.itb.fetch_acv 0 # ITB acv
358 system.cpu.itb.fetch_accesses 231947523 # ITB accesses
359 system.cpu.itb.read_hits 0 # DTB read hits
360 system.cpu.itb.read_misses 0 # DTB read misses
361 system.cpu.itb.read_acv 0 # DTB read access violations
362 system.cpu.itb.read_accesses 0 # DTB read accesses
363 system.cpu.itb.write_hits 0 # DTB write hits
364 system.cpu.itb.write_misses 0 # DTB write misses
365 system.cpu.itb.write_acv 0 # DTB write access violations
366 system.cpu.itb.write_accesses 0 # DTB write accesses
367 system.cpu.itb.data_hits 0 # DTB hits
368 system.cpu.itb.data_misses 0 # DTB misses
369 system.cpu.itb.data_acv 0 # DTB access violations
370 system.cpu.itb.data_accesses 0 # DTB accesses
371 system.cpu.workload.num_syscalls 29 # Number of system calls
372 system.cpu.numCycles 2034033960 # number of cpu cycles simulated
373 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
374 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
375 system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True).
376 system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False).
377 system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File
378 system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
379 system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File
380 system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
381 system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
382 system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
383 system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic
384 system.cpu.agen_unit.agens 617884714 # Number of Address Generations
385 system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken.
386 system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken).
387 system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted
388 system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted
389 system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts
390 system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed.
391 system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
392 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
393 system.cpu.contextSwitches 1 # Number of context switches
394 system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
395 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
396 system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself
397 system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed
398 system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed.
399 system.cpu.activity 77.269597 # Percentage of cycles cpu is active
400 system.cpu.comLoads 444595663 # Number of Load instructions committed
401 system.cpu.comStores 160728502 # Number of Store instructions committed
402 system.cpu.comBranches 214632552 # Number of Branches instructions committed
403 system.cpu.comNops 83736345 # Number of Nop instructions committed
404 system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
405 system.cpu.comInts 916086844 # Number of Integer instructions committed
406 system.cpu.comFloats 190 # Number of Floating Point instructions committed
407 system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
408 system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
409 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
410 system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
411 system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread)
412 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
413 system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads
414 system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread)
415 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
416 system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads
417 system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed.
418 system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed.
419 system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts).
420 system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed.
421 system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed.
422 system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts).
423 system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed.
424 system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed.
425 system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts).
426 system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed.
427 system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed.
428 system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts).
429 system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed.
430 system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed.
431 system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts).
432 system.cpu.icache.tags.replacements 1 # number of replacements
433 system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use
434 system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks.
435 system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
436 system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks.
437 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
438 system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor
439 system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy
440 system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy
441 system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits
442 system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits
443 system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits
444 system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits
445 system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits
446 system.cpu.icache.overall_hits::total 231946364 # number of overall hits
447 system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses
448 system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses
449 system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses
450 system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses
451 system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses
452 system.cpu.icache.overall_misses::total 1137 # number of overall misses
453 system.cpu.icache.ReadReq_miss_latency::cpu.inst 82490250 # number of ReadReq miss cycles
454 system.cpu.icache.ReadReq_miss_latency::total 82490250 # number of ReadReq miss cycles
455 system.cpu.icache.demand_miss_latency::cpu.inst 82490250 # number of demand (read+write) miss cycles
456 system.cpu.icache.demand_miss_latency::total 82490250 # number of demand (read+write) miss cycles
457 system.cpu.icache.overall_miss_latency::cpu.inst 82490250 # number of overall miss cycles
458 system.cpu.icache.overall_miss_latency::total 82490250 # number of overall miss cycles
459 system.cpu.icache.ReadReq_accesses::cpu.inst 231947501 # number of ReadReq accesses(hits+misses)
460 system.cpu.icache.ReadReq_accesses::total 231947501 # number of ReadReq accesses(hits+misses)
461 system.cpu.icache.demand_accesses::cpu.inst 231947501 # number of demand (read+write) accesses
462 system.cpu.icache.demand_accesses::total 231947501 # number of demand (read+write) accesses
463 system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses
464 system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses
465 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
466 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
467 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
468 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
469 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
470 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
471 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency
472 system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency
473 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency
474 system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency
475 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency
476 system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency
477 system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked
478 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
479 system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
480 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
481 system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked
482 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
483 system.cpu.icache.fast_writes 0 # number of fast writes performed
484 system.cpu.icache.cache_copies 0 # number of cache copies performed
485 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits
486 system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits
487 system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits
488 system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits
489 system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits
490 system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits
491 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
492 system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
493 system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
494 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
495 system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
496 system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
497 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65194000 # number of ReadReq MSHR miss cycles
498 system.cpu.icache.ReadReq_mshr_miss_latency::total 65194000 # number of ReadReq MSHR miss cycles
499 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65194000 # number of demand (read+write) MSHR miss cycles
500 system.cpu.icache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles
501 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65194000 # number of overall MSHR miss cycles
502 system.cpu.icache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles
503 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
504 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
505 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
506 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
507 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
508 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
509 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75895.227008 # average ReadReq mshr miss latency
510 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75895.227008 # average ReadReq mshr miss latency
511 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency
512 system.cpu.icache.demand_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency
513 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency
514 system.cpu.icache.overall_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency
515 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
516 system.cpu.toL2Bus.throughput 805844654 # Throughput (bytes/s)
517 system.cpu.toL2Bus.trans_dist::ReadReq 7222689 # Transaction distribution
518 system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Transaction distribution
519 system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution
520 system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution
521 system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution
522 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
523 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes)
524 system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes)
525 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
526 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes)
527 system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes)
528 system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes)
529 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
530 system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks)
531 system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
532 system.cpu.toL2Bus.respLayer0.occupancy 1466500 # Layer occupancy (ticks)
533 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
534 system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks)
535 system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
536 system.cpu.l2cache.tags.replacements 1926960 # number of replacements
537 system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use
538 system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks.
539 system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks.
540 system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks.
541 system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit.
542 system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor
543 system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor
544 system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor
545 system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy
546 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy
547 system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy
548 system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy
549 system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits
550 system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits
551 system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits
552 system.cpu.l2cache.Writeback_hits::total 3693279 # number of Writeback hits
553 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108323 # number of ReadExReq hits
554 system.cpu.l2cache.ReadExReq_hits::total 1108323 # number of ReadExReq hits
555 system.cpu.l2cache.demand_hits::cpu.data 7152619 # number of demand (read+write) hits
556 system.cpu.l2cache.demand_hits::total 7152619 # number of demand (read+write) hits
557 system.cpu.l2cache.overall_hits::cpu.data 7152619 # number of overall hits
558 system.cpu.l2cache.overall_hits::total 7152619 # number of overall hits
559 system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
560 system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses
561 system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses
562 system.cpu.l2cache.ReadExReq_misses::cpu.data 781298 # number of ReadExReq misses
563 system.cpu.l2cache.ReadExReq_misses::total 781298 # number of ReadExReq misses
564 system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
565 system.cpu.l2cache.demand_misses::cpu.data 1958832 # number of demand (read+write) misses
566 system.cpu.l2cache.demand_misses::total 1959691 # number of demand (read+write) misses
567 system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
568 system.cpu.l2cache.overall_misses::cpu.data 1958832 # number of overall misses
569 system.cpu.l2cache.overall_misses::total 1959691 # number of overall misses
570 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64331000 # number of ReadReq miss cycles
571 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104087297000 # number of ReadReq miss cycles
572 system.cpu.l2cache.ReadReq_miss_latency::total 104151628000 # number of ReadReq miss cycles
573 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79166748750 # number of ReadExReq miss cycles
574 system.cpu.l2cache.ReadExReq_miss_latency::total 79166748750 # number of ReadExReq miss cycles
575 system.cpu.l2cache.demand_miss_latency::cpu.inst 64331000 # number of demand (read+write) miss cycles
576 system.cpu.l2cache.demand_miss_latency::cpu.data 183254045750 # number of demand (read+write) miss cycles
577 system.cpu.l2cache.demand_miss_latency::total 183318376750 # number of demand (read+write) miss cycles
578 system.cpu.l2cache.overall_miss_latency::cpu.inst 64331000 # number of overall miss cycles
579 system.cpu.l2cache.overall_miss_latency::cpu.data 183254045750 # number of overall miss cycles
580 system.cpu.l2cache.overall_miss_latency::total 183318376750 # number of overall miss cycles
581 system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
582 system.cpu.l2cache.ReadReq_accesses::cpu.data 7221830 # number of ReadReq accesses(hits+misses)
583 system.cpu.l2cache.ReadReq_accesses::total 7222689 # number of ReadReq accesses(hits+misses)
584 system.cpu.l2cache.Writeback_accesses::writebacks 3693279 # number of Writeback accesses(hits+misses)
585 system.cpu.l2cache.Writeback_accesses::total 3693279 # number of Writeback accesses(hits+misses)
586 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889621 # number of ReadExReq accesses(hits+misses)
587 system.cpu.l2cache.ReadExReq_accesses::total 1889621 # number of ReadExReq accesses(hits+misses)
588 system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
589 system.cpu.l2cache.demand_accesses::cpu.data 9111451 # number of demand (read+write) accesses
590 system.cpu.l2cache.demand_accesses::total 9112310 # number of demand (read+write) accesses
591 system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
592 system.cpu.l2cache.overall_accesses::cpu.data 9111451 # number of overall (read+write) accesses
593 system.cpu.l2cache.overall_accesses::total 9112310 # number of overall (read+write) accesses
594 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
595 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
596 system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses
597 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses
598 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses
599 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
600 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses
601 system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses
602 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
603 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses
604 system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses
605 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74890.570431 # average ReadReq miss latency
606 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88394.302840 # average ReadReq miss latency
607 system.cpu.l2cache.ReadReq_avg_miss_latency::total 88384.459174 # average ReadReq miss latency
608 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101327.212856 # average ReadExReq miss latency
609 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101327.212856 # average ReadExReq miss latency
610 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency
611 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency
612 system.cpu.l2cache.demand_avg_miss_latency::total 93544.531638 # average overall miss latency
613 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency
614 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency
615 system.cpu.l2cache.overall_avg_miss_latency::total 93544.531638 # average overall miss latency
616 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
617 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
618 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
619 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
620 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
621 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
622 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
623 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
624 system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks
625 system.cpu.l2cache.writebacks::total 1018058 # number of writebacks
626 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
627 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses
628 system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses
629 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses
630 system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses
631 system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
632 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958832 # number of demand (read+write) MSHR misses
633 system.cpu.l2cache.demand_mshr_misses::total 1959691 # number of demand (read+write) MSHR misses
634 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
635 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958832 # number of overall MSHR misses
636 system.cpu.l2cache.overall_mshr_misses::total 1959691 # number of overall MSHR misses
637 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53514000 # number of ReadReq MSHR miss cycles
638 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89157154500 # number of ReadReq MSHR miss cycles
639 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89210668500 # number of ReadReq MSHR miss cycles
640 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69321257750 # number of ReadExReq MSHR miss cycles
641 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69321257750 # number of ReadExReq MSHR miss cycles
642 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53514000 # number of demand (read+write) MSHR miss cycles
643 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158478412250 # number of demand (read+write) MSHR miss cycles
644 system.cpu.l2cache.demand_mshr_miss_latency::total 158531926250 # number of demand (read+write) MSHR miss cycles
645 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53514000 # number of overall MSHR miss cycles
646 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158478412250 # number of overall MSHR miss cycles
647 system.cpu.l2cache.overall_mshr_miss_latency::total 158531926250 # number of overall MSHR miss cycles
648 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
649 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
650 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses
651 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses
652 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses
653 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
654 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses
655 system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses
656 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
657 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses
658 system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses
659 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62298.020955 # average ReadReq mshr miss latency
660 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75715.142408 # average ReadReq mshr miss latency
661 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75705.361878 # average ReadReq mshr miss latency
662 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88725.758609 # average ReadExReq mshr miss latency
663 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88725.758609 # average ReadExReq mshr miss latency
664 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency
665 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency
666 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency
667 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency
668 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency
669 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency
670 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
671 system.cpu.dcache.tags.replacements 9107355 # number of replacements
672 system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use
673 system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks.
674 system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks.
675 system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks.
676 system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit.
677 system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor
678 system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy
679 system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
680 system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits
681 system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits
682 system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits
683 system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits
684 system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits
685 system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits
686 system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits
687 system.cpu.dcache.overall_hits::total 593297569 # number of overall hits
688 system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses
689 system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses
690 system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses
691 system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses
692 system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses
693 system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses
694 system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses
695 system.cpu.dcache.overall_misses::total 12026596 # number of overall misses
696 system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles
697 system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles
698 system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles
699 system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles
700 system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles
701 system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles
702 system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles
703 system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles
704 system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
705 system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
706 system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
707 system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
708 system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
709 system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
710 system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
711 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
712 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
713 system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
714 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses
715 system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses
716 system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses
717 system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses
718 system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses
719 system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses
720 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency
721 system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency
722 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency
723 system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency
724 system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency
725 system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency
726 system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency
727 system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency
728 system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked
729 system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked
730 system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked
731 system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked
732 system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked
733 system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked
734 system.cpu.dcache.fast_writes 0 # number of fast writes performed
735 system.cpu.dcache.cache_copies 0 # number of cache copies performed
736 system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks
737 system.cpu.dcache.writebacks::total 3693279 # number of writebacks
738 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits
739 system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits
740 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits
741 system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits
742 system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits
743 system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits
744 system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits
745 system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits
746 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses
747 system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses
748 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses
749 system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses
750 system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses
751 system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses
752 system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses
753 system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses
754 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles
755 system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles
756 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles
757 system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles
758 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles
759 system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles
760 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles
761 system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles
762 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
763 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
764 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
765 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
766 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
767 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
768 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
769 system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
770 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency
771 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency
772 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency
773 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency
774 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency
775 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency
776 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency
777 system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency
778 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
780 ---------- End Simulation Statistics ----------
projects / gem5.git / blob