2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.005768 # Number of seconds simulated
4 sim_ticks 1005767806500 # Number of ticks simulated
5 final_tick 1005767806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 106626 # Simulator instruction rate (inst/s)
8 host_op_rate 106626 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 58930745 # Simulator tick rate (ticks/s)
10 host_mem_usage 266468 # Number of bytes of host memory used
11 host_seconds 17066.95 # Real time elapsed on the host
12 sim_insts 1819780127 # Number of instructions simulated
13 sim_ops 1819780127 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125365120 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 125420096 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1958830 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1959689 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 54661 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 124646185 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 124700846 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 54661 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 54661 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 64781934 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 64781934 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 64781934 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 54661 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 124646185 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 189482780 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 1959689 # Number of read requests accepted
40 system.physmem.writeReqs 1018056 # Number of write requests accepted
41 system.physmem.readBursts 1959689 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 1018056 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 125339392 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 80704 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 65154112 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 125420096 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 65155584 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 1261 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 118688 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 114039 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 116164 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 117666 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 117733 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 117466 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 119809 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 124448 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 126913 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 130015 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 128579 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 130223 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 125906 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 125163 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 122509 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 123107 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 61223 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 61467 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 60558 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 61216 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 61647 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 63085 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 64137 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 65614 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 65332 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 65770 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 65297 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 65611 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 64139 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 64200 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 64551 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 64186 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 1005767733500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 1959689 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 1018056 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 1667897 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 193105 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 75870 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 21555 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 29926 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 31516 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 51008 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 56043 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 59405 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 60493 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 60664 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 60587 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 60540 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 60592 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 60684 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 60779 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 62031 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 62029 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 60742 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 61437 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 59898 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 59460 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 159 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 1810756 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 105.200206 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 81.912098 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 131.997170 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 1417049 78.26% 78.26% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 275870 15.24% 93.49% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 50109 2.77% 96.26% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 20785 1.15% 97.41% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 12643 0.70% 98.11% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 6844 0.38% 98.48% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 5544 0.31% 98.79% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 3818 0.21% 99.00% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 18094 1.00% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 1810756 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 59345 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 32.999023 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 160.520477 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 59305 99.93% 99.93% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.95% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::total 59345 # Reads before turning the bus around for writes
226 system.physmem.wrPerTurnAround::samples 59345 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::mean 17.154486 # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::gmean 17.116028 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::stdev 1.157894 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::16 27533 46.39% 46.39% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::17 1478 2.49% 48.89% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::18 25288 42.61% 91.50% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::19 4106 6.92% 98.42% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::20 708 1.19% 99.61% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::21 151 0.25% 99.86% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::22 51 0.09% 99.95% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::23 15 0.03% 99.97% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::24 6 0.01% 99.98% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::25 2 0.00% 99.99% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::26 4 0.01% 99.99% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::total 59345 # Writes before turning the bus around for reads
244 system.physmem.totQLat 39644301500 # Total ticks spent queuing
245 system.physmem.totMemAccLat 76364826500 # Total ticks spent from burst creation until serviced by the DRAM
246 system.physmem.totBusLat 9792140000 # Total ticks spent in databus transfers
247 system.physmem.avgQLat 20242.92 # Average queueing delay per DRAM burst
248 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
249 system.physmem.avgMemAccLat 38992.92 # Average memory access latency per DRAM burst
250 system.physmem.avgRdBW 124.62 # Average DRAM read bandwidth in MiByte/s
251 system.physmem.avgWrBW 64.78 # Average achieved write bandwidth in MiByte/s
252 system.physmem.avgRdBWSys 124.70 # Average system read bandwidth in MiByte/s
253 system.physmem.avgWrBWSys 64.78 # Average system write bandwidth in MiByte/s
254 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
255 system.physmem.busUtil 1.48 # Data bus utilization in percentage
256 system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads
257 system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes
258 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
259 system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing
260 system.physmem.readRowHits 749188 # Number of row buffer hits during reads
261 system.physmem.writeRowHits 416511 # Number of row buffer hits during writes
262 system.physmem.readRowHitRate 38.25 # Row buffer hit rate for reads
263 system.physmem.writeRowHitRate 40.91 # Row buffer hit rate for writes
264 system.physmem.avgGap 337761.54 # Average gap between requests
265 system.physmem.pageHitRate 39.16 # Row buffer hit rate, read and write combined
266 system.physmem.memoryStateTime::IDLE 297166155500 # Time in different power states
267 system.physmem.memoryStateTime::REF 33584720000 # Time in different power states
268 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
269 system.physmem.memoryStateTime::ACT 675014883250 # Time in different power states
270 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
271 system.membus.throughput 189482780 # Throughput (bytes/s)
272 system.membus.trans_dist::ReadReq 1178393 # Transaction distribution
273 system.membus.trans_dist::ReadResp 1178393 # Transaction distribution
274 system.membus.trans_dist::Writeback 1018056 # Transaction distribution
275 system.membus.trans_dist::ReadExReq 781296 # Transaction distribution
276 system.membus.trans_dist::ReadExResp 781296 # Transaction distribution
277 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937434 # Packet count per connected master and slave (bytes)
278 system.membus.pkt_count::total 4937434 # Packet count per connected master and slave (bytes)
279 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575680 # Cumulative packet size per connected master and slave (bytes)
280 system.membus.tot_pkt_size::total 190575680 # Cumulative packet size per connected master and slave (bytes)
281 system.membus.data_through_bus 190575680 # Total data (bytes)
282 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
283 system.membus.reqLayer0.occupancy 11779296500 # Layer occupancy (ticks)
284 system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
285 system.membus.respLayer1.occupancy 18345408000 # Layer occupancy (ticks)
286 system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
287 system.cpu_clk_domain.clock 500 # Clock period in ticks
288 system.cpu.branchPred.lookups 326515024 # Number of BP lookups
289 system.cpu.branchPred.condPredicted 252570896 # Number of conditional branches predicted
290 system.cpu.branchPred.condIncorrect 138240520 # Number of conditional branches incorrect
291 system.cpu.branchPred.BTBLookups 220728385 # Number of BTB lookups
292 system.cpu.branchPred.BTBHits 135412850 # Number of BTB hits
293 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
294 system.cpu.branchPred.BTBHitPct 61.348181 # BTB Hit Percentage
295 system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
296 system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
297 system.cpu.dtb.fetch_hits 0 # ITB hits
298 system.cpu.dtb.fetch_misses 0 # ITB misses
299 system.cpu.dtb.fetch_acv 0 # ITB acv
300 system.cpu.dtb.fetch_accesses 0 # ITB accesses
301 system.cpu.dtb.read_hits 444825863 # DTB read hits
302 system.cpu.dtb.read_misses 4897078 # DTB read misses
303 system.cpu.dtb.read_acv 0 # DTB read access violations
304 system.cpu.dtb.read_accesses 449722941 # DTB read accesses
305 system.cpu.dtb.write_hits 160844247 # DTB write hits
306 system.cpu.dtb.write_misses 1701304 # DTB write misses
307 system.cpu.dtb.write_acv 0 # DTB write access violations
308 system.cpu.dtb.write_accesses 162545551 # DTB write accesses
309 system.cpu.dtb.data_hits 605670110 # DTB hits
310 system.cpu.dtb.data_misses 6598382 # DTB misses
311 system.cpu.dtb.data_acv 0 # DTB access violations
312 system.cpu.dtb.data_accesses 612268492 # DTB accesses
313 system.cpu.itb.fetch_hits 231919747 # ITB hits
314 system.cpu.itb.fetch_misses 22 # ITB misses
315 system.cpu.itb.fetch_acv 0 # ITB acv
316 system.cpu.itb.fetch_accesses 231919769 # ITB accesses
317 system.cpu.itb.read_hits 0 # DTB read hits
318 system.cpu.itb.read_misses 0 # DTB read misses
319 system.cpu.itb.read_acv 0 # DTB read access violations
320 system.cpu.itb.read_accesses 0 # DTB read accesses
321 system.cpu.itb.write_hits 0 # DTB write hits
322 system.cpu.itb.write_misses 0 # DTB write misses
323 system.cpu.itb.write_acv 0 # DTB write access violations
324 system.cpu.itb.write_accesses 0 # DTB write accesses
325 system.cpu.itb.data_hits 0 # DTB hits
326 system.cpu.itb.data_misses 0 # DTB misses
327 system.cpu.itb.data_acv 0 # DTB access violations
328 system.cpu.itb.data_accesses 0 # DTB accesses
329 system.cpu.workload.num_syscalls 29 # Number of system calls
330 system.cpu.numCycles 2011535614 # number of cpu cycles simulated
331 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
332 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
333 system.cpu.branch_predictor.predictedTaken 172226277 # Number of Branches Predicted As Taken (True).
334 system.cpu.branch_predictor.predictedNotTaken 154288747 # Number of Branches Predicted As Not Taken (False).
335 system.cpu.regfile_manager.intRegFileReads 1667639381 # Number of Reads from Int. Register File
336 system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
337 system.cpu.regfile_manager.intRegFileAccesses 3043841998 # Total Accesses (Read+Write) to the Int. Register File
338 system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
339 system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
340 system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
341 system.cpu.regfile_manager.regForwards 651725578 # Number of Registers Read Through Forwarding Logic
342 system.cpu.agen_unit.agens 617883712 # Number of Address Generations
343 system.cpu.execution_unit.predictedTakenIncorrect 120527925 # Number of Branches Incorrectly Predicted As Taken.
344 system.cpu.execution_unit.predictedNotTakenIncorrect 11114137 # Number of Branches Incorrectly Predicted As Not Taken).
345 system.cpu.execution_unit.mispredicted 131642062 # Number of Branches Incorrectly Predicted
346 system.cpu.execution_unit.predicted 83557916 # Number of Branches Incorrectly Predicted
347 system.cpu.execution_unit.mispredictPct 61.171968 # Percentage of Incorrect Branches Predicts
348 system.cpu.execution_unit.executions 1139358188 # Number of Instructions Executed.
349 system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
350 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
351 system.cpu.contextSwitches 1 # Number of context switches
352 system.cpu.threadCycles 1742007028 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
353 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
354 system.cpu.timesIdled 7502506 # Number of times that the entire CPU went into an idle state and unscheduled itself
355 system.cpu.idleCycles 439794636 # Number of cycles cpu's stages were not processed
356 system.cpu.runCycles 1571740978 # Number of cycles cpu stages are processed.
357 system.cpu.activity 78.136373 # Percentage of cycles cpu is active
358 system.cpu.comLoads 444595663 # Number of Load instructions committed
359 system.cpu.comStores 160728502 # Number of Store instructions committed
360 system.cpu.comBranches 214632552 # Number of Branches instructions committed
361 system.cpu.comNops 83736345 # Number of Nop instructions committed
362 system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
363 system.cpu.comInts 916086844 # Number of Integer instructions committed
364 system.cpu.comFloats 190 # Number of Floating Point instructions committed
365 system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
366 system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
367 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
368 system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
369 system.cpu.cpi 1.105373 # CPI: Cycles Per Instruction (Per-Thread)
370 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
371 system.cpu.cpi_total 1.105373 # CPI: Total CPI of All Threads
372 system.cpu.ipc 0.904672 # IPC: Instructions Per Cycle (Per-Thread)
373 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
374 system.cpu.ipc_total 0.904672 # IPC: Total IPC of All Threads
375 system.cpu.stage0.idleCycles 824896841 # Number of cycles 0 instructions are processed.
376 system.cpu.stage0.runCycles 1186638773 # Number of cycles 1+ instructions are processed.
377 system.cpu.stage0.utilization 58.991686 # Percentage of cycles stage was utilized (processing insts).
378 system.cpu.stage1.idleCycles 1077691733 # Number of cycles 0 instructions are processed.
379 system.cpu.stage1.runCycles 933843881 # Number of cycles 1+ instructions are processed.
380 system.cpu.stage1.utilization 46.424427 # Percentage of cycles stage was utilized (processing insts).
381 system.cpu.stage2.idleCycles 1039140389 # Number of cycles 0 instructions are processed.
382 system.cpu.stage2.runCycles 972395225 # Number of cycles 1+ instructions are processed.
383 system.cpu.stage2.utilization 48.340940 # Percentage of cycles stage was utilized (processing insts).
384 system.cpu.stage3.idleCycles 1601912902 # Number of cycles 0 instructions are processed.
385 system.cpu.stage3.runCycles 409622712 # Number of cycles 1+ instructions are processed.
386 system.cpu.stage3.utilization 20.363682 # Percentage of cycles stage was utilized (processing insts).
387 system.cpu.stage4.idleCycles 990187341 # Number of cycles 0 instructions are processed.
388 system.cpu.stage4.runCycles 1021348273 # Number of cycles 1+ instructions are processed.
389 system.cpu.stage4.utilization 50.774556 # Percentage of cycles stage was utilized (processing insts).
390 system.cpu.icache.tags.replacements 1 # number of replacements
391 system.cpu.icache.tags.tagsinuse 668.237280 # Cycle average of tags in use
392 system.cpu.icache.tags.total_refs 231918592 # Total number of references to valid blocks.
393 system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
394 system.cpu.icache.tags.avg_refs 269986.719441 # Average number of references to valid blocks.
395 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
396 system.cpu.icache.tags.occ_blocks::cpu.inst 668.237280 # Average occupied blocks per requestor
397 system.cpu.icache.tags.occ_percent::cpu.inst 0.326288 # Average percentage of cache occupancy
398 system.cpu.icache.tags.occ_percent::total 0.326288 # Average percentage of cache occupancy
399 system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id
400 system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
401 system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id
402 system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id
403 system.cpu.icache.tags.tag_accesses 463840351 # Number of tag accesses
404 system.cpu.icache.tags.data_accesses 463840351 # Number of data accesses
405 system.cpu.icache.ReadReq_hits::cpu.inst 231918592 # number of ReadReq hits
406 system.cpu.icache.ReadReq_hits::total 231918592 # number of ReadReq hits
407 system.cpu.icache.demand_hits::cpu.inst 231918592 # number of demand (read+write) hits
408 system.cpu.icache.demand_hits::total 231918592 # number of demand (read+write) hits
409 system.cpu.icache.overall_hits::cpu.inst 231918592 # number of overall hits
410 system.cpu.icache.overall_hits::total 231918592 # number of overall hits
411 system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
412 system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
413 system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
414 system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
415 system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
416 system.cpu.icache.overall_misses::total 1154 # number of overall misses
417 system.cpu.icache.ReadReq_miss_latency::cpu.inst 83508500 # number of ReadReq miss cycles
418 system.cpu.icache.ReadReq_miss_latency::total 83508500 # number of ReadReq miss cycles
419 system.cpu.icache.demand_miss_latency::cpu.inst 83508500 # number of demand (read+write) miss cycles
420 system.cpu.icache.demand_miss_latency::total 83508500 # number of demand (read+write) miss cycles
421 system.cpu.icache.overall_miss_latency::cpu.inst 83508500 # number of overall miss cycles
422 system.cpu.icache.overall_miss_latency::total 83508500 # number of overall miss cycles
423 system.cpu.icache.ReadReq_accesses::cpu.inst 231919746 # number of ReadReq accesses(hits+misses)
424 system.cpu.icache.ReadReq_accesses::total 231919746 # number of ReadReq accesses(hits+misses)
425 system.cpu.icache.demand_accesses::cpu.inst 231919746 # number of demand (read+write) accesses
426 system.cpu.icache.demand_accesses::total 231919746 # number of demand (read+write) accesses
427 system.cpu.icache.overall_accesses::cpu.inst 231919746 # number of overall (read+write) accesses
428 system.cpu.icache.overall_accesses::total 231919746 # number of overall (read+write) accesses
429 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
430 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
431 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
432 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
433 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
434 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
435 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72364.384749 # average ReadReq miss latency
436 system.cpu.icache.ReadReq_avg_miss_latency::total 72364.384749 # average ReadReq miss latency
437 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency
438 system.cpu.icache.demand_avg_miss_latency::total 72364.384749 # average overall miss latency
439 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency
440 system.cpu.icache.overall_avg_miss_latency::total 72364.384749 # average overall miss latency
441 system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked
442 system.cpu.icache.blocked_cycles::no_targets 418 # number of cycles access was blocked
443 system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
444 system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
445 system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked
446 system.cpu.icache.avg_blocked_cycles::no_targets 418 # average number of cycles each access was blocked
447 system.cpu.icache.fast_writes 0 # number of fast writes performed
448 system.cpu.icache.cache_copies 0 # number of cache copies performed
449 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits
450 system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits
451 system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits
452 system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits
453 system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits
454 system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits
455 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
456 system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
457 system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
458 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
459 system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
460 system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
461 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61831500 # number of ReadReq MSHR miss cycles
462 system.cpu.icache.ReadReq_mshr_miss_latency::total 61831500 # number of ReadReq MSHR miss cycles
463 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61831500 # number of demand (read+write) MSHR miss cycles
464 system.cpu.icache.demand_mshr_miss_latency::total 61831500 # number of demand (read+write) MSHR miss cycles
465 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61831500 # number of overall MSHR miss cycles
466 system.cpu.icache.overall_mshr_miss_latency::total 61831500 # number of overall MSHR miss cycles
467 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
468 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
469 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
470 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
471 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
472 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
473 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71980.791618 # average ReadReq mshr miss latency
474 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71980.791618 # average ReadReq mshr miss latency
475 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency
476 system.cpu.icache.demand_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency
477 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency
478 system.cpu.icache.overall_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency
479 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
480 system.cpu.toL2Bus.throughput 814858454 # Throughput (bytes/s)
481 system.cpu.toL2Bus.trans_dist::ReadReq 7222692 # Transaction distribution
482 system.cpu.toL2Bus.trans_dist::ReadResp 7222692 # Transaction distribution
483 system.cpu.toL2Bus.trans_dist::Writeback 3693285 # Transaction distribution
484 system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution
485 system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution
486 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
487 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916197 # Packet count per connected master and slave (bytes)
488 system.cpu.toL2Bus.pkt_count::total 21917915 # Packet count per connected master and slave (bytes)
489 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
490 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503424 # Cumulative packet size per connected master and slave (bytes)
491 system.cpu.toL2Bus.tot_pkt_size::total 819558400 # Cumulative packet size per connected master and slave (bytes)
492 system.cpu.toL2Bus.data_through_bus 819558400 # Total data (bytes)
493 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
494 system.cpu.toL2Bus.reqLayer0.occupancy 10096085000 # Layer occupancy (ticks)
495 system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
496 system.cpu.toL2Bus.respLayer0.occupancy 1445000 # Layer occupancy (ticks)
497 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
498 system.cpu.toL2Bus.respLayer1.occupancy 13977776250 # Layer occupancy (ticks)
499 system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
500 system.cpu.l2cache.tags.replacements 1926959 # number of replacements
501 system.cpu.l2cache.tags.tagsinuse 30915.615811 # Cycle average of tags in use
502 system.cpu.l2cache.tags.total_refs 8958694 # Total number of references to valid blocks.
503 system.cpu.l2cache.tags.sampled_refs 1956752 # Sample count of references to valid blocks.
504 system.cpu.l2cache.tags.avg_refs 4.578349 # Average number of references to valid blocks.
505 system.cpu.l2cache.tags.warmup_cycle 67887905750 # Cycle when the warmup percentage was hit.
506 system.cpu.l2cache.tags.occ_blocks::writebacks 14928.983043 # Average occupied blocks per requestor
507 system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.785512 # Average occupied blocks per requestor
508 system.cpu.l2cache.tags.occ_blocks::cpu.data 15951.847256 # Average occupied blocks per requestor
509 system.cpu.l2cache.tags.occ_percent::writebacks 0.455596 # Average percentage of cache occupancy
510 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001062 # Average percentage of cache occupancy
511 system.cpu.l2cache.tags.occ_percent::cpu.data 0.486812 # Average percentage of cache occupancy
512 system.cpu.l2cache.tags.occ_percent::total 0.943470 # Average percentage of cache occupancy
513 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id
514 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
515 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id
516 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id
517 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id
518 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id
519 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id
520 system.cpu.l2cache.tags.tag_accesses 106291175 # Number of tag accesses
521 system.cpu.l2cache.tags.data_accesses 106291175 # Number of data accesses
522 system.cpu.l2cache.ReadReq_hits::cpu.data 6044299 # number of ReadReq hits
523 system.cpu.l2cache.ReadReq_hits::total 6044299 # number of ReadReq hits
524 system.cpu.l2cache.Writeback_hits::writebacks 3693285 # number of Writeback hits
525 system.cpu.l2cache.Writeback_hits::total 3693285 # number of Writeback hits
526 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits
527 system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits
528 system.cpu.l2cache.demand_hits::cpu.data 7152626 # number of demand (read+write) hits
529 system.cpu.l2cache.demand_hits::total 7152626 # number of demand (read+write) hits
530 system.cpu.l2cache.overall_hits::cpu.data 7152626 # number of overall hits
531 system.cpu.l2cache.overall_hits::total 7152626 # number of overall hits
532 system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
533 system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses
534 system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses
535 system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses
536 system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses
537 system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
538 system.cpu.l2cache.demand_misses::cpu.data 1958830 # number of demand (read+write) misses
539 system.cpu.l2cache.demand_misses::total 1959689 # number of demand (read+write) misses
540 system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
541 system.cpu.l2cache.overall_misses::cpu.data 1958830 # number of overall misses
542 system.cpu.l2cache.overall_misses::total 1959689 # number of overall misses
543 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60968500 # number of ReadReq miss cycles
544 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94791357750 # number of ReadReq miss cycles
545 system.cpu.l2cache.ReadReq_miss_latency::total 94852326250 # number of ReadReq miss cycles
546 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65779017750 # number of ReadExReq miss cycles
547 system.cpu.l2cache.ReadExReq_miss_latency::total 65779017750 # number of ReadExReq miss cycles
548 system.cpu.l2cache.demand_miss_latency::cpu.inst 60968500 # number of demand (read+write) miss cycles
549 system.cpu.l2cache.demand_miss_latency::cpu.data 160570375500 # number of demand (read+write) miss cycles
550 system.cpu.l2cache.demand_miss_latency::total 160631344000 # number of demand (read+write) miss cycles
551 system.cpu.l2cache.overall_miss_latency::cpu.inst 60968500 # number of overall miss cycles
552 system.cpu.l2cache.overall_miss_latency::cpu.data 160570375500 # number of overall miss cycles
553 system.cpu.l2cache.overall_miss_latency::total 160631344000 # number of overall miss cycles
554 system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
555 system.cpu.l2cache.ReadReq_accesses::cpu.data 7221833 # number of ReadReq accesses(hits+misses)
556 system.cpu.l2cache.ReadReq_accesses::total 7222692 # number of ReadReq accesses(hits+misses)
557 system.cpu.l2cache.Writeback_accesses::writebacks 3693285 # number of Writeback accesses(hits+misses)
558 system.cpu.l2cache.Writeback_accesses::total 3693285 # number of Writeback accesses(hits+misses)
559 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889623 # number of ReadExReq accesses(hits+misses)
560 system.cpu.l2cache.ReadExReq_accesses::total 1889623 # number of ReadExReq accesses(hits+misses)
561 system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
562 system.cpu.l2cache.demand_accesses::cpu.data 9111456 # number of demand (read+write) accesses
563 system.cpu.l2cache.demand_accesses::total 9112315 # number of demand (read+write) accesses
564 system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
565 system.cpu.l2cache.overall_accesses::cpu.data 9111456 # number of overall (read+write) accesses
566 system.cpu.l2cache.overall_accesses::total 9112315 # number of overall (read+write) accesses
567 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
568 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
569 system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
570 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses
571 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses
572 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
573 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses
574 system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses
575 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
576 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
577 system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
578 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70976.135041 # average ReadReq miss latency
579 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80499.890237 # average ReadReq miss latency
580 system.cpu.l2cache.ReadReq_avg_miss_latency::total 80492.947811 # average ReadReq miss latency
581 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84192.185484 # average ReadExReq miss latency
582 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84192.185484 # average ReadExReq miss latency
583 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency
584 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency
585 system.cpu.l2cache.demand_avg_miss_latency::total 81967.773458 # average overall miss latency
586 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency
587 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency
588 system.cpu.l2cache.overall_avg_miss_latency::total 81967.773458 # average overall miss latency
589 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
590 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
591 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
592 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
593 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
594 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
595 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
596 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
597 system.cpu.l2cache.writebacks::writebacks 1018056 # number of writebacks
598 system.cpu.l2cache.writebacks::total 1018056 # number of writebacks
599 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
600 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses
601 system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses
602 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses
603 system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses
604 system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
605 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958830 # number of demand (read+write) MSHR misses
606 system.cpu.l2cache.demand_mshr_misses::total 1959689 # number of demand (read+write) MSHR misses
607 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
608 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958830 # number of overall MSHR misses
609 system.cpu.l2cache.overall_mshr_misses::total 1959689 # number of overall MSHR misses
610 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50186500 # number of ReadReq MSHR miss cycles
611 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80032548250 # number of ReadReq MSHR miss cycles
612 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80082734750 # number of ReadReq MSHR miss cycles
613 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56010972750 # number of ReadExReq MSHR miss cycles
614 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56010972750 # number of ReadExReq MSHR miss cycles
615 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50186500 # number of demand (read+write) MSHR miss cycles
616 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 136043521000 # number of demand (read+write) MSHR miss cycles
617 system.cpu.l2cache.demand_mshr_miss_latency::total 136093707500 # number of demand (read+write) MSHR miss cycles
618 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50186500 # number of overall MSHR miss cycles
619 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 136043521000 # number of overall MSHR miss cycles
620 system.cpu.l2cache.overall_mshr_miss_latency::total 136093707500 # number of overall MSHR miss cycles
621 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
622 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
623 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
624 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses
625 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses
626 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
627 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
628 system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses
629 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
630 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
631 system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
632 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58424.330617 # average ReadReq mshr miss latency
633 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67966.231336 # average ReadReq mshr miss latency
634 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67959.275683 # average ReadReq mshr miss latency
635 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71689.824023 # average ReadExReq mshr miss latency
636 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71689.824023 # average ReadExReq mshr miss latency
637 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency
638 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency
639 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency
640 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency
641 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency
642 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency
643 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
644 system.cpu.dcache.tags.replacements 9107360 # number of replacements
645 system.cpu.dcache.tags.tagsinuse 4082.305318 # Cycle average of tags in use
646 system.cpu.dcache.tags.total_refs 593299863 # Total number of references to valid blocks.
647 system.cpu.dcache.tags.sampled_refs 9111456 # Sample count of references to valid blocks.
648 system.cpu.dcache.tags.avg_refs 65.115813 # Average number of references to valid blocks.
649 system.cpu.dcache.tags.warmup_cycle 12706320250 # Cycle when the warmup percentage was hit.
650 system.cpu.dcache.tags.occ_blocks::cpu.data 4082.305318 # Average occupied blocks per requestor
651 system.cpu.dcache.tags.occ_percent::cpu.data 0.996657 # Average percentage of cache occupancy
652 system.cpu.dcache.tags.occ_percent::total 0.996657 # Average percentage of cache occupancy
653 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
654 system.cpu.dcache.tags.age_task_id_blocks_1024::0 574 # Occupied blocks per task id
655 system.cpu.dcache.tags.age_task_id_blocks_1024::1 2872 # Occupied blocks per task id
656 system.cpu.dcache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
657 system.cpu.dcache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id
658 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
659 system.cpu.dcache.tags.tag_accesses 1219759786 # Number of tag accesses
660 system.cpu.dcache.tags.data_accesses 1219759786 # Number of data accesses
661 system.cpu.dcache.ReadReq_hits::cpu.data 437268763 # number of ReadReq hits
662 system.cpu.dcache.ReadReq_hits::total 437268763 # number of ReadReq hits
663 system.cpu.dcache.WriteReq_hits::cpu.data 156031100 # number of WriteReq hits
664 system.cpu.dcache.WriteReq_hits::total 156031100 # number of WriteReq hits
665 system.cpu.dcache.demand_hits::cpu.data 593299863 # number of demand (read+write) hits
666 system.cpu.dcache.demand_hits::total 593299863 # number of demand (read+write) hits
667 system.cpu.dcache.overall_hits::cpu.data 593299863 # number of overall hits
668 system.cpu.dcache.overall_hits::total 593299863 # number of overall hits
669 system.cpu.dcache.ReadReq_misses::cpu.data 7326900 # number of ReadReq misses
670 system.cpu.dcache.ReadReq_misses::total 7326900 # number of ReadReq misses
671 system.cpu.dcache.WriteReq_misses::cpu.data 4697402 # number of WriteReq misses
672 system.cpu.dcache.WriteReq_misses::total 4697402 # number of WriteReq misses
673 system.cpu.dcache.demand_misses::cpu.data 12024302 # number of demand (read+write) misses
674 system.cpu.dcache.demand_misses::total 12024302 # number of demand (read+write) misses
675 system.cpu.dcache.overall_misses::cpu.data 12024302 # number of overall misses
676 system.cpu.dcache.overall_misses::total 12024302 # number of overall misses
677 system.cpu.dcache.ReadReq_miss_latency::cpu.data 179720219500 # number of ReadReq miss cycles
678 system.cpu.dcache.ReadReq_miss_latency::total 179720219500 # number of ReadReq miss cycles
679 system.cpu.dcache.WriteReq_miss_latency::cpu.data 246249534250 # number of WriteReq miss cycles
680 system.cpu.dcache.WriteReq_miss_latency::total 246249534250 # number of WriteReq miss cycles
681 system.cpu.dcache.demand_miss_latency::cpu.data 425969753750 # number of demand (read+write) miss cycles
682 system.cpu.dcache.demand_miss_latency::total 425969753750 # number of demand (read+write) miss cycles
683 system.cpu.dcache.overall_miss_latency::cpu.data 425969753750 # number of overall miss cycles
684 system.cpu.dcache.overall_miss_latency::total 425969753750 # number of overall miss cycles
685 system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
686 system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
687 system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
688 system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
689 system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
690 system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
691 system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
692 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
693 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
694 system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
695 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029226 # miss rate for WriteReq accesses
696 system.cpu.dcache.WriteReq_miss_rate::total 0.029226 # miss rate for WriteReq accesses
697 system.cpu.dcache.demand_miss_rate::cpu.data 0.019864 # miss rate for demand accesses
698 system.cpu.dcache.demand_miss_rate::total 0.019864 # miss rate for demand accesses
699 system.cpu.dcache.overall_miss_rate::cpu.data 0.019864 # miss rate for overall accesses
700 system.cpu.dcache.overall_miss_rate::total 0.019864 # miss rate for overall accesses
701 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24528.821125 # average ReadReq miss latency
702 system.cpu.dcache.ReadReq_avg_miss_latency::total 24528.821125 # average ReadReq miss latency
703 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52422.495296 # average WriteReq miss latency
704 system.cpu.dcache.WriteReq_avg_miss_latency::total 52422.495296 # average WriteReq miss latency
705 system.cpu.dcache.demand_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency
706 system.cpu.dcache.demand_avg_miss_latency::total 35425.736459 # average overall miss latency
707 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency
708 system.cpu.dcache.overall_avg_miss_latency::total 35425.736459 # average overall miss latency
709 system.cpu.dcache.blocked_cycles::no_mshrs 10235273 # number of cycles access was blocked
710 system.cpu.dcache.blocked_cycles::no_targets 7848261 # number of cycles access was blocked
711 system.cpu.dcache.blocked::no_mshrs 412771 # number of cycles access was blocked
712 system.cpu.dcache.blocked::no_targets 73432 # number of cycles access was blocked
713 system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.796492 # average number of cycles each access was blocked
714 system.cpu.dcache.avg_blocked_cycles::no_targets 106.877941 # average number of cycles each access was blocked
715 system.cpu.dcache.fast_writes 0 # number of fast writes performed
716 system.cpu.dcache.cache_copies 0 # number of cache copies performed
717 system.cpu.dcache.writebacks::writebacks 3693285 # number of writebacks
718 system.cpu.dcache.writebacks::total 3693285 # number of writebacks
719 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits
720 system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits
721 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2808220 # number of WriteReq MSHR hits
722 system.cpu.dcache.WriteReq_mshr_hits::total 2808220 # number of WriteReq MSHR hits
723 system.cpu.dcache.demand_mshr_hits::cpu.data 2912846 # number of demand (read+write) MSHR hits
724 system.cpu.dcache.demand_mshr_hits::total 2912846 # number of demand (read+write) MSHR hits
725 system.cpu.dcache.overall_mshr_hits::cpu.data 2912846 # number of overall MSHR hits
726 system.cpu.dcache.overall_mshr_hits::total 2912846 # number of overall MSHR hits
727 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222274 # number of ReadReq MSHR misses
728 system.cpu.dcache.ReadReq_mshr_misses::total 7222274 # number of ReadReq MSHR misses
729 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
730 system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
731 system.cpu.dcache.demand_mshr_misses::cpu.data 9111456 # number of demand (read+write) MSHR misses
732 system.cpu.dcache.demand_mshr_misses::total 9111456 # number of demand (read+write) MSHR misses
733 system.cpu.dcache.overall_mshr_misses::cpu.data 9111456 # number of overall MSHR misses
734 system.cpu.dcache.overall_mshr_misses::total 9111456 # number of overall MSHR misses
735 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162584714500 # number of ReadReq MSHR miss cycles
736 system.cpu.dcache.ReadReq_mshr_miss_latency::total 162584714500 # number of ReadReq MSHR miss cycles
737 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78915202250 # number of WriteReq MSHR miss cycles
738 system.cpu.dcache.WriteReq_mshr_miss_latency::total 78915202250 # number of WriteReq MSHR miss cycles
739 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 241499916750 # number of demand (read+write) MSHR miss cycles
740 system.cpu.dcache.demand_mshr_miss_latency::total 241499916750 # number of demand (read+write) MSHR miss cycles
741 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 241499916750 # number of overall MSHR miss cycles
742 system.cpu.dcache.overall_mshr_miss_latency::total 241499916750 # number of overall MSHR miss cycles
743 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
744 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
745 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
746 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
747 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
748 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
749 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
750 system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
751 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22511.568309 # average ReadReq mshr miss latency
752 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22511.568309 # average ReadReq mshr miss latency
753 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41772.154430 # average WriteReq mshr miss latency
754 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41772.154430 # average WriteReq mshr miss latency
755 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency
756 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency
757 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency
758 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency
759 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
761 ---------- End Simulation Statistics ----------
projects / gem5.git / blob