2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.007337 # Number of seconds simulated
4 sim_ticks 1007336591500 # Number of ticks simulated
5 final_tick 1007336591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 109896 # Simulator instruction rate (inst/s)
8 host_op_rate 109896 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 60832901 # Simulator tick rate (ticks/s)
10 host_mem_usage 265436 # Number of bytes of host memory used
11 host_seconds 16559.08 # Real time elapsed on the host
12 sim_insts 1819780127 # Number of instructions simulated
13 sim_ops 1819780127 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 54576 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 124452002 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 124506578 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 54576 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 54576 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 64680982 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 64680982 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 64680982 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 54576 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 124452002 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 189187560 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 1959688 # Number of read requests accepted
40 system.physmem.writeReqs 1018055 # Number of write requests accepted
41 system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 125336064 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 83968 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 65153920 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 1312 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 118685 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 114026 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 116162 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 117671 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 117731 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 117464 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 119807 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 124441 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 126920 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 130015 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 128574 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 130216 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 125899 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 125145 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 122505 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 123115 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 61223 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 61467 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 60558 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 61215 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 61647 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 63083 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 64136 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 65614 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 65332 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 65769 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 65294 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 65608 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 64146 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 64202 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 64550 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 64186 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 1007336518500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 1959688 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 1018055 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 1664981 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 198590 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 70959 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 23846 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 26939 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 28117 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 34916 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 48946 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 53936 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 56821 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 58079 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 58536 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 58949 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 59504 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 64559 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 64811 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 64584 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 72712 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 62778 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 60810 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 59834 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 59240 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 14814 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 4880 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 1773 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 67 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 1266500 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 109.102187 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 83.148932 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 142.836675 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 979529 77.34% 77.34% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 199046 15.72% 93.06% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 36524 2.88% 95.94% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 14982 1.18% 97.12% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 8864 0.70% 97.82% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 4419 0.35% 98.17% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 2809 0.22% 98.40% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2238 0.18% 98.57% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 18089 1.43% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 1266500 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 58142 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 33.680816 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 161.230571 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 58099 99.93% 99.93% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::total 58142 # Reads before turning the bus around for writes
226 system.physmem.wrPerTurnAround::samples 58142 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::mean 17.509374 # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::gmean 17.424358 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::stdev 1.849185 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::16 29010 49.90% 49.90% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::17 1046 1.80% 51.69% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::18 6657 11.45% 63.14% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::19 16493 28.37% 91.51% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::20 3312 5.70% 97.21% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::21 1061 1.82% 99.03% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::22 264 0.45% 99.49% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::23 97 0.17% 99.65% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::24 56 0.10% 99.75% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::25 17 0.03% 99.78% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::26 18 0.03% 99.81% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::27 13 0.02% 99.83% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::28 5 0.01% 99.84% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::29 6 0.01% 99.85% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::30 4 0.01% 99.86% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::31 5 0.01% 99.87% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::32 5 0.01% 99.87% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::33 3 0.01% 99.88% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::34 3 0.01% 99.88% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::35 2 0.00% 99.89% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::36 2 0.00% 99.89% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::38 1 0.00% 99.89% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::39 28 0.05% 99.94% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::40 9 0.02% 99.96% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::41 6 0.01% 99.97% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::42 2 0.00% 99.97% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::43 5 0.01% 99.98% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::46 1 0.00% 99.98% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::47 1 0.00% 99.98% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::48 2 0.00% 99.99% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::49 2 0.00% 99.99% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::50 1 0.00% 99.99% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::53 1 0.00% 99.99% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::54 1 0.00% 99.99% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::55 1 0.00% 100.00% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::59 1 0.00% 100.00% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::62 1 0.00% 100.00% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::total 58142 # Writes before turning the bus around for reads
268 system.physmem.totQLat 19659284500 # Total ticks spent queuing
269 system.physmem.totMemAccLat 80383790750 # Total ticks spent from burst creation until serviced by the DRAM
270 system.physmem.totBusLat 9791880000 # Total ticks spent in databus transfers
271 system.physmem.totBankLat 50932626250 # Total ticks spent accessing banks
272 system.physmem.avgQLat 10038.56 # Average queueing delay per DRAM burst
273 system.physmem.avgBankLat 26007.58 # Average bank access latency per DRAM burst
274 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
275 system.physmem.avgMemAccLat 41046.15 # Average memory access latency per DRAM burst
276 system.physmem.avgRdBW 124.42 # Average DRAM read bandwidth in MiByte/s
277 system.physmem.avgWrBW 64.68 # Average achieved write bandwidth in MiByte/s
278 system.physmem.avgRdBWSys 124.51 # Average system read bandwidth in MiByte/s
279 system.physmem.avgWrBWSys 64.68 # Average system write bandwidth in MiByte/s
280 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
281 system.physmem.busUtil 1.48 # Data bus utilization in percentage
282 system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads
283 system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes
284 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
285 system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
286 system.physmem.readRowHits 753336 # Number of row buffer hits during reads
287 system.physmem.writeRowHits 422191 # Number of row buffer hits during writes
288 system.physmem.readRowHitRate 38.47 # Row buffer hit rate for reads
289 system.physmem.writeRowHitRate 41.47 # Row buffer hit rate for writes
290 system.physmem.avgGap 338288.60 # Average gap between requests
291 system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined
292 system.physmem.prechargeAllPercent 12.29 # Percentage of time for which DRAM has all the banks in precharge state
293 system.membus.throughput 189187560 # Throughput (bytes/s)
294 system.membus.trans_dist::ReadReq 1178393 # Transaction distribution
295 system.membus.trans_dist::ReadResp 1178393 # Transaction distribution
296 system.membus.trans_dist::Writeback 1018055 # Transaction distribution
297 system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
298 system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
299 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes)
300 system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes)
301 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes)
302 system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes)
303 system.membus.data_through_bus 190575552 # Total data (bytes)
304 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
305 system.membus.reqLayer0.occupancy 11782666500 # Layer occupancy (ticks)
306 system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
307 system.membus.respLayer1.occupancy 18347417750 # Layer occupancy (ticks)
308 system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
309 system.cpu_clk_domain.clock 500 # Clock period in ticks
310 system.cpu.branchPred.lookups 326511183 # Number of BP lookups
311 system.cpu.branchPred.condPredicted 252559725 # Number of conditional branches predicted
312 system.cpu.branchPred.condIncorrect 138218265 # Number of conditional branches incorrect
313 system.cpu.branchPred.BTBLookups 220270477 # Number of BTB lookups
314 system.cpu.branchPred.BTBHits 135614039 # Number of BTB hits
315 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
316 system.cpu.branchPred.BTBHitPct 61.567052 # BTB Hit Percentage
317 system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
318 system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
319 system.cpu.dtb.fetch_hits 0 # ITB hits
320 system.cpu.dtb.fetch_misses 0 # ITB misses
321 system.cpu.dtb.fetch_acv 0 # ITB acv
322 system.cpu.dtb.fetch_accesses 0 # ITB accesses
323 system.cpu.dtb.read_hits 444830139 # DTB read hits
324 system.cpu.dtb.read_misses 4897078 # DTB read misses
325 system.cpu.dtb.read_acv 0 # DTB read access violations
326 system.cpu.dtb.read_accesses 449727217 # DTB read accesses
327 system.cpu.dtb.write_hits 160844128 # DTB write hits
328 system.cpu.dtb.write_misses 1701304 # DTB write misses
329 system.cpu.dtb.write_acv 0 # DTB write access violations
330 system.cpu.dtb.write_accesses 162545432 # DTB write accesses
331 system.cpu.dtb.data_hits 605674267 # DTB hits
332 system.cpu.dtb.data_misses 6598382 # DTB misses
333 system.cpu.dtb.data_acv 0 # DTB access violations
334 system.cpu.dtb.data_accesses 612272649 # DTB accesses
335 system.cpu.itb.fetch_hits 232118114 # ITB hits
336 system.cpu.itb.fetch_misses 22 # ITB misses
337 system.cpu.itb.fetch_acv 0 # ITB acv
338 system.cpu.itb.fetch_accesses 232118136 # ITB accesses
339 system.cpu.itb.read_hits 0 # DTB read hits
340 system.cpu.itb.read_misses 0 # DTB read misses
341 system.cpu.itb.read_acv 0 # DTB read access violations
342 system.cpu.itb.read_accesses 0 # DTB read accesses
343 system.cpu.itb.write_hits 0 # DTB write hits
344 system.cpu.itb.write_misses 0 # DTB write misses
345 system.cpu.itb.write_acv 0 # DTB write access violations
346 system.cpu.itb.write_accesses 0 # DTB write accesses
347 system.cpu.itb.data_hits 0 # DTB hits
348 system.cpu.itb.data_misses 0 # DTB misses
349 system.cpu.itb.data_acv 0 # DTB access violations
350 system.cpu.itb.data_accesses 0 # DTB accesses
351 system.cpu.workload.num_syscalls 29 # Number of system calls
352 system.cpu.numCycles 2014673184 # number of cpu cycles simulated
353 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
354 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
355 system.cpu.branch_predictor.predictedTaken 172428181 # Number of Branches Predicted As Taken (True).
356 system.cpu.branch_predictor.predictedNotTaken 154083002 # Number of Branches Predicted As Not Taken (False).
357 system.cpu.regfile_manager.intRegFileReads 1667622783 # Number of Reads from Int. Register File
358 system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
359 system.cpu.regfile_manager.intRegFileAccesses 3043825400 # Total Accesses (Read+Write) to the Int. Register File
360 system.cpu.regfile_manager.floatRegFileReads 231 # Number of Reads from FP Register File
361 system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
362 system.cpu.regfile_manager.floatRegFileAccesses 576 # Total Accesses (Read+Write) to the FP Register File
363 system.cpu.regfile_manager.regForwards 651695392 # Number of Registers Read Through Forwarding Logic
364 system.cpu.agen_unit.agens 617886274 # Number of Address Generations
365 system.cpu.execution_unit.predictedTakenIncorrect 120493688 # Number of Branches Incorrectly Predicted As Taken.
366 system.cpu.execution_unit.predictedNotTakenIncorrect 11126119 # Number of Branches Incorrectly Predicted As Not Taken).
367 system.cpu.execution_unit.mispredicted 131619807 # Number of Branches Incorrectly Predicted
368 system.cpu.execution_unit.predicted 83580161 # Number of Branches Incorrectly Predicted
369 system.cpu.execution_unit.mispredictPct 61.161629 # Percentage of Incorrect Branches Predicts
370 system.cpu.execution_unit.executions 1139354623 # Number of Instructions Executed.
371 system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
372 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
373 system.cpu.contextSwitches 1 # Number of context switches
374 system.cpu.threadCycles 1742144730 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
375 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
376 system.cpu.timesIdled 7512368 # Number of times that the entire CPU went into an idle state and unscheduled itself
377 system.cpu.idleCycles 442846963 # Number of cycles cpu's stages were not processed
378 system.cpu.runCycles 1571826221 # Number of cycles cpu stages are processed.
379 system.cpu.activity 78.018918 # Percentage of cycles cpu is active
380 system.cpu.comLoads 444595663 # Number of Load instructions committed
381 system.cpu.comStores 160728502 # Number of Store instructions committed
382 system.cpu.comBranches 214632552 # Number of Branches instructions committed
383 system.cpu.comNops 83736345 # Number of Nop instructions committed
384 system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
385 system.cpu.comInts 916086844 # Number of Integer instructions committed
386 system.cpu.comFloats 190 # Number of Floating Point instructions committed
387 system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
388 system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
389 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
390 system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
391 system.cpu.cpi 1.107097 # CPI: Cycles Per Instruction (Per-Thread)
392 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
393 system.cpu.cpi_total 1.107097 # CPI: Total CPI of All Threads
394 system.cpu.ipc 0.903263 # IPC: Instructions Per Cycle (Per-Thread)
395 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
396 system.cpu.ipc_total 0.903263 # IPC: Total IPC of All Threads
397 system.cpu.stage0.idleCycles 827756857 # Number of cycles 0 instructions are processed.
398 system.cpu.stage0.runCycles 1186916327 # Number of cycles 1+ instructions are processed.
399 system.cpu.stage0.utilization 58.913591 # Percentage of cycles stage was utilized (processing insts).
400 system.cpu.stage1.idleCycles 1081059316 # Number of cycles 0 instructions are processed.
401 system.cpu.stage1.runCycles 933613868 # Number of cycles 1+ instructions are processed.
402 system.cpu.stage1.utilization 46.340711 # Percentage of cycles stage was utilized (processing insts).
403 system.cpu.stage2.idleCycles 1042290381 # Number of cycles 0 instructions are processed.
404 system.cpu.stage2.runCycles 972382803 # Number of cycles 1+ instructions are processed.
405 system.cpu.stage2.utilization 48.265039 # Percentage of cycles stage was utilized (processing insts).
406 system.cpu.stage3.idleCycles 1605047974 # Number of cycles 0 instructions are processed.
407 system.cpu.stage3.runCycles 409625210 # Number of cycles 1+ instructions are processed.
408 system.cpu.stage3.utilization 20.332092 # Percentage of cycles stage was utilized (processing insts).
409 system.cpu.stage4.idleCycles 993337465 # Number of cycles 0 instructions are processed.
410 system.cpu.stage4.runCycles 1021335719 # Number of cycles 1+ instructions are processed.
411 system.cpu.stage4.utilization 50.694858 # Percentage of cycles stage was utilized (processing insts).
412 system.cpu.icache.tags.replacements 1 # number of replacements
413 system.cpu.icache.tags.tagsinuse 668.288600 # Cycle average of tags in use
414 system.cpu.icache.tags.total_refs 232116975 # Total number of references to valid blocks.
415 system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
416 system.cpu.icache.tags.avg_refs 270217.665891 # Average number of references to valid blocks.
417 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
418 system.cpu.icache.tags.occ_blocks::cpu.inst 668.288600 # Average occupied blocks per requestor
419 system.cpu.icache.tags.occ_percent::cpu.inst 0.326313 # Average percentage of cache occupancy
420 system.cpu.icache.tags.occ_percent::total 0.326313 # Average percentage of cache occupancy
421 system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id
422 system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
423 system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id
424 system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id
425 system.cpu.icache.tags.tag_accesses 464237087 # Number of tag accesses
426 system.cpu.icache.tags.data_accesses 464237087 # Number of data accesses
427 system.cpu.icache.ReadReq_hits::cpu.inst 232116975 # number of ReadReq hits
428 system.cpu.icache.ReadReq_hits::total 232116975 # number of ReadReq hits
429 system.cpu.icache.demand_hits::cpu.inst 232116975 # number of demand (read+write) hits
430 system.cpu.icache.demand_hits::total 232116975 # number of demand (read+write) hits
431 system.cpu.icache.overall_hits::cpu.inst 232116975 # number of overall hits
432 system.cpu.icache.overall_hits::total 232116975 # number of overall hits
433 system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses
434 system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses
435 system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses
436 system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses
437 system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses
438 system.cpu.icache.overall_misses::total 1139 # number of overall misses
439 system.cpu.icache.ReadReq_miss_latency::cpu.inst 81449500 # number of ReadReq miss cycles
440 system.cpu.icache.ReadReq_miss_latency::total 81449500 # number of ReadReq miss cycles
441 system.cpu.icache.demand_miss_latency::cpu.inst 81449500 # number of demand (read+write) miss cycles
442 system.cpu.icache.demand_miss_latency::total 81449500 # number of demand (read+write) miss cycles
443 system.cpu.icache.overall_miss_latency::cpu.inst 81449500 # number of overall miss cycles
444 system.cpu.icache.overall_miss_latency::total 81449500 # number of overall miss cycles
445 system.cpu.icache.ReadReq_accesses::cpu.inst 232118114 # number of ReadReq accesses(hits+misses)
446 system.cpu.icache.ReadReq_accesses::total 232118114 # number of ReadReq accesses(hits+misses)
447 system.cpu.icache.demand_accesses::cpu.inst 232118114 # number of demand (read+write) accesses
448 system.cpu.icache.demand_accesses::total 232118114 # number of demand (read+write) accesses
449 system.cpu.icache.overall_accesses::cpu.inst 232118114 # number of overall (read+write) accesses
450 system.cpu.icache.overall_accesses::total 232118114 # number of overall (read+write) accesses
451 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
452 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
453 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
454 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
455 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
456 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
457 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594 # average ReadReq miss latency
458 system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594 # average ReadReq miss latency
459 system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency
460 system.cpu.icache.demand_avg_miss_latency::total 71509.657594 # average overall miss latency
461 system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency
462 system.cpu.icache.overall_avg_miss_latency::total 71509.657594 # average overall miss latency
463 system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked
464 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
465 system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
466 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
467 system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked
468 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
469 system.cpu.icache.fast_writes 0 # number of fast writes performed
470 system.cpu.icache.cache_copies 0 # number of cache copies performed
471 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits
472 system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
473 system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits
474 system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits
475 system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits
476 system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits
477 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
478 system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
479 system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
480 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
481 system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
482 system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
483 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 63326500 # number of ReadReq MSHR miss cycles
484 system.cpu.icache.ReadReq_mshr_miss_latency::total 63326500 # number of ReadReq MSHR miss cycles
485 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 63326500 # number of demand (read+write) MSHR miss cycles
486 system.cpu.icache.demand_mshr_miss_latency::total 63326500 # number of demand (read+write) MSHR miss cycles
487 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 63326500 # number of overall MSHR miss cycles
488 system.cpu.icache.overall_mshr_miss_latency::total 63326500 # number of overall MSHR miss cycles
489 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
490 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
491 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
492 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
493 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
494 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
495 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427 # average ReadReq mshr miss latency
496 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427 # average ReadReq mshr miss latency
497 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency
498 system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency
499 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency
500 system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency
501 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
502 system.cpu.toL2Bus.throughput 813589109 # Throughput (bytes/s)
503 system.cpu.toL2Bus.trans_dist::ReadReq 7222688 # Transaction distribution
504 system.cpu.toL2Bus.trans_dist::ReadResp 7222688 # Transaction distribution
505 system.cpu.toL2Bus.trans_dist::Writeback 3693283 # Transaction distribution
506 system.cpu.toL2Bus.trans_dist::ReadExReq 1889624 # Transaction distribution
507 system.cpu.toL2Bus.trans_dist::ReadExResp 1889624 # Transaction distribution
508 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
509 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916189 # Packet count per connected master and slave (bytes)
510 system.cpu.toL2Bus.pkt_count::total 21917907 # Packet count per connected master and slave (bytes)
511 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
512 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503104 # Cumulative packet size per connected master and slave (bytes)
513 system.cpu.toL2Bus.tot_pkt_size::total 819558080 # Cumulative packet size per connected master and slave (bytes)
514 system.cpu.toL2Bus.data_through_bus 819558080 # Total data (bytes)
515 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
516 system.cpu.toL2Bus.reqLayer0.occupancy 10096080500 # Layer occupancy (ticks)
517 system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
518 system.cpu.toL2Bus.respLayer0.occupancy 1443000 # Layer occupancy (ticks)
519 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
520 system.cpu.toL2Bus.respLayer1.occupancy 13971303500 # Layer occupancy (ticks)
521 system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
522 system.cpu.l2cache.tags.replacements 1926957 # number of replacements
523 system.cpu.l2cache.tags.tagsinuse 30916.680897 # Cycle average of tags in use
524 system.cpu.l2cache.tags.total_refs 8958690 # Total number of references to valid blocks.
525 system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks.
526 system.cpu.l2cache.tags.avg_refs 4.578352 # Average number of references to valid blocks.
527 system.cpu.l2cache.tags.warmup_cycle 67897094750 # Cycle when the warmup percentage was hit.
528 system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701 # Average occupied blocks per requestor
529 system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.739406 # Average occupied blocks per requestor
530 system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790 # Average occupied blocks per requestor
531 system.cpu.l2cache.tags.occ_percent::writebacks 0.455536 # Average percentage of cache occupancy
532 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001060 # Average percentage of cache occupancy
533 system.cpu.l2cache.tags.occ_percent::cpu.data 0.486906 # Average percentage of cache occupancy
534 system.cpu.l2cache.tags.occ_percent::total 0.943502 # Average percentage of cache occupancy
535 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id
536 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
537 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 586 # Occupied blocks per task id
538 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id
539 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id
540 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id
541 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id
542 system.cpu.l2cache.tags.tag_accesses 106291134 # Number of tag accesses
543 system.cpu.l2cache.tags.data_accesses 106291134 # Number of data accesses
544 system.cpu.l2cache.ReadReq_hits::cpu.data 6044295 # number of ReadReq hits
545 system.cpu.l2cache.ReadReq_hits::total 6044295 # number of ReadReq hits
546 system.cpu.l2cache.Writeback_hits::writebacks 3693283 # number of Writeback hits
547 system.cpu.l2cache.Writeback_hits::total 3693283 # number of Writeback hits
548 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108329 # number of ReadExReq hits
549 system.cpu.l2cache.ReadExReq_hits::total 1108329 # number of ReadExReq hits
550 system.cpu.l2cache.demand_hits::cpu.data 7152624 # number of demand (read+write) hits
551 system.cpu.l2cache.demand_hits::total 7152624 # number of demand (read+write) hits
552 system.cpu.l2cache.overall_hits::cpu.data 7152624 # number of overall hits
553 system.cpu.l2cache.overall_hits::total 7152624 # number of overall hits
554 system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
555 system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses
556 system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses
557 system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses
558 system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses
559 system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
560 system.cpu.l2cache.demand_misses::cpu.data 1958829 # number of demand (read+write) misses
561 system.cpu.l2cache.demand_misses::total 1959688 # number of demand (read+write) misses
562 system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
563 system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses
564 system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses
565 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 62463500 # number of ReadReq miss cycles
566 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95853275750 # number of ReadReq miss cycles
567 system.cpu.l2cache.ReadReq_miss_latency::total 95915739250 # number of ReadReq miss cycles
568 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68840007000 # number of ReadExReq miss cycles
569 system.cpu.l2cache.ReadExReq_miss_latency::total 68840007000 # number of ReadExReq miss cycles
570 system.cpu.l2cache.demand_miss_latency::cpu.inst 62463500 # number of demand (read+write) miss cycles
571 system.cpu.l2cache.demand_miss_latency::cpu.data 164693282750 # number of demand (read+write) miss cycles
572 system.cpu.l2cache.demand_miss_latency::total 164755746250 # number of demand (read+write) miss cycles
573 system.cpu.l2cache.overall_miss_latency::cpu.inst 62463500 # number of overall miss cycles
574 system.cpu.l2cache.overall_miss_latency::cpu.data 164693282750 # number of overall miss cycles
575 system.cpu.l2cache.overall_miss_latency::total 164755746250 # number of overall miss cycles
576 system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
577 system.cpu.l2cache.ReadReq_accesses::cpu.data 7221829 # number of ReadReq accesses(hits+misses)
578 system.cpu.l2cache.ReadReq_accesses::total 7222688 # number of ReadReq accesses(hits+misses)
579 system.cpu.l2cache.Writeback_accesses::writebacks 3693283 # number of Writeback accesses(hits+misses)
580 system.cpu.l2cache.Writeback_accesses::total 3693283 # number of Writeback accesses(hits+misses)
581 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889624 # number of ReadExReq accesses(hits+misses)
582 system.cpu.l2cache.ReadExReq_accesses::total 1889624 # number of ReadExReq accesses(hits+misses)
583 system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
584 system.cpu.l2cache.demand_accesses::cpu.data 9111453 # number of demand (read+write) accesses
585 system.cpu.l2cache.demand_accesses::total 9112312 # number of demand (read+write) accesses
586 system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
587 system.cpu.l2cache.overall_accesses::cpu.data 9111453 # number of overall (read+write) accesses
588 system.cpu.l2cache.overall_accesses::total 9112312 # number of overall (read+write) accesses
589 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
590 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
591 system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses
592 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413466 # miss rate for ReadExReq accesses
593 system.cpu.l2cache.ReadExReq_miss_rate::total 0.413466 # miss rate for ReadExReq accesses
594 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
595 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses
596 system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses
597 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
598 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
599 system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
600 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72716.530850 # average ReadReq miss latency
601 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81401.705386 # average ReadReq miss latency
602 system.cpu.l2cache.ReadReq_avg_miss_latency::total 81395.374251 # average ReadReq miss latency
603 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88110.133816 # average ReadExReq miss latency
604 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88110.133816 # average ReadExReq miss latency
605 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency
606 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency
607 system.cpu.l2cache.demand_avg_miss_latency::total 84072.437169 # average overall miss latency
608 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency
609 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency
610 system.cpu.l2cache.overall_avg_miss_latency::total 84072.437169 # average overall miss latency
611 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
612 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
613 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
614 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
615 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
616 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
617 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
618 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
619 system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks
620 system.cpu.l2cache.writebacks::total 1018055 # number of writebacks
621 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
622 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses
623 system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses
624 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses
625 system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses
626 system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
627 system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses
628 system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses
629 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
630 system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
631 system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses
632 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51686000 # number of ReadReq MSHR miss cycles
633 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81095366750 # number of ReadReq MSHR miss cycles
634 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 81147052750 # number of ReadReq MSHR miss cycles
635 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59075528500 # number of ReadExReq MSHR miss cycles
636 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59075528500 # number of ReadExReq MSHR miss cycles
637 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51686000 # number of demand (read+write) MSHR miss cycles
638 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140170895250 # number of demand (read+write) MSHR miss cycles
639 system.cpu.l2cache.demand_mshr_miss_latency::total 140222581250 # number of demand (read+write) MSHR miss cycles
640 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51686000 # number of overall MSHR miss cycles
641 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140170895250 # number of overall MSHR miss cycles
642 system.cpu.l2cache.overall_mshr_miss_latency::total 140222581250 # number of overall MSHR miss cycles
643 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
644 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
645 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses
646 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413466 # mshr miss rate for ReadExReq accesses
647 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413466 # mshr miss rate for ReadExReq accesses
648 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
649 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
650 system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses
651 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
652 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
653 system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
654 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076 # average ReadReq mshr miss latency
655 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219 # average ReadReq mshr miss latency
656 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118 # average ReadReq mshr miss latency
657 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210 # average ReadExReq mshr miss latency
658 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210 # average ReadExReq mshr miss latency
659 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency
660 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency
661 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency
662 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency
663 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency
664 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency
665 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
666 system.cpu.dcache.tags.replacements 9107357 # number of replacements
667 system.cpu.dcache.tags.tagsinuse 4082.325879 # Cycle average of tags in use
668 system.cpu.dcache.tags.total_refs 593298406 # Total number of references to valid blocks.
669 system.cpu.dcache.tags.sampled_refs 9111453 # Sample count of references to valid blocks.
670 system.cpu.dcache.tags.avg_refs 65.115674 # Average number of references to valid blocks.
671 system.cpu.dcache.tags.warmup_cycle 12706876000 # Cycle when the warmup percentage was hit.
672 system.cpu.dcache.tags.occ_blocks::cpu.data 4082.325879 # Average occupied blocks per requestor
673 system.cpu.dcache.tags.occ_percent::cpu.data 0.996662 # Average percentage of cache occupancy
674 system.cpu.dcache.tags.occ_percent::total 0.996662 # Average percentage of cache occupancy
675 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
676 system.cpu.dcache.tags.age_task_id_blocks_1024::0 560 # Occupied blocks per task id
677 system.cpu.dcache.tags.age_task_id_blocks_1024::1 2879 # Occupied blocks per task id
678 system.cpu.dcache.tags.age_task_id_blocks_1024::2 619 # Occupied blocks per task id
679 system.cpu.dcache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id
680 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
681 system.cpu.dcache.tags.tag_accesses 1219759783 # Number of tag accesses
682 system.cpu.dcache.tags.data_accesses 1219759783 # Number of data accesses
683 system.cpu.dcache.ReadReq_hits::cpu.data 437268768 # number of ReadReq hits
684 system.cpu.dcache.ReadReq_hits::total 437268768 # number of ReadReq hits
685 system.cpu.dcache.WriteReq_hits::cpu.data 156029638 # number of WriteReq hits
686 system.cpu.dcache.WriteReq_hits::total 156029638 # number of WriteReq hits
687 system.cpu.dcache.demand_hits::cpu.data 593298406 # number of demand (read+write) hits
688 system.cpu.dcache.demand_hits::total 593298406 # number of demand (read+write) hits
689 system.cpu.dcache.overall_hits::cpu.data 593298406 # number of overall hits
690 system.cpu.dcache.overall_hits::total 593298406 # number of overall hits
691 system.cpu.dcache.ReadReq_misses::cpu.data 7326895 # number of ReadReq misses
692 system.cpu.dcache.ReadReq_misses::total 7326895 # number of ReadReq misses
693 system.cpu.dcache.WriteReq_misses::cpu.data 4698864 # number of WriteReq misses
694 system.cpu.dcache.WriteReq_misses::total 4698864 # number of WriteReq misses
695 system.cpu.dcache.demand_misses::cpu.data 12025759 # number of demand (read+write) misses
696 system.cpu.dcache.demand_misses::total 12025759 # number of demand (read+write) misses
697 system.cpu.dcache.overall_misses::cpu.data 12025759 # number of overall misses
698 system.cpu.dcache.overall_misses::total 12025759 # number of overall misses
699 system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750 # number of ReadReq miss cycles
700 system.cpu.dcache.ReadReq_miss_latency::total 180765205750 # number of ReadReq miss cycles
701 system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250 # number of WriteReq miss cycles
702 system.cpu.dcache.WriteReq_miss_latency::total 250221551250 # number of WriteReq miss cycles
703 system.cpu.dcache.demand_miss_latency::cpu.data 430986757000 # number of demand (read+write) miss cycles
704 system.cpu.dcache.demand_miss_latency::total 430986757000 # number of demand (read+write) miss cycles
705 system.cpu.dcache.overall_miss_latency::cpu.data 430986757000 # number of overall miss cycles
706 system.cpu.dcache.overall_miss_latency::total 430986757000 # number of overall miss cycles
707 system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
708 system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
709 system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
710 system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
711 system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
712 system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
713 system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
714 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
715 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
716 system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
717 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029235 # miss rate for WriteReq accesses
718 system.cpu.dcache.WriteReq_miss_rate::total 0.029235 # miss rate for WriteReq accesses
719 system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses
720 system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses
721 system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses
722 system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses
723 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206 # average ReadReq miss latency
724 system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206 # average ReadReq miss latency
725 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926 # average WriteReq miss latency
726 system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926 # average WriteReq miss latency
727 system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency
728 system.cpu.dcache.demand_avg_miss_latency::total 35838.632472 # average overall miss latency
729 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency
730 system.cpu.dcache.overall_avg_miss_latency::total 35838.632472 # average overall miss latency
731 system.cpu.dcache.blocked_cycles::no_mshrs 11447989 # number of cycles access was blocked
732 system.cpu.dcache.blocked_cycles::no_targets 7764770 # number of cycles access was blocked
733 system.cpu.dcache.blocked::no_mshrs 416735 # number of cycles access was blocked
734 system.cpu.dcache.blocked::no_targets 73422 # number of cycles access was blocked
735 system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.470668 # average number of cycles each access was blocked
736 system.cpu.dcache.avg_blocked_cycles::no_targets 105.755359 # average number of cycles each access was blocked
737 system.cpu.dcache.fast_writes 0 # number of fast writes performed
738 system.cpu.dcache.cache_copies 0 # number of cache copies performed
739 system.cpu.dcache.writebacks::writebacks 3693283 # number of writebacks
740 system.cpu.dcache.writebacks::total 3693283 # number of writebacks
741 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits
742 system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits
743 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809682 # number of WriteReq MSHR hits
744 system.cpu.dcache.WriteReq_mshr_hits::total 2809682 # number of WriteReq MSHR hits
745 system.cpu.dcache.demand_mshr_hits::cpu.data 2914306 # number of demand (read+write) MSHR hits
746 system.cpu.dcache.demand_mshr_hits::total 2914306 # number of demand (read+write) MSHR hits
747 system.cpu.dcache.overall_mshr_hits::cpu.data 2914306 # number of overall MSHR hits
748 system.cpu.dcache.overall_mshr_hits::total 2914306 # number of overall MSHR hits
749 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222271 # number of ReadReq MSHR misses
750 system.cpu.dcache.ReadReq_mshr_misses::total 7222271 # number of ReadReq MSHR misses
751 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
752 system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
753 system.cpu.dcache.demand_mshr_misses::cpu.data 9111453 # number of demand (read+write) MSHR misses
754 system.cpu.dcache.demand_mshr_misses::total 9111453 # number of demand (read+write) MSHR misses
755 system.cpu.dcache.overall_mshr_misses::cpu.data 9111453 # number of overall MSHR misses
756 system.cpu.dcache.overall_mshr_misses::total 9111453 # number of overall MSHR misses
757 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750 # number of ReadReq MSHR miss cycles
758 system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750 # number of ReadReq MSHR miss cycles
759 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81975016250 # number of WriteReq MSHR miss cycles
760 system.cpu.dcache.WriteReq_mshr_miss_latency::total 81975016250 # number of WriteReq MSHR miss cycles
761 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000 # number of demand (read+write) MSHR miss cycles
762 system.cpu.dcache.demand_mshr_miss_latency::total 245622028000 # number of demand (read+write) MSHR miss cycles
763 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000 # number of overall MSHR miss cycles
764 system.cpu.dcache.overall_mshr_miss_latency::total 245622028000 # number of overall MSHR miss cycles
765 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
766 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
767 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
768 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
769 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
770 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
771 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
772 system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
773 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978 # average ReadReq mshr miss latency
774 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978 # average ReadReq mshr miss latency
775 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628 # average WriteReq mshr miss latency
776 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628 # average WriteReq mshr miss latency
777 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency
778 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency
779 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency
780 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency
781 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
783 ---------- End Simulation Statistics ----------
projects / gem5.git / blob