2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.983203 # Number of seconds simulated
4 sim_ticks 983202553500 # Number of ticks simulated
5 final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 94547 # Simulator instruction rate (inst/s)
8 host_op_rate 94547 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 51082649 # Simulator tick rate (ticks/s)
10 host_mem_usage 219392 # Number of bytes of host memory used
11 host_seconds 19247.29 # Real time elapsed on the host
12 sim_insts 1819780127 # Number of instructions simulated
13 sim_ops 1819780127 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory
16 system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory
17 system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
18 system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
19 system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory
20 system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory
21 system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
22 system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s)
33 system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s)
37 system.cpu.dtb.fetch_hits 0 # ITB hits
38 system.cpu.dtb.fetch_misses 0 # ITB misses
39 system.cpu.dtb.fetch_acv 0 # ITB acv
40 system.cpu.dtb.fetch_accesses 0 # ITB accesses
41 system.cpu.dtb.read_hits 444615529 # DTB read hits
42 system.cpu.dtb.read_misses 4897078 # DTB read misses
43 system.cpu.dtb.read_acv 0 # DTB read access violations
44 system.cpu.dtb.read_accesses 449512607 # DTB read accesses
45 system.cpu.dtb.write_hits 160920414 # DTB write hits
46 system.cpu.dtb.write_misses 1701304 # DTB write misses
47 system.cpu.dtb.write_acv 0 # DTB write access violations
48 system.cpu.dtb.write_accesses 162621718 # DTB write accesses
49 system.cpu.dtb.data_hits 605535943 # DTB hits
50 system.cpu.dtb.data_misses 6598382 # DTB misses
51 system.cpu.dtb.data_acv 0 # DTB access violations
52 system.cpu.dtb.data_accesses 612134325 # DTB accesses
53 system.cpu.itb.fetch_hits 232170189 # ITB hits
54 system.cpu.itb.fetch_misses 22 # ITB misses
55 system.cpu.itb.fetch_acv 0 # ITB acv
56 system.cpu.itb.fetch_accesses 232170211 # ITB accesses
57 system.cpu.itb.read_hits 0 # DTB read hits
58 system.cpu.itb.read_misses 0 # DTB read misses
59 system.cpu.itb.read_acv 0 # DTB read access violations
60 system.cpu.itb.read_accesses 0 # DTB read accesses
61 system.cpu.itb.write_hits 0 # DTB write hits
62 system.cpu.itb.write_misses 0 # DTB write misses
63 system.cpu.itb.write_acv 0 # DTB write access violations
64 system.cpu.itb.write_accesses 0 # DTB write accesses
65 system.cpu.itb.data_hits 0 # DTB hits
66 system.cpu.itb.data_misses 0 # DTB misses
67 system.cpu.itb.data_acv 0 # DTB access violations
68 system.cpu.itb.data_accesses 0 # DTB accesses
69 system.cpu.workload.num_syscalls 29 # Number of system calls
70 system.cpu.numCycles 1966405108 # number of cpu cycles simulated
71 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
72 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
73 system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups
74 system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted
75 system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect
76 system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups
77 system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits
78 system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
79 system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
80 system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage
81 system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True).
82 system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False).
83 system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File
84 system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
85 system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File
86 system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File
87 system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
88 system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File
89 system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic
90 system.cpu.agen_unit.agens 617989099 # Number of Address Generations
91 system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken.
92 system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken).
93 system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted
94 system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted
95 system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts
96 system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed.
97 system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
98 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
99 system.cpu.contextSwitches 1 # Number of context switches
100 system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
101 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
102 system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself
103 system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed
104 system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed.
105 system.cpu.activity 80.200661 # Percentage of cycles cpu is active
106 system.cpu.comLoads 444595663 # Number of Load instructions committed
107 system.cpu.comStores 160728502 # Number of Store instructions committed
108 system.cpu.comBranches 214632552 # Number of Branches instructions committed
109 system.cpu.comNops 83736345 # Number of Nop instructions committed
110 system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
111 system.cpu.comInts 916086844 # Number of Integer instructions committed
112 system.cpu.comFloats 190 # Number of Floating Point instructions committed
113 system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
114 system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
115 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
116 system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
117 system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread)
118 system.cpu.smt_cpi nan # CPI: Total SMT-CPI
119 system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads
120 system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread)
121 system.cpu.smt_ipc nan # IPC: Total SMT-IPC
122 system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads
123 system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed.
124 system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed.
125 system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts).
126 system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed.
127 system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed.
128 system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts).
129 system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed.
130 system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed.
131 system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts).
132 system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed.
133 system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed.
134 system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts).
135 system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed.
136 system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed.
137 system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts).
138 system.cpu.icache.replacements 1 # number of replacements
139 system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use
140 system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks.
141 system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
142 system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks.
143 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
144 system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor
145 system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy
146 system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy
147 system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits
148 system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits
149 system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits
150 system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits
151 system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits
152 system.cpu.icache.overall_hits::total 232169108 # number of overall hits
153 system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses
154 system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses
155 system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses
156 system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses
157 system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses
158 system.cpu.icache.overall_misses::total 1077 # number of overall misses
159 system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles
160 system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles
161 system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles
162 system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles
163 system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles
164 system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles
165 system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses)
166 system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses)
167 system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses
168 system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses
169 system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses
170 system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses
171 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
172 system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
173 system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
174 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
175 system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
176 system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
177 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency
178 system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency
179 system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
180 system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency
181 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
182 system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency
183 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
184 system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked
185 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
186 system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
187 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
188 system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked
189 system.cpu.icache.fast_writes 0 # number of fast writes performed
190 system.cpu.icache.cache_copies 0 # number of cache copies performed
191 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits
192 system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits
193 system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits
194 system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits
195 system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits
196 system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits
197 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
198 system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
199 system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
200 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
201 system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
202 system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
203 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles
204 system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles
205 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles
206 system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles
207 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles
208 system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles
209 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
210 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
211 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
212 system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
213 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
214 system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
215 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency
216 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency
217 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency
218 system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency
219 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency
220 system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency
221 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
222 system.cpu.dcache.replacements 9107371 # number of replacements
223 system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use
224 system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks.
225 system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks.
226 system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks.
227 system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit.
228 system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor
229 system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy
230 system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy
231 system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits
232 system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits
233 system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits
234 system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits
235 system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits
236 system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits
237 system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits
238 system.cpu.dcache.overall_hits::total 595063275 # number of overall hits
239 system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses
240 system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses
241 system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses
242 system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses
243 system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses
244 system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses
245 system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses
246 system.cpu.dcache.overall_misses::total 10260890 # number of overall misses
247 system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles
248 system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles
249 system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles
250 system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles
251 system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles
252 system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles
253 system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles
254 system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles
255 system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
256 system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
257 system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
258 system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
259 system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
260 system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
261 system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
262 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
263 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses
264 system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses
265 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses
266 system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses
267 system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses
268 system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses
269 system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses
270 system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses
271 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency
272 system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency
273 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency
274 system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency
275 system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
276 system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency
277 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
278 system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency
279 system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked
280 system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked
281 system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked
282 system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked
283 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked
284 system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked
285 system.cpu.dcache.fast_writes 0 # number of fast writes performed
286 system.cpu.dcache.cache_copies 0 # number of cache copies performed
287 system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks
288 system.cpu.dcache.writebacks::total 3389692 # number of writebacks
289 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits
290 system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits
291 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits
292 system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits
293 system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits
294 system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits
295 system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits
296 system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits
297 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
298 system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
299 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses
300 system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses
301 system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses
302 system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses
303 system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses
304 system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses
305 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles
306 system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles
307 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles
308 system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles
309 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles
310 system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles
311 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles
312 system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles
313 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
314 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
315 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
316 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
317 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
318 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
319 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
320 system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
321 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency
322 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency
323 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency
324 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency
325 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency
326 system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency
327 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency
328 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency
329 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
330 system.cpu.l2cache.replacements 2133758 # number of replacements
331 system.cpu.l2cache.tagsinuse 30529.573479 # Cycle average of tags in use
332 system.cpu.l2cache.total_refs 8448408 # Total number of references to valid blocks.
333 system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks.
334 system.cpu.l2cache.avg_refs 3.905065 # Average number of references to valid blocks.
335 system.cpu.l2cache.warmup_cycle 182812071500 # Cycle when the warmup percentage was hit.
336 system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor
337 system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor
338 system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor
339 system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy
340 system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy
341 system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy
342 system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy
343 system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits
344 system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits
345 system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits
346 system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits
347 system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # number of ReadExReq hits
348 system.cpu.l2cache.ReadExReq_hits::total 1100796 # number of ReadExReq hits
349 system.cpu.l2cache.demand_hits::cpu.data 6961783 # number of demand (read+write) hits
350 system.cpu.l2cache.demand_hits::total 6961783 # number of demand (read+write) hits
351 system.cpu.l2cache.overall_hits::cpu.data 6961783 # number of overall hits
352 system.cpu.l2cache.overall_hits::total 6961783 # number of overall hits
353 system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
354 system.cpu.l2cache.ReadReq_misses::cpu.data 1360851 # number of ReadReq misses
355 system.cpu.l2cache.ReadReq_misses::total 1361710 # number of ReadReq misses
356 system.cpu.l2cache.ReadExReq_misses::cpu.data 788833 # number of ReadExReq misses
357 system.cpu.l2cache.ReadExReq_misses::total 788833 # number of ReadExReq misses
358 system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
359 system.cpu.l2cache.demand_misses::cpu.data 2149684 # number of demand (read+write) misses
360 system.cpu.l2cache.demand_misses::total 2150543 # number of demand (read+write) misses
361 system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
362 system.cpu.l2cache.overall_misses::cpu.data 2149684 # number of overall misses
363 system.cpu.l2cache.overall_misses::total 2150543 # number of overall misses
364 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46256500 # number of ReadReq miss cycles
365 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71433605500 # number of ReadReq miss cycles
366 system.cpu.l2cache.ReadReq_miss_latency::total 71479862000 # number of ReadReq miss cycles
367 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42030855000 # number of ReadExReq miss cycles
368 system.cpu.l2cache.ReadExReq_miss_latency::total 42030855000 # number of ReadExReq miss cycles
369 system.cpu.l2cache.demand_miss_latency::cpu.inst 46256500 # number of demand (read+write) miss cycles
370 system.cpu.l2cache.demand_miss_latency::cpu.data 113464460500 # number of demand (read+write) miss cycles
371 system.cpu.l2cache.demand_miss_latency::total 113510717000 # number of demand (read+write) miss cycles
372 system.cpu.l2cache.overall_miss_latency::cpu.inst 46256500 # number of overall miss cycles
373 system.cpu.l2cache.overall_miss_latency::cpu.data 113464460500 # number of overall miss cycles
374 system.cpu.l2cache.overall_miss_latency::total 113510717000 # number of overall miss cycles
375 system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
376 system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses)
377 system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses)
378 system.cpu.l2cache.Writeback_accesses::writebacks 3389692 # number of Writeback accesses(hits+misses)
379 system.cpu.l2cache.Writeback_accesses::total 3389692 # number of Writeback accesses(hits+misses)
380 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889629 # number of ReadExReq accesses(hits+misses)
381 system.cpu.l2cache.ReadExReq_accesses::total 1889629 # number of ReadExReq accesses(hits+misses)
382 system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
383 system.cpu.l2cache.demand_accesses::cpu.data 9111467 # number of demand (read+write) accesses
384 system.cpu.l2cache.demand_accesses::total 9112326 # number of demand (read+write) accesses
385 system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
386 system.cpu.l2cache.overall_accesses::cpu.data 9111467 # number of overall (read+write) accesses
387 system.cpu.l2cache.overall_accesses::total 9112326 # number of overall (read+write) accesses
388 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
389 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses
390 system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses
391 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417454 # miss rate for ReadExReq accesses
392 system.cpu.l2cache.ReadExReq_miss_rate::total 0.417454 # miss rate for ReadExReq accesses
393 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
394 system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses
395 system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses
396 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
397 system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses
398 system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses
399 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency
400 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency
401 system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency
402 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53282.323382 # average ReadExReq miss latency
403 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53282.323382 # average ReadExReq miss latency
404 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
405 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
406 system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 # average overall miss latency
407 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
408 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
409 system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency
410 system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked
411 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
412 system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked
413 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
414 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked
415 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
416 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
417 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
418 system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks
419 system.cpu.l2cache.writebacks::total 1048517 # number of writebacks
420 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
421 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360851 # number of ReadReq MSHR misses
422 system.cpu.l2cache.ReadReq_mshr_misses::total 1361710 # number of ReadReq MSHR misses
423 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses
424 system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses
425 system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
426 system.cpu.l2cache.demand_mshr_misses::cpu.data 2149684 # number of demand (read+write) MSHR misses
427 system.cpu.l2cache.demand_mshr_misses::total 2150543 # number of demand (read+write) MSHR misses
428 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
429 system.cpu.l2cache.overall_mshr_misses::cpu.data 2149684 # number of overall MSHR misses
430 system.cpu.l2cache.overall_mshr_misses::total 2150543 # number of overall MSHR misses
431 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35788000 # number of ReadReq MSHR miss cycles
432 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54811327000 # number of ReadReq MSHR miss cycles
433 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54847115000 # number of ReadReq MSHR miss cycles
434 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32423383500 # number of ReadExReq MSHR miss cycles
435 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles
436 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles
437 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles
438 system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles
439 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles
440 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles
441 system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles
442 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
443 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses
444 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
445 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417454 # mshr miss rate for ReadExReq accesses
446 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417454 # mshr miss rate for ReadExReq accesses
447 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
448 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses
449 system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses
450 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
451 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
452 system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
453 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency
454 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency
455 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency
456 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency
457 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency
458 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency
459 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency
460 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency
461 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency
462 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency
463 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency
464 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
466 ---------- End Simulation Statistics ----------
projects / gem5.git / blob