2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.009857 # Number of seconds simulated
4 sim_ticks 1009857089500 # Number of ticks simulated
5 final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 102085 # Simulator instruction rate (inst/s)
8 host_tick_rate 56650413 # Simulator tick rate (ticks/s)
9 host_mem_usage 208040 # Number of bytes of host memory used
10 host_seconds 17826.12 # Real time elapsed on the host
11 sim_insts 1819780127 # Number of instructions simulated
12 system.physmem.bytes_read 172617984 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 74938304 # Number of bytes written to this memory
15 system.physmem.num_reads 2697156 # Number of read requests responded to by this memory
16 system.physmem.num_writes 1170911 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s)
22 system.cpu.dtb.fetch_hits 0 # ITB hits
23 system.cpu.dtb.fetch_misses 0 # ITB misses
24 system.cpu.dtb.fetch_acv 0 # ITB acv
25 system.cpu.dtb.fetch_accesses 0 # ITB accesses
26 system.cpu.dtb.read_hits 444614420 # DTB read hits
27 system.cpu.dtb.read_misses 4897078 # DTB read misses
28 system.cpu.dtb.read_acv 0 # DTB read access violations
29 system.cpu.dtb.read_accesses 449511498 # DTB read accesses
30 system.cpu.dtb.write_hits 160920903 # DTB write hits
31 system.cpu.dtb.write_misses 1701304 # DTB write misses
32 system.cpu.dtb.write_acv 0 # DTB write access violations
33 system.cpu.dtb.write_accesses 162622207 # DTB write accesses
34 system.cpu.dtb.data_hits 605535323 # DTB hits
35 system.cpu.dtb.data_misses 6598382 # DTB misses
36 system.cpu.dtb.data_acv 0 # DTB access violations
37 system.cpu.dtb.data_accesses 612133705 # DTB accesses
38 system.cpu.itb.fetch_hits 233080732 # ITB hits
39 system.cpu.itb.fetch_misses 22 # ITB misses
40 system.cpu.itb.fetch_acv 0 # ITB acv
41 system.cpu.itb.fetch_accesses 233080754 # ITB accesses
42 system.cpu.itb.read_hits 0 # DTB read hits
43 system.cpu.itb.read_misses 0 # DTB read misses
44 system.cpu.itb.read_acv 0 # DTB read access violations
45 system.cpu.itb.read_accesses 0 # DTB read accesses
46 system.cpu.itb.write_hits 0 # DTB write hits
47 system.cpu.itb.write_misses 0 # DTB write misses
48 system.cpu.itb.write_acv 0 # DTB write access violations
49 system.cpu.itb.write_accesses 0 # DTB write accesses
50 system.cpu.itb.data_hits 0 # DTB hits
51 system.cpu.itb.data_misses 0 # DTB misses
52 system.cpu.itb.data_acv 0 # DTB access violations
53 system.cpu.itb.data_accesses 0 # DTB accesses
54 system.cpu.workload.num_syscalls 29 # Number of system calls
55 system.cpu.numCycles 2019714180 # number of cpu cycles simulated
56 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58 system.cpu.contextSwitches 1 # Number of context switches
59 system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
60 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
61 system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself
62 system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed
63 system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed.
64 system.cpu.activity 78.072669 # Percentage of cycles cpu is active
65 system.cpu.comLoads 444595663 # Number of Load instructions committed
66 system.cpu.comStores 160728502 # Number of Store instructions committed
67 system.cpu.comBranches 214632552 # Number of Branches instructions committed
68 system.cpu.comNops 83736345 # Number of Nop instructions committed
69 system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
70 system.cpu.comInts 916086844 # Number of Integer instructions committed
71 system.cpu.comFloats 190 # Number of Floating Point instructions committed
72 system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread)
73 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
74 system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total)
75 system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread)
76 system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
77 system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads
78 system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread)
79 system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
80 system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads
81 system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups
82 system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted
83 system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect
84 system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups
85 system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits
86 system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
87 system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
88 system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage
89 system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True).
90 system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False).
91 system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File
92 system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
93 system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File
94 system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
95 system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
96 system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
97 system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic
98 system.cpu.agen_unit.agens 617252269 # Number of Address Generations
99 system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken.
100 system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken).
101 system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted
102 system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted
103 system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts
104 system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed.
105 system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
106 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
107 system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed.
108 system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed.
109 system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts).
110 system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed.
111 system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed.
112 system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts).
113 system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed.
114 system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed.
115 system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts).
116 system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed.
117 system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed.
118 system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts).
119 system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed.
120 system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed.
121 system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts).
122 system.cpu.icache.replacements 1 # number of replacements
123 system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use
124 system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks.
125 system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks.
126 system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks.
127 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
128 system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context
129 system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy
130 system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits
131 system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits
132 system.cpu.icache.overall_hits 233079667 # number of overall hits
133 system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses
134 system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses
135 system.cpu.icache.overall_misses 1062 # number of overall misses
136 system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles
137 system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles
138 system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles
139 system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses)
140 system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses
141 system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses
142 system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
143 system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
144 system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
145 system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency
146 system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency
147 system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency
148 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
149 system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
150 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
151 system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
152 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
153 system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked
154 system.cpu.icache.fast_writes 0 # number of fast writes performed
155 system.cpu.icache.cache_copies 0 # number of cache copies performed
156 system.cpu.icache.writebacks 0 # number of writebacks
157 system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits
158 system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits
159 system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits
160 system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses
161 system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses
162 system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses
163 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
164 system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles
165 system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles
166 system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles
167 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
168 system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
169 system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
170 system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
171 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency
172 system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
173 system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
174 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
175 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
176 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
177 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
178 system.cpu.dcache.replacements 9107352 # number of replacements
179 system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use
180 system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks.
181 system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
182 system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks.
183 system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit.
184 system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context
185 system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy
186 system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits
187 system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits
188 system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits
189 system.cpu.dcache.overall_hits 595070081 # number of overall hits
190 system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses
191 system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses
192 system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses
193 system.cpu.dcache.overall_misses 10254084 # number of overall misses
194 system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles
195 system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles
196 system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles
197 system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles
198 system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
199 system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
200 system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
201 system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
202 system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses
203 system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses
204 system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses
205 system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses
206 system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency
207 system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency
208 system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency
209 system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency
210 system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked
211 system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked
212 system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked
213 system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked
214 system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked
215 system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked
216 system.cpu.dcache.fast_writes 0 # number of fast writes performed
217 system.cpu.dcache.cache_copies 0 # number of cache copies performed
218 system.cpu.dcache.writebacks 3058572 # number of writebacks
219 system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits
220 system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits
221 system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits
222 system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits
223 system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses
224 system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses
225 system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses
226 system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses
227 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
228 system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles
229 system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles
230 system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles
231 system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles
232 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
233 system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
234 system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
235 system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses
236 system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses
237 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency
238 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency
239 system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
240 system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
241 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
242 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
243 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
244 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
245 system.cpu.l2cache.replacements 2686299 # number of replacements
246 system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use
247 system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks.
248 system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks.
249 system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks.
250 system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit.
251 system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context
252 system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context
253 system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy
254 system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy
255 system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits
256 system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits
257 system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits
258 system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits
259 system.cpu.l2cache.overall_hits 6415150 # number of overall hits
260 system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses
261 system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses
262 system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses
263 system.cpu.l2cache.overall_misses 2697156 # number of overall misses
264 system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles
265 system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles
266 system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles
267 system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles
268 system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses)
269 system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses)
270 system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses)
271 system.cpu.l2cache.demand_accesses 9112306 # number of demand (read+write) accesses
272 system.cpu.l2cache.overall_accesses 9112306 # number of overall (read+write) accesses
273 system.cpu.l2cache.ReadReq_miss_rate 0.250305 # miss rate for ReadReq accesses
274 system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses
275 system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses
276 system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses
277 system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency
278 system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency
279 system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency
280 system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency
281 system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
282 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
283 system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
284 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
285 system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked
286 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
287 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
288 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
289 system.cpu.l2cache.writebacks 1170911 # number of writebacks
290 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
291 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
292 system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses
293 system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses
294 system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses
295 system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses
296 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
297 system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles
298 system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles
299 system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles
300 system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles
301 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
302 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses
303 system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses
304 system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses
305 system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses
306 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency
307 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency
308 system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
309 system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
310 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
311 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
312 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
313 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
315 ---------- End Simulation Statistics ----------
projects / gem5.git / blob