tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 eventq_index=0
  18 init_param=0
  19 kernel=
  20 load_addr_mask=1099511627775
  21 mem_mode=timing
  22 mem_ranges=
  23 memories=system.physmem
  24 num_work_ids=16
  25 readfile=
  26 symbolfile=
  27 work_begin_ckpt_count=0
  28 work_begin_cpu_id_exit=-1
  29 work_begin_exit_count=0
  30 work_cpus_ckpt_count=0
  31 work_end_ckpt_count=0
  32 work_end_exit_count=0
  33 work_item_id=-1
  34 system_port=system.membus.slave[0]
  35
  36 [system.clk_domain]
  37 type=SrcClockDomain
  38 clock=1000
  39 eventq_index=0
  40 voltage_domain=system.voltage_domain
  41
  42 [system.cpu]
  43 type=DerivO3CPU
  44 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  45 LFSTSize=1024
  46 LQEntries=32
  47 LSQCheckLoads=true
  48 LSQDepCheckShift=4
  49 SQEntries=32
  50 SSITSize=1024
  51 activity=0
  52 backComSize=5
  53 branchPred=system.cpu.branchPred
  54 cachePorts=200
  55 checker=Null
  56 clk_domain=system.cpu_clk_domain
  57 commitToDecodeDelay=1
  58 commitToFetchDelay=1
  59 commitToIEWDelay=1
  60 commitToRenameDelay=1
  61 commitWidth=8
  62 cpu_id=0
  63 decodeToFetchDelay=1
  64 decodeToRenameDelay=1
  65 decodeWidth=8
  66 dispatchWidth=8
  67 do_checkpoint_insts=true
  68 do_quiesce=true
  69 do_statistics_insts=true
  70 dtb=system.cpu.dtb
  71 eventq_index=0
  72 fetchBufferSize=64
  73 fetchToDecodeDelay=1
  74 fetchTrapLatency=1
  75 fetchWidth=8
  76 forwardComSize=5
  77 fuPool=system.cpu.fuPool
  78 function_trace=false
  79 function_trace_start=0
  80 iewToCommitDelay=1
  81 iewToDecodeDelay=1
  82 iewToFetchDelay=1
  83 iewToRenameDelay=1
  84 interrupts=system.cpu.interrupts
  85 isa=system.cpu.isa
  86 issueToExecuteDelay=1
  87 issueWidth=8
  88 itb=system.cpu.itb
  89 max_insts_all_threads=0
  90 max_insts_any_thread=0
  91 max_loads_all_threads=0
  92 max_loads_any_thread=0
  93 needsTSO=false
  94 numIQEntries=64
  95 numPhysCCRegs=0
  96 numPhysFloatRegs=256
  97 numPhysIntRegs=256
  98 numROBEntries=192
  99 numRobs=1
 100 numThreads=1
 101 profile=0
 102 progress_interval=0
 103 renameToDecodeDelay=1
 104 renameToFetchDelay=1
 105 renameToIEWDelay=2
 106 renameToROBDelay=1
 107 renameWidth=8
 108 simpoint_start_insts=
 109 smtCommitPolicy=RoundRobin
 110 smtFetchPolicy=SingleThread
 111 smtIQPolicy=Partitioned
 112 smtIQThreshold=100
 113 smtLSQPolicy=Partitioned
 114 smtLSQThreshold=100
 115 smtNumFetchingThreads=1
 116 smtROBPolicy=Partitioned
 117 smtROBThreshold=100
 118 squashWidth=8
 119 store_set_clear_period=250000
 120 switched_out=false
 121 system=system
 122 tracer=system.cpu.tracer
 123 trapLatency=13
 124 wbDepth=1
 125 wbWidth=8
 126 workload=system.cpu.workload
 127 dcache_port=system.cpu.dcache.cpu_side
 128 icache_port=system.cpu.icache.cpu_side
 129
 130 [system.cpu.branchPred]
 131 type=BranchPredictor
 132 BTBEntries=4096
 133 BTBTagSize=16
 134 RASSize=16
 135 choiceCtrBits=2
 136 choicePredictorSize=8192
 137 eventq_index=0
 138 globalCtrBits=2
 139 globalPredictorSize=8192
 140 instShiftAmt=2
 141 localCtrBits=2
 142 localHistoryTableSize=2048
 143 localPredictorSize=2048
 144 numThreads=1
 145 predType=tournament
 146
 147 [system.cpu.dcache]
 148 type=BaseCache
 149 children=tags
 150 addr_ranges=0:18446744073709551615
 151 assoc=2
 152 clk_domain=system.cpu_clk_domain
 153 eventq_index=0
 154 forward_snoops=true
 155 hit_latency=2
 156 is_top_level=true
 157 max_miss_count=0
 158 mshrs=4
 159 prefetch_on_access=false
 160 prefetcher=Null
 161 response_latency=2
 162 size=262144
 163 system=system
 164 tags=system.cpu.dcache.tags
 165 tgts_per_mshr=20
 166 two_queue=false
 167 write_buffers=8
 168 cpu_side=system.cpu.dcache_port
 169 mem_side=system.cpu.toL2Bus.slave[1]
 170
 171 [system.cpu.dcache.tags]
 172 type=LRU
 173 assoc=2
 174 block_size=64
 175 clk_domain=system.cpu_clk_domain
 176 eventq_index=0
 177 hit_latency=2
 178 size=262144
 179
 180 [system.cpu.dtb]
 181 type=AlphaTLB
 182 eventq_index=0
 183 size=64
 184
 185 [system.cpu.fuPool]
 186 type=FUPool
 187 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 188 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 189 eventq_index=0
 190
 191 [system.cpu.fuPool.FUList0]
 192 type=FUDesc
 193 children=opList
 194 count=6
 195 eventq_index=0
 196 opList=system.cpu.fuPool.FUList0.opList
 197
 198 [system.cpu.fuPool.FUList0.opList]
 199 type=OpDesc
 200 eventq_index=0
 201 issueLat=1
 202 opClass=IntAlu
 203 opLat=1
 204
 205 [system.cpu.fuPool.FUList1]
 206 type=FUDesc
 207 children=opList0 opList1
 208 count=2
 209 eventq_index=0
 210 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 211
 212 [system.cpu.fuPool.FUList1.opList0]
 213 type=OpDesc
 214 eventq_index=0
 215 issueLat=1
 216 opClass=IntMult
 217 opLat=3
 218
 219 [system.cpu.fuPool.FUList1.opList1]
 220 type=OpDesc
 221 eventq_index=0
 222 issueLat=19
 223 opClass=IntDiv
 224 opLat=20
 225
 226 [system.cpu.fuPool.FUList2]
 227 type=FUDesc
 228 children=opList0 opList1 opList2
 229 count=4
 230 eventq_index=0
 231 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 232
 233 [system.cpu.fuPool.FUList2.opList0]
 234 type=OpDesc
 235 eventq_index=0
 236 issueLat=1
 237 opClass=FloatAdd
 238 opLat=2
 239
 240 [system.cpu.fuPool.FUList2.opList1]
 241 type=OpDesc
 242 eventq_index=0
 243 issueLat=1
 244 opClass=FloatCmp
 245 opLat=2
 246
 247 [system.cpu.fuPool.FUList2.opList2]
 248 type=OpDesc
 249 eventq_index=0
 250 issueLat=1
 251 opClass=FloatCvt
 252 opLat=2
 253
 254 [system.cpu.fuPool.FUList3]
 255 type=FUDesc
 256 children=opList0 opList1 opList2
 257 count=2
 258 eventq_index=0
 259 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 260
 261 [system.cpu.fuPool.FUList3.opList0]
 262 type=OpDesc
 263 eventq_index=0
 264 issueLat=1
 265 opClass=FloatMult
 266 opLat=4
 267
 268 [system.cpu.fuPool.FUList3.opList1]
 269 type=OpDesc
 270 eventq_index=0
 271 issueLat=12
 272 opClass=FloatDiv
 273 opLat=12
 274
 275 [system.cpu.fuPool.FUList3.opList2]
 276 type=OpDesc
 277 eventq_index=0
 278 issueLat=24
 279 opClass=FloatSqrt
 280 opLat=24
 281
 282 [system.cpu.fuPool.FUList4]
 283 type=FUDesc
 284 children=opList
 285 count=0
 286 eventq_index=0
 287 opList=system.cpu.fuPool.FUList4.opList
 288
 289 [system.cpu.fuPool.FUList4.opList]
 290 type=OpDesc
 291 eventq_index=0
 292 issueLat=1
 293 opClass=MemRead
 294 opLat=1
 295
 296 [system.cpu.fuPool.FUList5]
 297 type=FUDesc
 298 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 299 count=4
 300 eventq_index=0
 301 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 302
 303 [system.cpu.fuPool.FUList5.opList00]
 304 type=OpDesc
 305 eventq_index=0
 306 issueLat=1
 307 opClass=SimdAdd
 308 opLat=1
 309
 310 [system.cpu.fuPool.FUList5.opList01]
 311 type=OpDesc
 312 eventq_index=0
 313 issueLat=1
 314 opClass=SimdAddAcc
 315 opLat=1
 316
 317 [system.cpu.fuPool.FUList5.opList02]
 318 type=OpDesc
 319 eventq_index=0
 320 issueLat=1
 321 opClass=SimdAlu
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList03]
 325 type=OpDesc
 326 eventq_index=0
 327 issueLat=1
 328 opClass=SimdCmp
 329 opLat=1
 330
 331 [system.cpu.fuPool.FUList5.opList04]
 332 type=OpDesc
 333 eventq_index=0
 334 issueLat=1
 335 opClass=SimdCvt
 336 opLat=1
 337
 338 [system.cpu.fuPool.FUList5.opList05]
 339 type=OpDesc
 340 eventq_index=0
 341 issueLat=1
 342 opClass=SimdMisc
 343 opLat=1
 344
 345 [system.cpu.fuPool.FUList5.opList06]
 346 type=OpDesc
 347 eventq_index=0
 348 issueLat=1
 349 opClass=SimdMult
 350 opLat=1
 351
 352 [system.cpu.fuPool.FUList5.opList07]
 353 type=OpDesc
 354 eventq_index=0
 355 issueLat=1
 356 opClass=SimdMultAcc
 357 opLat=1
 358
 359 [system.cpu.fuPool.FUList5.opList08]
 360 type=OpDesc
 361 eventq_index=0
 362 issueLat=1
 363 opClass=SimdShift
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList09]
 367 type=OpDesc
 368 eventq_index=0
 369 issueLat=1
 370 opClass=SimdShiftAcc
 371 opLat=1
 372
 373 [system.cpu.fuPool.FUList5.opList10]
 374 type=OpDesc
 375 eventq_index=0
 376 issueLat=1
 377 opClass=SimdSqrt
 378 opLat=1
 379
 380 [system.cpu.fuPool.FUList5.opList11]
 381 type=OpDesc
 382 eventq_index=0
 383 issueLat=1
 384 opClass=SimdFloatAdd
 385 opLat=1
 386
 387 [system.cpu.fuPool.FUList5.opList12]
 388 type=OpDesc
 389 eventq_index=0
 390 issueLat=1
 391 opClass=SimdFloatAlu
 392 opLat=1
 393
 394 [system.cpu.fuPool.FUList5.opList13]
 395 type=OpDesc
 396 eventq_index=0
 397 issueLat=1
 398 opClass=SimdFloatCmp
 399 opLat=1
 400
 401 [system.cpu.fuPool.FUList5.opList14]
 402 type=OpDesc
 403 eventq_index=0
 404 issueLat=1
 405 opClass=SimdFloatCvt
 406 opLat=1
 407
 408 [system.cpu.fuPool.FUList5.opList15]
 409 type=OpDesc
 410 eventq_index=0
 411 issueLat=1
 412 opClass=SimdFloatDiv
 413 opLat=1
 414
 415 [system.cpu.fuPool.FUList5.opList16]
 416 type=OpDesc
 417 eventq_index=0
 418 issueLat=1
 419 opClass=SimdFloatMisc
 420 opLat=1
 421
 422 [system.cpu.fuPool.FUList5.opList17]
 423 type=OpDesc
 424 eventq_index=0
 425 issueLat=1
 426 opClass=SimdFloatMult
 427 opLat=1
 428
 429 [system.cpu.fuPool.FUList5.opList18]
 430 type=OpDesc
 431 eventq_index=0
 432 issueLat=1
 433 opClass=SimdFloatMultAcc
 434 opLat=1
 435
 436 [system.cpu.fuPool.FUList5.opList19]
 437 type=OpDesc
 438 eventq_index=0
 439 issueLat=1
 440 opClass=SimdFloatSqrt
 441 opLat=1
 442
 443 [system.cpu.fuPool.FUList6]
 444 type=FUDesc
 445 children=opList
 446 count=0
 447 eventq_index=0
 448 opList=system.cpu.fuPool.FUList6.opList
 449
 450 [system.cpu.fuPool.FUList6.opList]
 451 type=OpDesc
 452 eventq_index=0
 453 issueLat=1
 454 opClass=MemWrite
 455 opLat=1
 456
 457 [system.cpu.fuPool.FUList7]
 458 type=FUDesc
 459 children=opList0 opList1
 460 count=4
 461 eventq_index=0
 462 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 463
 464 [system.cpu.fuPool.FUList7.opList0]
 465 type=OpDesc
 466 eventq_index=0
 467 issueLat=1
 468 opClass=MemRead
 469 opLat=1
 470
 471 [system.cpu.fuPool.FUList7.opList1]
 472 type=OpDesc
 473 eventq_index=0
 474 issueLat=1
 475 opClass=MemWrite
 476 opLat=1
 477
 478 [system.cpu.fuPool.FUList8]
 479 type=FUDesc
 480 children=opList
 481 count=1
 482 eventq_index=0
 483 opList=system.cpu.fuPool.FUList8.opList
 484
 485 [system.cpu.fuPool.FUList8.opList]
 486 type=OpDesc
 487 eventq_index=0
 488 issueLat=3
 489 opClass=IprAccess
 490 opLat=3
 491
 492 [system.cpu.icache]
 493 type=BaseCache
 494 children=tags
 495 addr_ranges=0:18446744073709551615
 496 assoc=2
 497 clk_domain=system.cpu_clk_domain
 498 eventq_index=0
 499 forward_snoops=true
 500 hit_latency=2
 501 is_top_level=true
 502 max_miss_count=0
 503 mshrs=4
 504 prefetch_on_access=false
 505 prefetcher=Null
 506 response_latency=2
 507 size=131072
 508 system=system
 509 tags=system.cpu.icache.tags
 510 tgts_per_mshr=20
 511 two_queue=false
 512 write_buffers=8
 513 cpu_side=system.cpu.icache_port
 514 mem_side=system.cpu.toL2Bus.slave[0]
 515
 516 [system.cpu.icache.tags]
 517 type=LRU
 518 assoc=2
 519 block_size=64
 520 clk_domain=system.cpu_clk_domain
 521 eventq_index=0
 522 hit_latency=2
 523 size=131072
 524
 525 [system.cpu.interrupts]
 526 type=AlphaInterrupts
 527 eventq_index=0
 528
 529 [system.cpu.isa]
 530 type=AlphaISA
 531 eventq_index=0
 532
 533 [system.cpu.itb]
 534 type=AlphaTLB
 535 eventq_index=0
 536 size=48
 537
 538 [system.cpu.l2cache]
 539 type=BaseCache
 540 children=tags
 541 addr_ranges=0:18446744073709551615
 542 assoc=8
 543 clk_domain=system.cpu_clk_domain
 544 eventq_index=0
 545 forward_snoops=true
 546 hit_latency=20
 547 is_top_level=false
 548 max_miss_count=0
 549 mshrs=20
 550 prefetch_on_access=false
 551 prefetcher=Null
 552 response_latency=20
 553 size=2097152
 554 system=system
 555 tags=system.cpu.l2cache.tags
 556 tgts_per_mshr=12
 557 two_queue=false
 558 write_buffers=8
 559 cpu_side=system.cpu.toL2Bus.master[0]
 560 mem_side=system.membus.slave[1]
 561
 562 [system.cpu.l2cache.tags]
 563 type=LRU
 564 assoc=8
 565 block_size=64
 566 clk_domain=system.cpu_clk_domain
 567 eventq_index=0
 568 hit_latency=20
 569 size=2097152
 570
 571 [system.cpu.toL2Bus]
 572 type=CoherentBus
 573 clk_domain=system.cpu_clk_domain
 574 eventq_index=0
 575 header_cycles=1
 576 system=system
 577 use_default_range=false
 578 width=32
 579 master=system.cpu.l2cache.cpu_side
 580 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 581
 582 [system.cpu.tracer]
 583 type=ExeTracer
 584 eventq_index=0
 585
 586 [system.cpu.workload]
 587 type=LiveProcess
 588 cmd=bzip2 input.source 1
 589 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 590 egid=100
 591 env=
 592 errout=cerr
 593 euid=100
 594 eventq_index=0
 595 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 596 gid=100
 597 input=cin
 598 max_stack_size=67108864
 599 output=cout
 600 pid=100
 601 ppid=99
 602 simpoint=0
 603 system=system
 604 uid=100
 605
 606 [system.cpu_clk_domain]
 607 type=SrcClockDomain
 608 clock=500
 609 eventq_index=0
 610 voltage_domain=system.voltage_domain
 611
 612 [system.membus]
 613 type=CoherentBus
 614 clk_domain=system.clk_domain
 615 eventq_index=0
 616 header_cycles=1
 617 system=system
 618 use_default_range=false
 619 width=8
 620 master=system.physmem.port
 621 slave=system.system_port system.cpu.l2cache.mem_side
 622
 623 [system.physmem]
 624 type=SimpleDRAM
 625 activation_limit=4
 626 addr_mapping=RaBaChCo
 627 banks_per_rank=8
 628 burst_length=8
 629 channels=1
 630 clk_domain=system.clk_domain
 631 conf_table_reported=true
 632 device_bus_width=8
 633 device_rowbuffer_size=1024
 634 devices_per_rank=8
 635 eventq_index=0
 636 in_addr_map=true
 637 mem_sched_policy=frfcfs
 638 null=false
 639 page_policy=open
 640 range=0:134217727
 641 ranks_per_channel=2
 642 read_buffer_size=32
 643 static_backend_latency=10000
 644 static_frontend_latency=10000
 645 tBURST=5000
 646 tCL=13750
 647 tRAS=35000
 648 tRCD=13750
 649 tREFI=7800000
 650 tRFC=300000
 651 tRP=13750
 652 tRRD=6250
 653 tWTR=7500
 654 tXAW=40000
 655 write_buffer_size=32
 656 write_high_thresh_perc=70
 657 write_low_thresh_perc=0
 658 port=system.membus.master[0]
 659
 660 [system.voltage_domain]
 661 type=VoltageDomain
 662 eventq_index=0
 663 voltage=1.000000
 664