tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 full_system=false
   5 time_sync_enable=false
   6 time_sync_period=100000000000
   7 time_sync_spin_threshold=100000000
   8
   9 [system]
  10 type=System
  11 children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
  12 boot_osflags=a
  13 cache_line_size=64
  14 clk_domain=system.clk_domain
  15 init_param=0
  16 kernel=
  17 load_addr_mask=1099511627775
  18 mem_mode=timing
  19 mem_ranges=
  20 memories=system.physmem
  21 num_work_ids=16
  22 readfile=
  23 symbolfile=
  24 work_begin_ckpt_count=0
  25 work_begin_cpu_id_exit=-1
  26 work_begin_exit_count=0
  27 work_cpus_ckpt_count=0
  28 work_end_ckpt_count=0
  29 work_end_exit_count=0
  30 work_item_id=-1
  31 system_port=system.membus.slave[0]
  32
  33 [system.clk_domain]
  34 type=SrcClockDomain
  35 clock=1000
  36 voltage_domain=system.voltage_domain
  37
  38 [system.cpu]
  39 type=DerivO3CPU
  40 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
  41 LFSTSize=1024
  42 LQEntries=32
  43 LSQCheckLoads=true
  44 LSQDepCheckShift=4
  45 SQEntries=32
  46 SSITSize=1024
  47 activity=0
  48 backComSize=5
  49 branchPred=system.cpu.branchPred
  50 cachePorts=200
  51 checker=Null
  52 clk_domain=system.cpu_clk_domain
  53 commitToDecodeDelay=1
  54 commitToFetchDelay=1
  55 commitToIEWDelay=1
  56 commitToRenameDelay=1
  57 commitWidth=8
  58 cpu_id=0
  59 decodeToFetchDelay=1
  60 decodeToRenameDelay=1
  61 decodeWidth=8
  62 dispatchWidth=8
  63 do_checkpoint_insts=true
  64 do_quiesce=true
  65 do_statistics_insts=true
  66 dtb=system.cpu.dtb
  67 fetchToDecodeDelay=1
  68 fetchTrapLatency=1
  69 fetchWidth=8
  70 forwardComSize=5
  71 fuPool=system.cpu.fuPool
  72 function_trace=false
  73 function_trace_start=0
  74 iewToCommitDelay=1
  75 iewToDecodeDelay=1
  76 iewToFetchDelay=1
  77 iewToRenameDelay=1
  78 interrupts=system.cpu.interrupts
  79 isa=system.cpu.isa
  80 issueToExecuteDelay=1
  81 issueWidth=8
  82 itb=system.cpu.itb
  83 max_insts_all_threads=0
  84 max_insts_any_thread=0
  85 max_loads_all_threads=0
  86 max_loads_any_thread=0
  87 needsTSO=false
  88 numIQEntries=64
  89 numPhysCCRegs=0
  90 numPhysFloatRegs=256
  91 numPhysIntRegs=256
  92 numROBEntries=192
  93 numRobs=1
  94 numThreads=1
  95 profile=0
  96 progress_interval=0
  97 renameToDecodeDelay=1
  98 renameToFetchDelay=1
  99 renameToIEWDelay=2
 100 renameToROBDelay=1
 101 renameWidth=8
 102 simpoint_start_insts=
 103 smtCommitPolicy=RoundRobin
 104 smtFetchPolicy=SingleThread
 105 smtIQPolicy=Partitioned
 106 smtIQThreshold=100
 107 smtLSQPolicy=Partitioned
 108 smtLSQThreshold=100
 109 smtNumFetchingThreads=1
 110 smtROBPolicy=Partitioned
 111 smtROBThreshold=100
 112 squashWidth=8
 113 store_set_clear_period=250000
 114 switched_out=false
 115 system=system
 116 tracer=system.cpu.tracer
 117 trapLatency=13
 118 wbDepth=1
 119 wbWidth=8
 120 workload=system.cpu.workload
 121 dcache_port=system.cpu.dcache.cpu_side
 122 icache_port=system.cpu.icache.cpu_side
 123
 124 [system.cpu.branchPred]
 125 type=BranchPredictor
 126 BTBEntries=4096
 127 BTBTagSize=16
 128 RASSize=16
 129 choiceCtrBits=2
 130 choicePredictorSize=8192
 131 globalCtrBits=2
 132 globalPredictorSize=8192
 133 instShiftAmt=2
 134 localCtrBits=2
 135 localHistoryTableSize=2048
 136 localPredictorSize=2048
 137 numThreads=1
 138 predType=tournament
 139
 140 [system.cpu.dcache]
 141 type=BaseCache
 142 children=tags
 143 addr_ranges=0:18446744073709551615
 144 assoc=2
 145 clk_domain=system.cpu_clk_domain
 146 forward_snoops=true
 147 hit_latency=2
 148 is_top_level=true
 149 max_miss_count=0
 150 mshrs=4
 151 prefetch_on_access=false
 152 prefetcher=Null
 153 response_latency=2
 154 size=262144
 155 system=system
 156 tags=system.cpu.dcache.tags
 157 tgts_per_mshr=20
 158 two_queue=false
 159 write_buffers=8
 160 cpu_side=system.cpu.dcache_port
 161 mem_side=system.cpu.toL2Bus.slave[1]
 162
 163 [system.cpu.dcache.tags]
 164 type=LRU
 165 assoc=2
 166 block_size=64
 167 clk_domain=system.cpu_clk_domain
 168 hit_latency=2
 169 size=262144
 170
 171 [system.cpu.dtb]
 172 type=AlphaTLB
 173 size=64
 174
 175 [system.cpu.fuPool]
 176 type=FUPool
 177 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 178 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 179
 180 [system.cpu.fuPool.FUList0]
 181 type=FUDesc
 182 children=opList
 183 count=6
 184 opList=system.cpu.fuPool.FUList0.opList
 185
 186 [system.cpu.fuPool.FUList0.opList]
 187 type=OpDesc
 188 issueLat=1
 189 opClass=IntAlu
 190 opLat=1
 191
 192 [system.cpu.fuPool.FUList1]
 193 type=FUDesc
 194 children=opList0 opList1
 195 count=2
 196 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 197
 198 [system.cpu.fuPool.FUList1.opList0]
 199 type=OpDesc
 200 issueLat=1
 201 opClass=IntMult
 202 opLat=3
 203
 204 [system.cpu.fuPool.FUList1.opList1]
 205 type=OpDesc
 206 issueLat=19
 207 opClass=IntDiv
 208 opLat=20
 209
 210 [system.cpu.fuPool.FUList2]
 211 type=FUDesc
 212 children=opList0 opList1 opList2
 213 count=4
 214 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 215
 216 [system.cpu.fuPool.FUList2.opList0]
 217 type=OpDesc
 218 issueLat=1
 219 opClass=FloatAdd
 220 opLat=2
 221
 222 [system.cpu.fuPool.FUList2.opList1]
 223 type=OpDesc
 224 issueLat=1
 225 opClass=FloatCmp
 226 opLat=2
 227
 228 [system.cpu.fuPool.FUList2.opList2]
 229 type=OpDesc
 230 issueLat=1
 231 opClass=FloatCvt
 232 opLat=2
 233
 234 [system.cpu.fuPool.FUList3]
 235 type=FUDesc
 236 children=opList0 opList1 opList2
 237 count=2
 238 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 239
 240 [system.cpu.fuPool.FUList3.opList0]
 241 type=OpDesc
 242 issueLat=1
 243 opClass=FloatMult
 244 opLat=4
 245
 246 [system.cpu.fuPool.FUList3.opList1]
 247 type=OpDesc
 248 issueLat=12
 249 opClass=FloatDiv
 250 opLat=12
 251
 252 [system.cpu.fuPool.FUList3.opList2]
 253 type=OpDesc
 254 issueLat=24
 255 opClass=FloatSqrt
 256 opLat=24
 257
 258 [system.cpu.fuPool.FUList4]
 259 type=FUDesc
 260 children=opList
 261 count=0
 262 opList=system.cpu.fuPool.FUList4.opList
 263
 264 [system.cpu.fuPool.FUList4.opList]
 265 type=OpDesc
 266 issueLat=1
 267 opClass=MemRead
 268 opLat=1
 269
 270 [system.cpu.fuPool.FUList5]
 271 type=FUDesc
 272 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 273 count=4
 274 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 275
 276 [system.cpu.fuPool.FUList5.opList00]
 277 type=OpDesc
 278 issueLat=1
 279 opClass=SimdAdd
 280 opLat=1
 281
 282 [system.cpu.fuPool.FUList5.opList01]
 283 type=OpDesc
 284 issueLat=1
 285 opClass=SimdAddAcc
 286 opLat=1
 287
 288 [system.cpu.fuPool.FUList5.opList02]
 289 type=OpDesc
 290 issueLat=1
 291 opClass=SimdAlu
 292 opLat=1
 293
 294 [system.cpu.fuPool.FUList5.opList03]
 295 type=OpDesc
 296 issueLat=1
 297 opClass=SimdCmp
 298 opLat=1
 299
 300 [system.cpu.fuPool.FUList5.opList04]
 301 type=OpDesc
 302 issueLat=1
 303 opClass=SimdCvt
 304 opLat=1
 305
 306 [system.cpu.fuPool.FUList5.opList05]
 307 type=OpDesc
 308 issueLat=1
 309 opClass=SimdMisc
 310 opLat=1
 311
 312 [system.cpu.fuPool.FUList5.opList06]
 313 type=OpDesc
 314 issueLat=1
 315 opClass=SimdMult
 316 opLat=1
 317
 318 [system.cpu.fuPool.FUList5.opList07]
 319 type=OpDesc
 320 issueLat=1
 321 opClass=SimdMultAcc
 322 opLat=1
 323
 324 [system.cpu.fuPool.FUList5.opList08]
 325 type=OpDesc
 326 issueLat=1
 327 opClass=SimdShift
 328 opLat=1
 329
 330 [system.cpu.fuPool.FUList5.opList09]
 331 type=OpDesc
 332 issueLat=1
 333 opClass=SimdShiftAcc
 334 opLat=1
 335
 336 [system.cpu.fuPool.FUList5.opList10]
 337 type=OpDesc
 338 issueLat=1
 339 opClass=SimdSqrt
 340 opLat=1
 341
 342 [system.cpu.fuPool.FUList5.opList11]
 343 type=OpDesc
 344 issueLat=1
 345 opClass=SimdFloatAdd
 346 opLat=1
 347
 348 [system.cpu.fuPool.FUList5.opList12]
 349 type=OpDesc
 350 issueLat=1
 351 opClass=SimdFloatAlu
 352 opLat=1
 353
 354 [system.cpu.fuPool.FUList5.opList13]
 355 type=OpDesc
 356 issueLat=1
 357 opClass=SimdFloatCmp
 358 opLat=1
 359
 360 [system.cpu.fuPool.FUList5.opList14]
 361 type=OpDesc
 362 issueLat=1
 363 opClass=SimdFloatCvt
 364 opLat=1
 365
 366 [system.cpu.fuPool.FUList5.opList15]
 367 type=OpDesc
 368 issueLat=1
 369 opClass=SimdFloatDiv
 370 opLat=1
 371
 372 [system.cpu.fuPool.FUList5.opList16]
 373 type=OpDesc
 374 issueLat=1
 375 opClass=SimdFloatMisc
 376 opLat=1
 377
 378 [system.cpu.fuPool.FUList5.opList17]
 379 type=OpDesc
 380 issueLat=1
 381 opClass=SimdFloatMult
 382 opLat=1
 383
 384 [system.cpu.fuPool.FUList5.opList18]
 385 type=OpDesc
 386 issueLat=1
 387 opClass=SimdFloatMultAcc
 388 opLat=1
 389
 390 [system.cpu.fuPool.FUList5.opList19]
 391 type=OpDesc
 392 issueLat=1
 393 opClass=SimdFloatSqrt
 394 opLat=1
 395
 396 [system.cpu.fuPool.FUList6]
 397 type=FUDesc
 398 children=opList
 399 count=0
 400 opList=system.cpu.fuPool.FUList6.opList
 401
 402 [system.cpu.fuPool.FUList6.opList]
 403 type=OpDesc
 404 issueLat=1
 405 opClass=MemWrite
 406 opLat=1
 407
 408 [system.cpu.fuPool.FUList7]
 409 type=FUDesc
 410 children=opList0 opList1
 411 count=4
 412 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 413
 414 [system.cpu.fuPool.FUList7.opList0]
 415 type=OpDesc
 416 issueLat=1
 417 opClass=MemRead
 418 opLat=1
 419
 420 [system.cpu.fuPool.FUList7.opList1]
 421 type=OpDesc
 422 issueLat=1
 423 opClass=MemWrite
 424 opLat=1
 425
 426 [system.cpu.fuPool.FUList8]
 427 type=FUDesc
 428 children=opList
 429 count=1
 430 opList=system.cpu.fuPool.FUList8.opList
 431
 432 [system.cpu.fuPool.FUList8.opList]
 433 type=OpDesc
 434 issueLat=3
 435 opClass=IprAccess
 436 opLat=3
 437
 438 [system.cpu.icache]
 439 type=BaseCache
 440 children=tags
 441 addr_ranges=0:18446744073709551615
 442 assoc=2
 443 clk_domain=system.cpu_clk_domain
 444 forward_snoops=true
 445 hit_latency=2
 446 is_top_level=true
 447 max_miss_count=0
 448 mshrs=4
 449 prefetch_on_access=false
 450 prefetcher=Null
 451 response_latency=2
 452 size=131072
 453 system=system
 454 tags=system.cpu.icache.tags
 455 tgts_per_mshr=20
 456 two_queue=false
 457 write_buffers=8
 458 cpu_side=system.cpu.icache_port
 459 mem_side=system.cpu.toL2Bus.slave[0]
 460
 461 [system.cpu.icache.tags]
 462 type=LRU
 463 assoc=2
 464 block_size=64
 465 clk_domain=system.cpu_clk_domain
 466 hit_latency=2
 467 size=131072
 468
 469 [system.cpu.interrupts]
 470 type=AlphaInterrupts
 471
 472 [system.cpu.isa]
 473 type=AlphaISA
 474
 475 [system.cpu.itb]
 476 type=AlphaTLB
 477 size=48
 478
 479 [system.cpu.l2cache]
 480 type=BaseCache
 481 children=tags
 482 addr_ranges=0:18446744073709551615
 483 assoc=8
 484 clk_domain=system.cpu_clk_domain
 485 forward_snoops=true
 486 hit_latency=20
 487 is_top_level=false
 488 max_miss_count=0
 489 mshrs=20
 490 prefetch_on_access=false
 491 prefetcher=Null
 492 response_latency=20
 493 size=2097152
 494 system=system
 495 tags=system.cpu.l2cache.tags
 496 tgts_per_mshr=12
 497 two_queue=false
 498 write_buffers=8
 499 cpu_side=system.cpu.toL2Bus.master[0]
 500 mem_side=system.membus.slave[1]
 501
 502 [system.cpu.l2cache.tags]
 503 type=LRU
 504 assoc=8
 505 block_size=64
 506 clk_domain=system.cpu_clk_domain
 507 hit_latency=20
 508 size=2097152
 509
 510 [system.cpu.toL2Bus]
 511 type=CoherentBus
 512 clk_domain=system.cpu_clk_domain
 513 header_cycles=1
 514 system=system
 515 use_default_range=false
 516 width=32
 517 master=system.cpu.l2cache.cpu_side
 518 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 519
 520 [system.cpu.tracer]
 521 type=ExeTracer
 522
 523 [system.cpu.workload]
 524 type=LiveProcess
 525 cmd=bzip2 input.source 1
 526 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 527 egid=100
 528 env=
 529 errout=cerr
 530 euid=100
 531 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 532 gid=100
 533 input=cin
 534 max_stack_size=67108864
 535 output=cout
 536 pid=100
 537 ppid=99
 538 simpoint=0
 539 system=system
 540 uid=100
 541
 542 [system.cpu_clk_domain]
 543 type=SrcClockDomain
 544 clock=500
 545 voltage_domain=system.voltage_domain
 546
 547 [system.membus]
 548 type=CoherentBus
 549 clk_domain=system.clk_domain
 550 header_cycles=1
 551 system=system
 552 use_default_range=false
 553 width=8
 554 master=system.physmem.port
 555 slave=system.system_port system.cpu.l2cache.mem_side
 556
 557 [system.physmem]
 558 type=SimpleDRAM
 559 activation_limit=4
 560 addr_mapping=RaBaChCo
 561 banks_per_rank=8
 562 burst_length=8
 563 channels=1
 564 clk_domain=system.clk_domain
 565 conf_table_reported=true
 566 device_bus_width=8
 567 device_rowbuffer_size=1024
 568 devices_per_rank=8
 569 in_addr_map=true
 570 mem_sched_policy=frfcfs
 571 null=false
 572 page_policy=open
 573 range=0:134217727
 574 ranks_per_channel=2
 575 read_buffer_size=32
 576 static_backend_latency=10000
 577 static_frontend_latency=10000
 578 tBURST=5000
 579 tCL=13750
 580 tRCD=13750
 581 tREFI=7800000
 582 tRFC=300000
 583 tRP=13750
 584 tWTR=7500
 585 tXAW=40000
 586 write_buffer_size=32
 587 write_thresh_perc=70
 588 port=system.membus.master[0]
 589
 590 [system.voltage_domain]
 591 type=VoltageDomain
 592 voltage=1.000000
 593