2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.682192 # Number of seconds simulated
4 sim_ticks 682191807000 # Number of ticks simulated
5 final_tick 682191807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 139307 # Simulator instruction rate (inst/s)
8 host_op_rate 139307 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 54741914 # Simulator tick rate (ticks/s)
10 host_mem_usage 268504 # Number of bytes of host memory used
11 host_seconds 12461.96 # Real time elapsed on the host
12 sim_insts 1736043781 # Number of instructions simulated
13 sim_ops 1736043781 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 61696 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.data 125800064 # Number of bytes read from this memory
18 system.physmem.bytes_read::total 125861760 # Number of bytes read from this memory
19 system.physmem.bytes_inst_read::cpu.inst 61696 # Number of instructions bytes read from this memory
20 system.physmem.bytes_inst_read::total 61696 # Number of instructions bytes read from this memory
21 system.physmem.bytes_written::writebacks 65265984 # Number of bytes written to this memory
22 system.physmem.bytes_written::total 65265984 # Number of bytes written to this memory
23 system.physmem.num_reads::cpu.inst 964 # Number of read requests responded to by this memory
24 system.physmem.num_reads::cpu.data 1965626 # Number of read requests responded to by this memory
25 system.physmem.num_reads::total 1966590 # Number of read requests responded to by this memory
26 system.physmem.num_writes::writebacks 1019781 # Number of write requests responded to by this memory
27 system.physmem.num_writes::total 1019781 # Number of write requests responded to by this memory
28 system.physmem.bw_read::cpu.inst 90438 # Total read bandwidth from this memory (bytes/s)
29 system.physmem.bw_read::cpu.data 184405709 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::total 184496147 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_inst_read::cpu.inst 90438 # Instruction read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::total 90438 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_write::writebacks 95671017 # Write bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::total 95671017 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_total::writebacks 95671017 # Total bandwidth to/from this memory (bytes/s)
36 system.physmem.bw_total::cpu.inst 90438 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.data 184405709 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::total 280167164 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.readReqs 1966590 # Number of read requests accepted
40 system.physmem.writeReqs 1019781 # Number of write requests accepted
41 system.physmem.readBursts 1966590 # Number of DRAM read bursts, including those serviced by the write queue
42 system.physmem.writeBursts 1019781 # Number of DRAM write bursts, including those merged in the write queue
43 system.physmem.bytesReadDRAM 125780416 # Total number of bytes read from DRAM
44 system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue
45 system.physmem.bytesWritten 65264896 # Total number of bytes written to DRAM
46 system.physmem.bytesReadSys 125861760 # Total read bytes from the system interface side
47 system.physmem.bytesWrittenSys 65265984 # Total written bytes from the system interface side
48 system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue
49 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51 system.physmem.perBankRdBursts::0 118991 # Per bank write bursts
52 system.physmem.perBankRdBursts::1 114394 # Per bank write bursts
53 system.physmem.perBankRdBursts::2 116519 # Per bank write bursts
54 system.physmem.perBankRdBursts::3 118029 # Per bank write bursts
55 system.physmem.perBankRdBursts::4 118142 # Per bank write bursts
56 system.physmem.perBankRdBursts::5 117777 # Per bank write bursts
57 system.physmem.perBankRdBursts::6 120156 # Per bank write bursts
58 system.physmem.perBankRdBursts::7 124892 # Per bank write bursts
59 system.physmem.perBankRdBursts::8 127514 # Per bank write bursts
60 system.physmem.perBankRdBursts::9 130376 # Per bank write bursts
61 system.physmem.perBankRdBursts::10 129025 # Per bank write bursts
62 system.physmem.perBankRdBursts::11 130742 # Per bank write bursts
63 system.physmem.perBankRdBursts::12 126628 # Per bank write bursts
64 system.physmem.perBankRdBursts::13 125605 # Per bank write bursts
65 system.physmem.perBankRdBursts::14 122932 # Per bank write bursts
66 system.physmem.perBankRdBursts::15 123597 # Per bank write bursts
67 system.physmem.perBankWrBursts::0 61284 # Per bank write bursts
68 system.physmem.perBankWrBursts::1 61572 # Per bank write bursts
69 system.physmem.perBankWrBursts::2 60658 # Per bank write bursts
70 system.physmem.perBankWrBursts::3 61323 # Per bank write bursts
71 system.physmem.perBankWrBursts::4 61765 # Per bank write bursts
72 system.physmem.perBankWrBursts::5 63192 # Per bank write bursts
73 system.physmem.perBankWrBursts::6 64214 # Per bank write bursts
74 system.physmem.perBankWrBursts::7 65706 # Per bank write bursts
75 system.physmem.perBankWrBursts::8 65482 # Per bank write bursts
76 system.physmem.perBankWrBursts::9 65855 # Per bank write bursts
77 system.physmem.perBankWrBursts::10 65405 # Per bank write bursts
78 system.physmem.perBankWrBursts::11 65740 # Per bank write bursts
79 system.physmem.perBankWrBursts::12 64329 # Per bank write bursts
80 system.physmem.perBankWrBursts::13 64310 # Per bank write bursts
81 system.physmem.perBankWrBursts::14 64647 # Per bank write bursts
82 system.physmem.perBankWrBursts::15 64282 # Per bank write bursts
83 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85 system.physmem.totGap 682191684500 # Total gap between requests
86 system.physmem.readPktSize::0 0 # Read request sizes (log2)
87 system.physmem.readPktSize::1 0 # Read request sizes (log2)
88 system.physmem.readPktSize::2 0 # Read request sizes (log2)
89 system.physmem.readPktSize::3 0 # Read request sizes (log2)
90 system.physmem.readPktSize::4 0 # Read request sizes (log2)
91 system.physmem.readPktSize::5 0 # Read request sizes (log2)
92 system.physmem.readPktSize::6 1966590 # Read request sizes (log2)
93 system.physmem.writePktSize::0 0 # Write request sizes (log2)
94 system.physmem.writePktSize::1 0 # Write request sizes (log2)
95 system.physmem.writePktSize::2 0 # Write request sizes (log2)
96 system.physmem.writePktSize::3 0 # Write request sizes (log2)
97 system.physmem.writePktSize::4 0 # Write request sizes (log2)
98 system.physmem.writePktSize::5 0 # Write request sizes (log2)
99 system.physmem.writePktSize::6 1019781 # Write request sizes (log2)
100 system.physmem.rdQLenPdf::0 1642976 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::1 230548 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::2 69552 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::3 22230 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::15 23411 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::16 24830 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::17 31804 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::18 47471 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::19 54150 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::20 57221 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::21 58425 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::22 59086 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::23 59586 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::24 60134 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::25 64812 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::26 65271 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::27 65616 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::28 73465 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::29 64939 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::30 61899 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::31 60584 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::32 59687 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::33 17452 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::34 5357 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::35 1832 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::36 647 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::37 358 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::40 145 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196 system.physmem.bytesPerActivate::samples 1251998 # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::mean 113.111439 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::gmean 84.586325 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::stdev 150.844327 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::0-127 955672 76.33% 76.33% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::128-255 201584 16.10% 92.43% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::256-383 38062 3.04% 95.47% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::384-511 16101 1.29% 96.76% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::512-639 9606 0.77% 97.53% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::640-767 4835 0.39% 97.91% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::768-895 3234 0.26% 98.17% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::896-1023 2576 0.21% 98.38% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1024-1151 20328 1.62% 100.00% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::total 1251998 # Bytes accessed per row activation
210 system.physmem.rdPerTurnAround::samples 58888 # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::mean 33.373692 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::stdev 161.339848 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::0-1023 58850 99.94% 99.94% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::total 58888 # Reads before turning the bus around for writes
226 system.physmem.wrPerTurnAround::samples 58888 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::mean 17.317009 # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::gmean 17.233410 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::stdev 1.918536 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::16-17 34047 57.82% 57.82% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::18-19 20086 34.11% 91.93% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::20-21 4266 7.24% 99.17% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::22-23 290 0.49% 99.66% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-25 84 0.14% 99.80% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::26-27 30 0.05% 99.86% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::28-29 14 0.02% 99.88% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::30-31 5 0.01% 99.89% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::32-33 4 0.01% 99.89% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::34-35 3 0.01% 99.90% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::36-37 2 0.00% 99.90% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::38-39 12 0.02% 99.92% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::40-41 19 0.03% 99.96% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::42-43 9 0.02% 99.97% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::44-45 1 0.00% 99.97% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::46-47 4 0.01% 99.98% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::48-49 2 0.00% 99.98% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::50-51 1 0.00% 99.98% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::52-53 1 0.00% 99.99% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::54-55 1 0.00% 99.99% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::64-65 1 0.00% 99.99% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::78-79 1 0.00% 99.99% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::86-87 1 0.00% 99.99% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::104-105 1 0.00% 100.00% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::106-107 1 0.00% 100.00% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::total 58888 # Writes before turning the bus around for reads
258 system.physmem.totQLat 20653307250 # Total ticks spent queuing
259 system.physmem.totMemAccLat 80037239750 # Total ticks spent from burst creation until serviced by the DRAM
260 system.physmem.totBusLat 9826595000 # Total ticks spent in databus transfers
261 system.physmem.totBankLat 49557337500 # Total ticks spent accessing banks
262 system.physmem.avgQLat 10508.88 # Average queueing delay per DRAM burst
263 system.physmem.avgBankLat 25215.93 # Average bank access latency per DRAM burst
264 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
265 system.physmem.avgMemAccLat 40724.81 # Average memory access latency per DRAM burst
266 system.physmem.avgRdBW 184.38 # Average DRAM read bandwidth in MiByte/s
267 system.physmem.avgWrBW 95.67 # Average achieved write bandwidth in MiByte/s
268 system.physmem.avgRdBWSys 184.50 # Average system read bandwidth in MiByte/s
269 system.physmem.avgWrBWSys 95.67 # Average system write bandwidth in MiByte/s
270 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
271 system.physmem.busUtil 2.19 # Data bus utilization in percentage
272 system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads
273 system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes
274 system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
275 system.physmem.avgWrQLen 25.29 # Average write queue length when enqueuing
276 system.physmem.readRowHits 797879 # Number of row buffer hits during reads
277 system.physmem.writeRowHits 422825 # Number of row buffer hits during writes
278 system.physmem.readRowHitRate 40.60 # Row buffer hit rate for reads
279 system.physmem.writeRowHitRate 41.46 # Row buffer hit rate for writes
280 system.physmem.avgGap 228435.01 # Average gap between requests
281 system.physmem.pageHitRate 40.89 # Row buffer hit rate, read and write combined
282 system.physmem.prechargeAllPercent 7.23 # Percentage of time for which DRAM has all the banks in precharge state
283 system.membus.throughput 280167164 # Throughput (bytes/s)
284 system.membus.trans_dist::ReadReq 1191439 # Transaction distribution
285 system.membus.trans_dist::ReadResp 1191439 # Transaction distribution
286 system.membus.trans_dist::Writeback 1019781 # Transaction distribution
287 system.membus.trans_dist::ReadExReq 775151 # Transaction distribution
288 system.membus.trans_dist::ReadExResp 775151 # Transaction distribution
289 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952961 # Packet count per connected master and slave (bytes)
290 system.membus.pkt_count::total 4952961 # Packet count per connected master and slave (bytes)
291 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191127744 # Cumulative packet size per connected master and slave (bytes)
292 system.membus.tot_pkt_size::total 191127744 # Cumulative packet size per connected master and slave (bytes)
293 system.membus.data_through_bus 191127744 # Total data (bytes)
294 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
295 system.membus.reqLayer0.occupancy 11872683000 # Layer occupancy (ticks)
296 system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
297 system.membus.respLayer1.occupancy 18474077250 # Layer occupancy (ticks)
298 system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
299 system.cpu_clk_domain.clock 500 # Clock period in ticks
300 system.cpu.branchPred.lookups 381618384 # Number of BP lookups
301 system.cpu.branchPred.condPredicted 296575373 # Number of conditional branches predicted
302 system.cpu.branchPred.condIncorrect 16092188 # Number of conditional branches incorrect
303 system.cpu.branchPred.BTBLookups 262164042 # Number of BTB lookups
304 system.cpu.branchPred.BTBHits 259697812 # Number of BTB hits
305 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
306 system.cpu.branchPred.BTBHitPct 99.059280 # BTB Hit Percentage
307 system.cpu.branchPred.usedRAS 24705469 # Number of times the RAS was used to get a target.
308 system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions.
309 system.cpu.dtb.fetch_hits 0 # ITB hits
310 system.cpu.dtb.fetch_misses 0 # ITB misses
311 system.cpu.dtb.fetch_acv 0 # ITB acv
312 system.cpu.dtb.fetch_accesses 0 # ITB accesses
313 system.cpu.dtb.read_hits 613976008 # DTB read hits
314 system.cpu.dtb.read_misses 11261750 # DTB read misses
315 system.cpu.dtb.read_acv 0 # DTB read access violations
316 system.cpu.dtb.read_accesses 625237758 # DTB read accesses
317 system.cpu.dtb.write_hits 212363538 # DTB write hits
318 system.cpu.dtb.write_misses 7134748 # DTB write misses
319 system.cpu.dtb.write_acv 0 # DTB write access violations
320 system.cpu.dtb.write_accesses 219498286 # DTB write accesses
321 system.cpu.dtb.data_hits 826339546 # DTB hits
322 system.cpu.dtb.data_misses 18396498 # DTB misses
323 system.cpu.dtb.data_acv 0 # DTB access violations
324 system.cpu.dtb.data_accesses 844736044 # DTB accesses
325 system.cpu.itb.fetch_hits 391110222 # ITB hits
326 system.cpu.itb.fetch_misses 44 # ITB misses
327 system.cpu.itb.fetch_acv 0 # ITB acv
328 system.cpu.itb.fetch_accesses 391110266 # ITB accesses
329 system.cpu.itb.read_hits 0 # DTB read hits
330 system.cpu.itb.read_misses 0 # DTB read misses
331 system.cpu.itb.read_acv 0 # DTB read access violations
332 system.cpu.itb.read_accesses 0 # DTB read accesses
333 system.cpu.itb.write_hits 0 # DTB write hits
334 system.cpu.itb.write_misses 0 # DTB write misses
335 system.cpu.itb.write_acv 0 # DTB write access violations
336 system.cpu.itb.write_accesses 0 # DTB write accesses
337 system.cpu.itb.data_hits 0 # DTB hits
338 system.cpu.itb.data_misses 0 # DTB misses
339 system.cpu.itb.data_acv 0 # DTB access violations
340 system.cpu.itb.data_accesses 0 # DTB accesses
341 system.cpu.workload.num_syscalls 29 # Number of system calls
342 system.cpu.numCycles 1364383615 # number of cpu cycles simulated
343 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
344 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
345 system.cpu.fetch.icacheStallCycles 402585287 # Number of cycles fetch is stalled on an Icache miss
346 system.cpu.fetch.Insts 3161125101 # Number of instructions fetch has processed
347 system.cpu.fetch.Branches 381618384 # Number of branches that fetch encountered
348 system.cpu.fetch.predictedBranches 284403281 # Number of branches that fetch has predicted taken
349 system.cpu.fetch.Cycles 574536383 # Number of cycles fetch has run and was not squashing or blocked
350 system.cpu.fetch.SquashCycles 140665925 # Number of cycles fetch has spent squashing
351 system.cpu.fetch.BlockedCycles 188120516 # Number of cycles fetch has spent blocked
352 system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
353 system.cpu.fetch.PendingTrapStallCycles 1448 # Number of stall cycles due to pending traps
354 system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR
355 system.cpu.fetch.CacheLines 391110222 # Number of cache lines fetched
356 system.cpu.fetch.IcacheSquashes 8062763 # Number of outstanding Icache misses that were squashed
357 system.cpu.fetch.rateDist::samples 1282059246 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::mean 2.465662 # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.rateDist::stdev 3.145744 # Number of instructions fetched each cycle (Total)
360 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::0 707522863 55.19% 55.19% # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.rateDist::1 42675531 3.33% 58.52% # Number of instructions fetched each cycle (Total)
363 system.cpu.fetch.rateDist::2 21787283 1.70% 60.21% # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::3 39707555 3.10% 63.31% # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::4 129310443 10.09% 73.40% # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::5 61549431 4.80% 78.20% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::6 38571496 3.01% 81.21% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::7 28142716 2.20% 83.40% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::8 212791928 16.60% 100.00% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::total 1282059246 # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.branchRate 0.279700 # Number of branch fetches per cycle
375 system.cpu.fetch.rate 2.316889 # Number of inst fetches per cycle
376 system.cpu.decode.IdleCycles 434597074 # Number of cycles decode is idle
377 system.cpu.decode.BlockedCycles 169317553 # Number of cycles decode is blocked
378 system.cpu.decode.RunCycles 542454813 # Number of cycles decode is running
379 system.cpu.decode.UnblockCycles 18875119 # Number of cycles decode is unblocking
380 system.cpu.decode.SquashCycles 116814687 # Number of cycles decode is squashing
381 system.cpu.decode.BranchResolved 58354170 # Number of times decode resolved a branch
382 system.cpu.decode.BranchMispred 898 # Number of times decode detected a branch misprediction
383 system.cpu.decode.DecodedInsts 3088496267 # Number of instructions handled by decode
384 system.cpu.decode.SquashedInsts 2037 # Number of squashed instructions handled by decode
385 system.cpu.rename.SquashCycles 116814687 # Number of cycles rename is squashing
386 system.cpu.rename.IdleCycles 457547940 # Number of cycles rename is idle
387 system.cpu.rename.BlockCycles 113953082 # Number of cycles rename is blocking
388 system.cpu.rename.serializeStallCycles 6967 # count of cycles rename stalled for serializing inst
389 system.cpu.rename.RunCycles 535589228 # Number of cycles rename is running
390 system.cpu.rename.UnblockCycles 58147342 # Number of cycles rename is unblocking
391 system.cpu.rename.RenamedInsts 3006454755 # Number of instructions processed by rename
392 system.cpu.rename.ROBFullEvents 609106 # Number of times rename has blocked due to ROB full
393 system.cpu.rename.IQFullEvents 1833248 # Number of times rename has blocked due to IQ full
394 system.cpu.rename.LSQFullEvents 51828481 # Number of times rename has blocked due to LSQ full
395 system.cpu.rename.RenamedOperands 2247677853 # Number of destination operands rename has renamed
396 system.cpu.rename.RenameLookups 3898974365 # Number of register rename lookups that rename has made
397 system.cpu.rename.int_rename_lookups 3898830865 # Number of integer rename lookups
398 system.cpu.rename.fp_rename_lookups 143499 # Number of floating rename lookups
399 system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
400 system.cpu.rename.UndoneMaps 871474890 # Number of HB maps that are undone due to squashing
401 system.cpu.rename.serializingInsts 178 # count of serializing insts renamed
402 system.cpu.rename.tempSerializingInsts 177 # count of temporary serializing insts renamed
403 system.cpu.rename.skidInsts 123676155 # count of insts added to the skid buffer
404 system.cpu.memDep0.insertedLoads 679702242 # Number of loads inserted to the mem dependence unit.
405 system.cpu.memDep0.insertedStores 255475560 # Number of stores inserted to the mem dependence unit.
406 system.cpu.memDep0.conflictingLoads 67614908 # Number of conflicting loads.
407 system.cpu.memDep0.conflictingStores 37053481 # Number of conflicting stores.
408 system.cpu.iq.iqInstsAdded 2724914461 # Number of instructions added to the IQ (excludes non-spec)
409 system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ
410 system.cpu.iq.iqInstsIssued 2509610552 # Number of instructions issued
411 system.cpu.iq.iqSquashedInstsIssued 3196332 # Number of squashed instructions issued
412 system.cpu.iq.iqSquashedInstsExamined 979670705 # Number of squashed instructions iterated over during squash; mainly for profiling
413 system.cpu.iq.iqSquashedOperandsExamined 416123894 # Number of squashed operands that are examined and possibly removed from graph
414 system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed
415 system.cpu.iq.issued_per_cycle::samples 1282059246 # Number of insts issued each cycle
416 system.cpu.iq.issued_per_cycle::mean 1.957484 # Number of insts issued each cycle
417 system.cpu.iq.issued_per_cycle::stdev 1.971278 # Number of insts issued each cycle
418 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
419 system.cpu.iq.issued_per_cycle::0 440049739 34.32% 34.32% # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::1 203670606 15.89% 50.21% # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::2 185671301 14.48% 64.69% # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::3 153363283 11.96% 76.65% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::4 133052268 10.38% 87.03% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::5 80767651 6.30% 93.33% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::6 65047769 5.07% 98.41% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::7 15319478 1.19% 99.60% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::8 5117151 0.40% 100.00% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::total 1282059246 # Number of insts issued each cycle
432 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
433 system.cpu.iq.fu_full::IntAlu 2188252 11.81% 11.81% # attempts to use FU when none available
434 system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available
435 system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available
436 system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available
437 system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available
438 system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available
439 system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available
441 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available
462 system.cpu.iq.fu_full::MemRead 11925862 64.39% 76.20% # attempts to use FU when none available
463 system.cpu.iq.fu_full::MemWrite 4407339 23.80% 100.00% # attempts to use FU when none available
464 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
465 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
466 system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
467 system.cpu.iq.FU_type_0::IntAlu 1643881644 65.50% 65.50% # Type of FU issued
468 system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.50% # Type of FU issued
469 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
470 system.cpu.iq.FU_type_0::FloatAdd 265 0.00% 65.50% # Type of FU issued
471 system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
472 system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.50% # Type of FU issued
473 system.cpu.iq.FU_type_0::FloatMult 23 0.00% 65.50% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued
475 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
496 system.cpu.iq.FU_type_0::MemRead 641614566 25.57% 91.07% # Type of FU issued
497 system.cpu.iq.FU_type_0::MemWrite 224113754 8.93% 100.00% # Type of FU issued
498 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
499 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
500 system.cpu.iq.FU_type_0::total 2509610552 # Type of FU issued
501 system.cpu.iq.rate 1.839373 # Inst issue rate
502 system.cpu.iq.fu_busy_cnt 18521453 # FU busy when requested
503 system.cpu.iq.fu_busy_rate 0.007380 # FU busy rate (busy events/executed inst)
504 system.cpu.iq.int_inst_queue_reads 6321098058 # Number of integer instruction queue reads
505 system.cpu.iq.int_inst_queue_writes 3703474382 # Number of integer instruction queue writes
506 system.cpu.iq.int_inst_queue_wakeup_accesses 2413201675 # Number of integer instruction queue wakeup accesses
507 system.cpu.iq.fp_inst_queue_reads 1900077 # Number of floating instruction queue reads
508 system.cpu.iq.fp_inst_queue_writes 1218284 # Number of floating instruction queue writes
509 system.cpu.iq.fp_inst_queue_wakeup_accesses 852187 # Number of floating instruction queue wakeup accesses
510 system.cpu.iq.int_alu_accesses 2527192648 # Number of integer alu accesses
511 system.cpu.iq.fp_alu_accesses 939357 # Number of floating point alu accesses
512 system.cpu.iew.lsq.thread0.forwLoads 62588107 # Number of loads that had data forwarded from stores
513 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
514 system.cpu.iew.lsq.thread0.squashedLoads 235106579 # Number of loads squashed
515 system.cpu.iew.lsq.thread0.ignoredResponses 263309 # Number of memory responses ignored because the instruction is squashed
516 system.cpu.iew.lsq.thread0.memOrderViolation 109146 # Number of memory ordering violations
517 system.cpu.iew.lsq.thread0.squashedStores 94747058 # Number of stores squashed
518 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
519 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
520 system.cpu.iew.lsq.thread0.rescheduledLoads 184 # Number of loads that were rescheduled
521 system.cpu.iew.lsq.thread0.cacheBlocked 1530387 # Number of times an access to memory failed due to the cache being blocked
522 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
523 system.cpu.iew.iewSquashCycles 116814687 # Number of cycles IEW is squashing
524 system.cpu.iew.iewBlockCycles 54760955 # Number of cycles IEW is blocking
525 system.cpu.iew.iewUnblockCycles 1302145 # Number of cycles IEW is unblocking
526 system.cpu.iew.iewDispatchedInsts 2867095326 # Number of instructions dispatched to IQ
527 system.cpu.iew.iewDispSquashedInsts 8936600 # Number of squashed instructions skipped by dispatch
528 system.cpu.iew.iewDispLoadInsts 679702242 # Number of dispatched load instructions
529 system.cpu.iew.iewDispStoreInsts 255475560 # Number of dispatched store instructions
530 system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions
531 system.cpu.iew.iewIQFullEvents 285836 # Number of times the IQ has become full, causing a stall
532 system.cpu.iew.iewLSQFullEvents 18373 # Number of times the LSQ has become full, causing a stall
533 system.cpu.iew.memOrderViolationEvents 109146 # Number of memory order violations
534 system.cpu.iew.predictedTakenIncorrect 10363389 # Number of branches that were predicted taken incorrectly
535 system.cpu.iew.predictedNotTakenIncorrect 8561306 # Number of branches that were predicted not taken incorrectly
536 system.cpu.iew.branchMispredicts 18924695 # Number of branch mispredicts detected at execute
537 system.cpu.iew.iewExecutedInsts 2462265598 # Number of executed instructions
538 system.cpu.iew.iewExecLoadInsts 625238282 # Number of load instructions executed
539 system.cpu.iew.iewExecSquashedInsts 47344954 # Number of squashed instructions skipped in execute
540 system.cpu.iew.exec_swp 0 # number of swp insts executed
541 system.cpu.iew.exec_nop 142180734 # number of nop insts executed
542 system.cpu.iew.exec_refs 844736593 # number of memory reference insts executed
543 system.cpu.iew.exec_branches 300891924 # Number of branches executed
544 system.cpu.iew.exec_stores 219498311 # Number of stores executed
545 system.cpu.iew.exec_rate 1.804673 # Inst execution rate
546 system.cpu.iew.wb_sent 2442007403 # cumulative count of insts sent to commit
547 system.cpu.iew.wb_count 2414053862 # cumulative count of insts written-back
548 system.cpu.iew.wb_producers 1388335082 # num instructions producing a value
549 system.cpu.iew.wb_consumers 1764294016 # num instructions consuming a value
550 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
551 system.cpu.iew.wb_rate 1.769337 # insts written-back per cycle
552 system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back
553 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
554 system.cpu.commit.commitSquashedInsts 826637792 # The number of squashed insts skipped by commit
555 system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
556 system.cpu.commit.branchMispredicts 16091391 # The number of times a branch was mispredicted
557 system.cpu.commit.committed_per_cycle::samples 1165244559 # Number of insts commited each cycle
558 system.cpu.commit.committed_per_cycle::mean 1.561715 # Number of insts commited each cycle
559 system.cpu.commit.committed_per_cycle::stdev 2.500982 # Number of insts commited each cycle
560 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
561 system.cpu.commit.committed_per_cycle::0 651170378 55.88% 55.88% # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::1 175014835 15.02% 70.90% # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::2 86149099 7.39% 78.30% # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::3 53527990 4.59% 82.89% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::4 34710349 2.98% 85.87% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::5 26102733 2.24% 88.11% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::6 21568948 1.85% 89.96% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::7 22887442 1.96% 91.92% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::8 94112785 8.08% 100.00% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::total 1165244559 # Number of insts commited each cycle
574 system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
575 system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
576 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
577 system.cpu.commit.refs 605324165 # Number of memory references committed
578 system.cpu.commit.loads 444595663 # Number of loads committed
579 system.cpu.commit.membars 0 # Number of memory barriers committed
580 system.cpu.commit.branches 214632552 # Number of branches committed
581 system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
582 system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
583 system.cpu.commit.function_calls 16767440 # Number of function calls committed.
584 system.cpu.commit.bw_lim_events 94112785 # number cycles where commit BW limit reached
585 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
586 system.cpu.rob.rob_reads 3631770492 # The number of ROB reads
587 system.cpu.rob.rob_writes 5409749589 # The number of ROB writes
588 system.cpu.timesIdled 953701 # Number of times that the entire CPU went into an idle state and unscheduled itself
589 system.cpu.idleCycles 82324369 # Total number of cycles that the CPU has spent unscheduled due to idling
590 system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
591 system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
592 system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
593 system.cpu.cpi 0.785915 # CPI: Cycles Per Instruction
594 system.cpu.cpi_total 0.785915 # CPI: Total CPI of All Threads
595 system.cpu.ipc 1.272402 # IPC: Instructions Per Cycle
596 system.cpu.ipc_total 1.272402 # IPC: Total IPC of All Threads
597 system.cpu.int_regfile_reads 3318200326 # number of integer regfile reads
598 system.cpu.int_regfile_writes 1932098427 # number of integer regfile writes
599 system.cpu.fp_regfile_reads 30699 # number of floating regfile reads
600 system.cpu.fp_regfile_writes 520 # number of floating regfile writes
601 system.cpu.misc_regfile_reads 25 # number of misc regfile reads
602 system.cpu.misc_regfile_writes 1 # number of misc regfile writes
603 system.cpu.toL2Bus.throughput 1210780745 # Throughput (bytes/s)
604 system.cpu.toL2Bus.trans_dist::ReadReq 7297678 # Transaction distribution
605 system.cpu.toL2Bus.trans_dist::ReadResp 7297678 # Transaction distribution
606 system.cpu.toL2Bus.trans_dist::Writeback 3724768 # Transaction distribution
607 system.cpu.toL2Bus.trans_dist::ReadExReq 1883565 # Transaction distribution
608 system.cpu.toL2Bus.trans_dist::ReadExResp 1883565 # Transaction distribution
609 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928 # Packet count per connected master and slave (bytes)
610 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085326 # Packet count per connected master and slave (bytes)
611 system.cpu.toL2Bus.pkt_count::total 22087254 # Packet count per connected master and slave (bytes)
612 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61696 # Cumulative packet size per connected master and slave (bytes)
613 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825923008 # Cumulative packet size per connected master and slave (bytes)
614 system.cpu.toL2Bus.tot_pkt_size::total 825984704 # Cumulative packet size per connected master and slave (bytes)
615 system.cpu.toL2Bus.data_through_bus 825984704 # Total data (bytes)
616 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
617 system.cpu.toL2Bus.reqLayer0.occupancy 10177843430 # Layer occupancy (ticks)
618 system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
619 system.cpu.toL2Bus.respLayer0.occupancy 1605500 # Layer occupancy (ticks)
620 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
621 system.cpu.toL2Bus.respLayer1.occupancy 14065476499 # Layer occupancy (ticks)
622 system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
623 system.cpu.icache.tags.replacements 1 # number of replacements
624 system.cpu.icache.tags.tagsinuse 773.695817 # Cycle average of tags in use
625 system.cpu.icache.tags.total_refs 391108717 # Total number of references to valid blocks.
626 system.cpu.icache.tags.sampled_refs 964 # Sample count of references to valid blocks.
627 system.cpu.icache.tags.avg_refs 405714.436722 # Average number of references to valid blocks.
628 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
629 system.cpu.icache.tags.occ_blocks::cpu.inst 773.695817 # Average occupied blocks per requestor
630 system.cpu.icache.tags.occ_percent::cpu.inst 0.377781 # Average percentage of cache occupancy
631 system.cpu.icache.tags.occ_percent::total 0.377781 # Average percentage of cache occupancy
632 system.cpu.icache.tags.occ_task_id_blocks::1024 963 # Occupied blocks per task id
633 system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
634 system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id
635 system.cpu.icache.tags.occ_task_id_percent::1024 0.470215 # Percentage of cache occupancy per task id
636 system.cpu.icache.tags.tag_accesses 782221404 # Number of tag accesses
637 system.cpu.icache.tags.data_accesses 782221404 # Number of data accesses
638 system.cpu.icache.ReadReq_hits::cpu.inst 391108717 # number of ReadReq hits
639 system.cpu.icache.ReadReq_hits::total 391108717 # number of ReadReq hits
640 system.cpu.icache.demand_hits::cpu.inst 391108717 # number of demand (read+write) hits
641 system.cpu.icache.demand_hits::total 391108717 # number of demand (read+write) hits
642 system.cpu.icache.overall_hits::cpu.inst 391108717 # number of overall hits
643 system.cpu.icache.overall_hits::total 391108717 # number of overall hits
644 system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses
645 system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses
646 system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses
647 system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses
648 system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses
649 system.cpu.icache.overall_misses::total 1503 # number of overall misses
650 system.cpu.icache.ReadReq_miss_latency::cpu.inst 108284500 # number of ReadReq miss cycles
651 system.cpu.icache.ReadReq_miss_latency::total 108284500 # number of ReadReq miss cycles
652 system.cpu.icache.demand_miss_latency::cpu.inst 108284500 # number of demand (read+write) miss cycles
653 system.cpu.icache.demand_miss_latency::total 108284500 # number of demand (read+write) miss cycles
654 system.cpu.icache.overall_miss_latency::cpu.inst 108284500 # number of overall miss cycles
655 system.cpu.icache.overall_miss_latency::total 108284500 # number of overall miss cycles
656 system.cpu.icache.ReadReq_accesses::cpu.inst 391110220 # number of ReadReq accesses(hits+misses)
657 system.cpu.icache.ReadReq_accesses::total 391110220 # number of ReadReq accesses(hits+misses)
658 system.cpu.icache.demand_accesses::cpu.inst 391110220 # number of demand (read+write) accesses
659 system.cpu.icache.demand_accesses::total 391110220 # number of demand (read+write) accesses
660 system.cpu.icache.overall_accesses::cpu.inst 391110220 # number of overall (read+write) accesses
661 system.cpu.icache.overall_accesses::total 391110220 # number of overall (read+write) accesses
662 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
663 system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
664 system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
665 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
666 system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
667 system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
668 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516 # average ReadReq miss latency
669 system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516 # average ReadReq miss latency
670 system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency
671 system.cpu.icache.demand_avg_miss_latency::total 72045.575516 # average overall miss latency
672 system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency
673 system.cpu.icache.overall_avg_miss_latency::total 72045.575516 # average overall miss latency
674 system.cpu.icache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked
675 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
676 system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
677 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
678 system.cpu.icache.avg_blocked_cycles::no_mshrs 69.800000 # average number of cycles each access was blocked
679 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
680 system.cpu.icache.fast_writes 0 # number of fast writes performed
681 system.cpu.icache.cache_copies 0 # number of cache copies performed
682 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 539 # number of ReadReq MSHR hits
683 system.cpu.icache.ReadReq_mshr_hits::total 539 # number of ReadReq MSHR hits
684 system.cpu.icache.demand_mshr_hits::cpu.inst 539 # number of demand (read+write) MSHR hits
685 system.cpu.icache.demand_mshr_hits::total 539 # number of demand (read+write) MSHR hits
686 system.cpu.icache.overall_mshr_hits::cpu.inst 539 # number of overall MSHR hits
687 system.cpu.icache.overall_mshr_hits::total 539 # number of overall MSHR hits
688 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses
689 system.cpu.icache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses
690 system.cpu.icache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses
691 system.cpu.icache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses
692 system.cpu.icache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses
693 system.cpu.icache.overall_mshr_misses::total 964 # number of overall MSHR misses
694 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75722000 # number of ReadReq MSHR miss cycles
695 system.cpu.icache.ReadReq_mshr_miss_latency::total 75722000 # number of ReadReq MSHR miss cycles
696 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75722000 # number of demand (read+write) MSHR miss cycles
697 system.cpu.icache.demand_mshr_miss_latency::total 75722000 # number of demand (read+write) MSHR miss cycles
698 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75722000 # number of overall MSHR miss cycles
699 system.cpu.icache.overall_mshr_miss_latency::total 75722000 # number of overall MSHR miss cycles
700 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
701 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
702 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
703 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
704 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
705 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
706 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531 # average ReadReq mshr miss latency
707 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531 # average ReadReq mshr miss latency
708 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency
709 system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency
710 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency
711 system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency
712 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
713 system.cpu.l2cache.tags.replacements 1933885 # number of replacements
714 system.cpu.l2cache.tags.tagsinuse 31421.269549 # Cycle average of tags in use
715 system.cpu.l2cache.tags.total_refs 9058254 # Total number of references to valid blocks.
716 system.cpu.l2cache.tags.sampled_refs 1963664 # Sample count of references to valid blocks.
717 system.cpu.l2cache.tags.avg_refs 4.612935 # Average number of references to valid blocks.
718 system.cpu.l2cache.tags.warmup_cycle 28359986250 # Cycle when the warmup percentage was hit.
719 system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791 # Average occupied blocks per requestor
720 system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.815575 # Average occupied blocks per requestor
721 system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182 # Average occupied blocks per requestor
722 system.cpu.l2cache.tags.occ_percent::writebacks 0.444701 # Average percentage of cache occupancy
723 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000818 # Average percentage of cache occupancy
724 system.cpu.l2cache.tags.occ_percent::cpu.data 0.513382 # Average percentage of cache occupancy
725 system.cpu.l2cache.tags.occ_percent::total 0.958901 # Average percentage of cache occupancy
726 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29779 # Occupied blocks per task id
727 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
728 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id
729 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id
730 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17299 # Occupied blocks per task id
731 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10767 # Occupied blocks per task id
732 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908783 # Percentage of cache occupancy per task id
733 system.cpu.l2cache.tags.tag_accesses 107095317 # Number of tag accesses
734 system.cpu.l2cache.tags.data_accesses 107095317 # Number of data accesses
735 system.cpu.l2cache.ReadReq_hits::cpu.data 6106239 # number of ReadReq hits
736 system.cpu.l2cache.ReadReq_hits::total 6106239 # number of ReadReq hits
737 system.cpu.l2cache.Writeback_hits::writebacks 3724768 # number of Writeback hits
738 system.cpu.l2cache.Writeback_hits::total 3724768 # number of Writeback hits
739 system.cpu.l2cache.ReadExReq_hits::cpu.data 1108414 # number of ReadExReq hits
740 system.cpu.l2cache.ReadExReq_hits::total 1108414 # number of ReadExReq hits
741 system.cpu.l2cache.demand_hits::cpu.data 7214653 # number of demand (read+write) hits
742 system.cpu.l2cache.demand_hits::total 7214653 # number of demand (read+write) hits
743 system.cpu.l2cache.overall_hits::cpu.data 7214653 # number of overall hits
744 system.cpu.l2cache.overall_hits::total 7214653 # number of overall hits
745 system.cpu.l2cache.ReadReq_misses::cpu.inst 964 # number of ReadReq misses
746 system.cpu.l2cache.ReadReq_misses::cpu.data 1190475 # number of ReadReq misses
747 system.cpu.l2cache.ReadReq_misses::total 1191439 # number of ReadReq misses
748 system.cpu.l2cache.ReadExReq_misses::cpu.data 775151 # number of ReadExReq misses
749 system.cpu.l2cache.ReadExReq_misses::total 775151 # number of ReadExReq misses
750 system.cpu.l2cache.demand_misses::cpu.inst 964 # number of demand (read+write) misses
751 system.cpu.l2cache.demand_misses::cpu.data 1965626 # number of demand (read+write) misses
752 system.cpu.l2cache.demand_misses::total 1966590 # number of demand (read+write) misses
753 system.cpu.l2cache.overall_misses::cpu.inst 964 # number of overall misses
754 system.cpu.l2cache.overall_misses::cpu.data 1965626 # number of overall misses
755 system.cpu.l2cache.overall_misses::total 1966590 # number of overall misses
756 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74752000 # number of ReadReq miss cycles
757 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 99906666750 # number of ReadReq miss cycles
758 system.cpu.l2cache.ReadReq_miss_latency::total 99981418750 # number of ReadReq miss cycles
759 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65179640000 # number of ReadExReq miss cycles
760 system.cpu.l2cache.ReadExReq_miss_latency::total 65179640000 # number of ReadExReq miss cycles
761 system.cpu.l2cache.demand_miss_latency::cpu.inst 74752000 # number of demand (read+write) miss cycles
762 system.cpu.l2cache.demand_miss_latency::cpu.data 165086306750 # number of demand (read+write) miss cycles
763 system.cpu.l2cache.demand_miss_latency::total 165161058750 # number of demand (read+write) miss cycles
764 system.cpu.l2cache.overall_miss_latency::cpu.inst 74752000 # number of overall miss cycles
765 system.cpu.l2cache.overall_miss_latency::cpu.data 165086306750 # number of overall miss cycles
766 system.cpu.l2cache.overall_miss_latency::total 165161058750 # number of overall miss cycles
767 system.cpu.l2cache.ReadReq_accesses::cpu.inst 964 # number of ReadReq accesses(hits+misses)
768 system.cpu.l2cache.ReadReq_accesses::cpu.data 7296714 # number of ReadReq accesses(hits+misses)
769 system.cpu.l2cache.ReadReq_accesses::total 7297678 # number of ReadReq accesses(hits+misses)
770 system.cpu.l2cache.Writeback_accesses::writebacks 3724768 # number of Writeback accesses(hits+misses)
771 system.cpu.l2cache.Writeback_accesses::total 3724768 # number of Writeback accesses(hits+misses)
772 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883565 # number of ReadExReq accesses(hits+misses)
773 system.cpu.l2cache.ReadExReq_accesses::total 1883565 # number of ReadExReq accesses(hits+misses)
774 system.cpu.l2cache.demand_accesses::cpu.inst 964 # number of demand (read+write) accesses
775 system.cpu.l2cache.demand_accesses::cpu.data 9180279 # number of demand (read+write) accesses
776 system.cpu.l2cache.demand_accesses::total 9181243 # number of demand (read+write) accesses
777 system.cpu.l2cache.overall_accesses::cpu.inst 964 # number of overall (read+write) accesses
778 system.cpu.l2cache.overall_accesses::cpu.data 9180279 # number of overall (read+write) accesses
779 system.cpu.l2cache.overall_accesses::total 9181243 # number of overall (read+write) accesses
780 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
781 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163152 # miss rate for ReadReq accesses
782 system.cpu.l2cache.ReadReq_miss_rate::total 0.163263 # miss rate for ReadReq accesses
783 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411534 # miss rate for ReadExReq accesses
784 system.cpu.l2cache.ReadExReq_miss_rate::total 0.411534 # miss rate for ReadExReq accesses
785 system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
786 system.cpu.l2cache.demand_miss_rate::cpu.data 0.214114 # miss rate for demand accesses
787 system.cpu.l2cache.demand_miss_rate::total 0.214196 # miss rate for demand accesses
788 system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
789 system.cpu.l2cache.overall_miss_rate::cpu.data 0.214114 # miss rate for overall accesses
790 system.cpu.l2cache.overall_miss_rate::total 0.214196 # miss rate for overall accesses
791 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77543.568465 # average ReadReq miss latency
792 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83921.683992 # average ReadReq miss latency
793 system.cpu.l2cache.ReadReq_avg_miss_latency::total 83916.523423 # average ReadReq miss latency
794 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84086.378009 # average ReadExReq miss latency
795 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84086.378009 # average ReadExReq miss latency
796 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency
797 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency
798 system.cpu.l2cache.demand_avg_miss_latency::total 83983.473296 # average overall miss latency
799 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency
800 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency
801 system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296 # average overall miss latency
802 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
803 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
804 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
805 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
806 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
807 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
808 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
809 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
810 system.cpu.l2cache.writebacks::writebacks 1019781 # number of writebacks
811 system.cpu.l2cache.writebacks::total 1019781 # number of writebacks
812 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses
813 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190475 # number of ReadReq MSHR misses
814 system.cpu.l2cache.ReadReq_mshr_misses::total 1191439 # number of ReadReq MSHR misses
815 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775151 # number of ReadExReq MSHR misses
816 system.cpu.l2cache.ReadExReq_mshr_misses::total 775151 # number of ReadExReq MSHR misses
817 system.cpu.l2cache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses
818 system.cpu.l2cache.demand_mshr_misses::cpu.data 1965626 # number of demand (read+write) MSHR misses
819 system.cpu.l2cache.demand_mshr_misses::total 1966590 # number of demand (read+write) MSHR misses
820 system.cpu.l2cache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses
821 system.cpu.l2cache.overall_mshr_misses::cpu.data 1965626 # number of overall MSHR misses
822 system.cpu.l2cache.overall_mshr_misses::total 1966590 # number of overall MSHR misses
823 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62625000 # number of ReadReq MSHR miss cycles
824 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84983280750 # number of ReadReq MSHR miss cycles
825 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85045905750 # number of ReadReq MSHR miss cycles
826 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55444498500 # number of ReadExReq MSHR miss cycles
827 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55444498500 # number of ReadExReq MSHR miss cycles
828 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62625000 # number of demand (read+write) MSHR miss cycles
829 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250 # number of demand (read+write) MSHR miss cycles
830 system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250 # number of demand (read+write) MSHR miss cycles
831 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62625000 # number of overall MSHR miss cycles
832 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250 # number of overall MSHR miss cycles
833 system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250 # number of overall MSHR miss cycles
834 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
835 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163152 # mshr miss rate for ReadReq accesses
836 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163263 # mshr miss rate for ReadReq accesses
837 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses
838 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses
839 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
840 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for demand accesses
841 system.cpu.l2cache.demand_mshr_miss_rate::total 0.214196 # mshr miss rate for demand accesses
842 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
843 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for overall accesses
844 system.cpu.l2cache.overall_mshr_miss_rate::total 0.214196 # mshr miss rate for overall accesses
845 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946 # average ReadReq mshr miss latency
846 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216 # average ReadReq mshr miss latency
847 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869 # average ReadReq mshr miss latency
848 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090 # average ReadExReq mshr miss latency
849 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090 # average ReadExReq mshr miss latency
850 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency
851 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency
852 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency
853 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency
854 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency
855 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency
856 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
857 system.cpu.dcache.tags.replacements 9176183 # number of replacements
858 system.cpu.dcache.tags.tagsinuse 4087.522150 # Cycle average of tags in use
859 system.cpu.dcache.tags.total_refs 694277633 # Total number of references to valid blocks.
860 system.cpu.dcache.tags.sampled_refs 9180279 # Sample count of references to valid blocks.
861 system.cpu.dcache.tags.avg_refs 75.627073 # Average number of references to valid blocks.
862 system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit.
863 system.cpu.dcache.tags.occ_blocks::cpu.data 4087.522150 # Average occupied blocks per requestor
864 system.cpu.dcache.tags.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy
865 system.cpu.dcache.tags.occ_percent::total 0.997930 # Average percentage of cache occupancy
866 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
867 system.cpu.dcache.tags.age_task_id_blocks_1024::0 705 # Occupied blocks per task id
868 system.cpu.dcache.tags.age_task_id_blocks_1024::1 2966 # Occupied blocks per task id
869 system.cpu.dcache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id
870 system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
871 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
872 system.cpu.dcache.tags.tag_accesses 1430905565 # Number of tag accesses
873 system.cpu.dcache.tags.data_accesses 1430905565 # Number of data accesses
874 system.cpu.dcache.ReadReq_hits::cpu.data 538740047 # number of ReadReq hits
875 system.cpu.dcache.ReadReq_hits::total 538740047 # number of ReadReq hits
876 system.cpu.dcache.WriteReq_hits::cpu.data 155537583 # number of WriteReq hits
877 system.cpu.dcache.WriteReq_hits::total 155537583 # number of WriteReq hits
878 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits
879 system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits
880 system.cpu.dcache.demand_hits::cpu.data 694277630 # number of demand (read+write) hits
881 system.cpu.dcache.demand_hits::total 694277630 # number of demand (read+write) hits
882 system.cpu.dcache.overall_hits::cpu.data 694277630 # number of overall hits
883 system.cpu.dcache.overall_hits::total 694277630 # number of overall hits
884 system.cpu.dcache.ReadReq_misses::cpu.data 11394090 # number of ReadReq misses
885 system.cpu.dcache.ReadReq_misses::total 11394090 # number of ReadReq misses
886 system.cpu.dcache.WriteReq_misses::cpu.data 5190919 # number of WriteReq misses
887 system.cpu.dcache.WriteReq_misses::total 5190919 # number of WriteReq misses
888 system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
889 system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
890 system.cpu.dcache.demand_misses::cpu.data 16585009 # number of demand (read+write) misses
891 system.cpu.dcache.demand_misses::total 16585009 # number of demand (read+write) misses
892 system.cpu.dcache.overall_misses::cpu.data 16585009 # number of overall misses
893 system.cpu.dcache.overall_misses::total 16585009 # number of overall misses
894 system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499 # number of ReadReq miss cycles
895 system.cpu.dcache.ReadReq_miss_latency::total 335805939499 # number of ReadReq miss cycles
896 system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439 # number of WriteReq miss cycles
897 system.cpu.dcache.WriteReq_miss_latency::total 289123962439 # number of WriteReq miss cycles
898 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201500 # number of LoadLockedReq miss cycles
899 system.cpu.dcache.LoadLockedReq_miss_latency::total 201500 # number of LoadLockedReq miss cycles
900 system.cpu.dcache.demand_miss_latency::cpu.data 624929901938 # number of demand (read+write) miss cycles
901 system.cpu.dcache.demand_miss_latency::total 624929901938 # number of demand (read+write) miss cycles
902 system.cpu.dcache.overall_miss_latency::cpu.data 624929901938 # number of overall miss cycles
903 system.cpu.dcache.overall_miss_latency::total 624929901938 # number of overall miss cycles
904 system.cpu.dcache.ReadReq_accesses::cpu.data 550134137 # number of ReadReq accesses(hits+misses)
905 system.cpu.dcache.ReadReq_accesses::total 550134137 # number of ReadReq accesses(hits+misses)
906 system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
907 system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
908 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
909 system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
910 system.cpu.dcache.demand_accesses::cpu.data 710862639 # number of demand (read+write) accesses
911 system.cpu.dcache.demand_accesses::total 710862639 # number of demand (read+write) accesses
912 system.cpu.dcache.overall_accesses::cpu.data 710862639 # number of overall (read+write) accesses
913 system.cpu.dcache.overall_accesses::total 710862639 # number of overall (read+write) accesses
914 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020711 # miss rate for ReadReq accesses
915 system.cpu.dcache.ReadReq_miss_rate::total 0.020711 # miss rate for ReadReq accesses
916 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032296 # miss rate for WriteReq accesses
917 system.cpu.dcache.WriteReq_miss_rate::total 0.032296 # miss rate for WriteReq accesses
918 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses
919 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses
920 system.cpu.dcache.demand_miss_rate::cpu.data 0.023331 # miss rate for demand accesses
921 system.cpu.dcache.demand_miss_rate::total 0.023331 # miss rate for demand accesses
922 system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses
923 system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses
924 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234 # average ReadReq miss latency
925 system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234 # average ReadReq miss latency
926 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048 # average WriteReq miss latency
927 system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048 # average WriteReq miss latency
928 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 201500 # average LoadLockedReq miss latency
929 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 201500 # average LoadLockedReq miss latency
930 system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency
931 system.cpu.dcache.demand_avg_miss_latency::total 37680.407767 # average overall miss latency
932 system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency
933 system.cpu.dcache.overall_avg_miss_latency::total 37680.407767 # average overall miss latency
934 system.cpu.dcache.blocked_cycles::no_mshrs 11880802 # number of cycles access was blocked
935 system.cpu.dcache.blocked_cycles::no_targets 8587513 # number of cycles access was blocked
936 system.cpu.dcache.blocked::no_mshrs 745209 # number of cycles access was blocked
937 system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked
938 system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.942913 # average number of cycles each access was blocked
939 system.cpu.dcache.avg_blocked_cycles::no_targets 131.841759 # average number of cycles each access was blocked
940 system.cpu.dcache.fast_writes 0 # number of fast writes performed
941 system.cpu.dcache.cache_copies 0 # number of cache copies performed
942 system.cpu.dcache.writebacks::writebacks 3724768 # number of writebacks
943 system.cpu.dcache.writebacks::total 3724768 # number of writebacks
944 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097367 # number of ReadReq MSHR hits
945 system.cpu.dcache.ReadReq_mshr_hits::total 4097367 # number of ReadReq MSHR hits
946 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307364 # number of WriteReq MSHR hits
947 system.cpu.dcache.WriteReq_mshr_hits::total 3307364 # number of WriteReq MSHR hits
948 system.cpu.dcache.demand_mshr_hits::cpu.data 7404731 # number of demand (read+write) MSHR hits
949 system.cpu.dcache.demand_mshr_hits::total 7404731 # number of demand (read+write) MSHR hits
950 system.cpu.dcache.overall_mshr_hits::cpu.data 7404731 # number of overall MSHR hits
951 system.cpu.dcache.overall_mshr_hits::total 7404731 # number of overall MSHR hits
952 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296723 # number of ReadReq MSHR misses
953 system.cpu.dcache.ReadReq_mshr_misses::total 7296723 # number of ReadReq MSHR misses
954 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses
955 system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses
956 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
957 system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
958 system.cpu.dcache.demand_mshr_misses::cpu.data 9180278 # number of demand (read+write) MSHR misses
959 system.cpu.dcache.demand_mshr_misses::total 9180278 # number of demand (read+write) MSHR misses
960 system.cpu.dcache.overall_mshr_misses::cpu.data 9180278 # number of overall MSHR misses
961 system.cpu.dcache.overall_mshr_misses::total 9180278 # number of overall MSHR misses
962 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751 # number of ReadReq MSHR miss cycles
963 system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751 # number of ReadReq MSHR miss cycles
964 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78582140948 # number of WriteReq MSHR miss cycles
965 system.cpu.dcache.WriteReq_mshr_miss_latency::total 78582140948 # number of WriteReq MSHR miss cycles
966 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199500 # number of LoadLockedReq MSHR miss cycles
967 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199500 # number of LoadLockedReq MSHR miss cycles
968 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699 # number of demand (read+write) MSHR miss cycles
969 system.cpu.dcache.demand_mshr_miss_latency::total 247685422699 # number of demand (read+write) MSHR miss cycles
970 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699 # number of overall MSHR miss cycles
971 system.cpu.dcache.overall_mshr_miss_latency::total 247685422699 # number of overall MSHR miss cycles
972 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses
973 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses
974 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
975 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
976 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
977 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
978 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses
979 system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses
980 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses
981 system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses
982 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576 # average ReadReq mshr miss latency
983 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576 # average ReadReq mshr miss latency
984 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171 # average WriteReq mshr miss latency
985 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171 # average WriteReq mshr miss latency
986 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 199500 # average LoadLockedReq mshr miss latency
987 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 199500 # average LoadLockedReq mshr miss latency
988 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency
989 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency
990 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency
991 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency
992 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
994 ---------- End Simulation Statistics ----------
projects / gem5.git / blob