2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.150356 # Number of seconds simulated
4 sim_ticks 1150356296500 # Number of ticks simulated
5 final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 374766 # Simulator instruction rate (inst/s)
8 host_op_rate 403753 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 279117141 # Simulator tick rate (ticks/s)
10 host_mem_usage 273688 # Number of bytes of host memory used
11 host_seconds 4121.41 # Real time elapsed on the host
12 sim_insts 1544563088 # Number of instructions simulated
13 sim_ops 1664032481 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory
24 system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory
26 system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory
27 system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory
28 system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory
29 system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s)
30 system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s)
31 system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s)
32 system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s)
33 system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s)
34 system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s)
35 system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s)
36 system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s)
37 system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s)
38 system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s)
39 system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s)
40 system.physmem.readReqs 2064812 # Number of read requests accepted
41 system.physmem.writeReqs 1060173 # Number of write requests accepted
42 system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue
43 system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue
44 system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM
45 system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue
46 system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM
47 system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side
48 system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side
49 system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue
50 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
51 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
52 system.physmem.perBankRdBursts::0 128530 # Per bank write bursts
53 system.physmem.perBankRdBursts::1 125798 # Per bank write bursts
54 system.physmem.perBankRdBursts::2 122667 # Per bank write bursts
55 system.physmem.perBankRdBursts::3 124564 # Per bank write bursts
56 system.physmem.perBankRdBursts::4 123583 # Per bank write bursts
57 system.physmem.perBankRdBursts::5 123689 # Per bank write bursts
58 system.physmem.perBankRdBursts::6 124368 # Per bank write bursts
59 system.physmem.perBankRdBursts::7 124965 # Per bank write bursts
60 system.physmem.perBankRdBursts::8 132503 # Per bank write bursts
61 system.physmem.perBankRdBursts::9 134776 # Per bank write bursts
62 system.physmem.perBankRdBursts::10 133237 # Per bank write bursts
63 system.physmem.perBankRdBursts::11 134508 # Per bank write bursts
64 system.physmem.perBankRdBursts::12 134521 # Per bank write bursts
65 system.physmem.perBankRdBursts::13 134606 # Per bank write bursts
66 system.physmem.perBankRdBursts::14 130538 # Per bank write bursts
67 system.physmem.perBankRdBursts::15 130654 # Per bank write bursts
68 system.physmem.perBankWrBursts::0 66782 # Per bank write bursts
69 system.physmem.perBankWrBursts::1 64941 # Per bank write bursts
70 system.physmem.perBankWrBursts::2 63176 # Per bank write bursts
71 system.physmem.perBankWrBursts::3 63581 # Per bank write bursts
72 system.physmem.perBankWrBursts::4 63564 # Per bank write bursts
73 system.physmem.perBankWrBursts::5 63647 # Per bank write bursts
74 system.physmem.perBankWrBursts::6 65050 # Per bank write bursts
75 system.physmem.perBankWrBursts::7 66062 # Per bank write bursts
76 system.physmem.perBankWrBursts::8 67977 # Per bank write bursts
77 system.physmem.perBankWrBursts::9 68434 # Per bank write bursts
78 system.physmem.perBankWrBursts::10 68153 # Per bank write bursts
79 system.physmem.perBankWrBursts::11 68587 # Per bank write bursts
80 system.physmem.perBankWrBursts::12 68034 # Per bank write bursts
81 system.physmem.perBankWrBursts::13 68534 # Per bank write bursts
82 system.physmem.perBankWrBursts::14 67158 # Per bank write bursts
83 system.physmem.perBankWrBursts::15 66466 # Per bank write bursts
84 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
85 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
86 system.physmem.totGap 1150356195500 # Total gap between requests
87 system.physmem.readPktSize::0 0 # Read request sizes (log2)
88 system.physmem.readPktSize::1 0 # Read request sizes (log2)
89 system.physmem.readPktSize::2 0 # Read request sizes (log2)
90 system.physmem.readPktSize::3 0 # Read request sizes (log2)
91 system.physmem.readPktSize::4 0 # Read request sizes (log2)
92 system.physmem.readPktSize::5 0 # Read request sizes (log2)
93 system.physmem.readPktSize::6 2064812 # Read request sizes (log2)
94 system.physmem.writePktSize::0 0 # Write request sizes (log2)
95 system.physmem.writePktSize::1 0 # Write request sizes (log2)
96 system.physmem.writePktSize::2 0 # Write request sizes (log2)
97 system.physmem.writePktSize::3 0 # Write request sizes (log2)
98 system.physmem.writePktSize::4 0 # Write request sizes (log2)
99 system.physmem.writePktSize::5 0 # Write request sizes (log2)
100 system.physmem.writePktSize::6 1060173 # Write request sizes (log2)
101 system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
197 system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation
211 system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes
219 system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes
220 system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
221 system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes
222 system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes
226 system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads
237 system.physmem.totQLat 60011294750 # Total ticks spent queuing
238 system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM
239 system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers
240 system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst
241 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
242 system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst
243 system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s
244 system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s
245 system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s
246 system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s
247 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
248 system.physmem.busUtil 1.36 # Data bus utilization in percentage
249 system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads
250 system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes
251 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
252 system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing
253 system.physmem.readRowHits 775182 # Number of row buffer hits during reads
254 system.physmem.writeRowHits 420747 # Number of row buffer hits during writes
255 system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads
256 system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes
257 system.physmem.avgGap 368115.75 # Average gap between requests
258 system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined
259 system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ)
260 system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ)
261 system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ)
262 system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ)
263 system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ)
264 system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ)
265 system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ)
266 system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ)
267 system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ)
268 system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ)
269 system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ)
270 system.physmem_0.averagePower 468.682274 # Core power per rank (mW)
271 system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank
272 system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states
273 system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states
274 system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states
275 system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states
276 system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states
277 system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states
278 system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ)
279 system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ)
280 system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ)
281 system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ)
282 system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ)
283 system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ)
284 system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ)
285 system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ)
286 system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ)
287 system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ)
288 system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ)
289 system.physmem_1.averagePower 469.932679 # Core power per rank (mW)
290 system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank
291 system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states
292 system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states
293 system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states
294 system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states
295 system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states
296 system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states
297 system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
298 system.cpu.branchPred.lookups 240030332 # Number of BP lookups
299 system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted
300 system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect
301 system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups
302 system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits
303 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
304 system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage
305 system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target.
306 system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
307 system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups.
308 system.cpu.branchPred.indirectHits 232 # Number of indirect target hits.
309 system.cpu.branchPred.indirectMisses 306 # Number of indirect misses.
310 system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches.
311 system.cpu_clk_domain.clock 500 # Clock period in ticks
312 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
313 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
314 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
315 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
316 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
317 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
318 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
319 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
320 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
321 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
322 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
323 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
324 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
325 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
326 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
327 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
328 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
329 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
330 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
331 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
332 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
333 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
334 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
335 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
336 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
337 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
338 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
339 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
340 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
341 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
342 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
343 system.cpu.dtb.walker.walks 0 # Table walker walks requested
344 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
345 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
346 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
347 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
348 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
349 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
350 system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
351 system.cpu.dtb.inst_hits 0 # ITB inst hits
352 system.cpu.dtb.inst_misses 0 # ITB inst misses
353 system.cpu.dtb.read_hits 0 # DTB read hits
354 system.cpu.dtb.read_misses 0 # DTB read misses
355 system.cpu.dtb.write_hits 0 # DTB write hits
356 system.cpu.dtb.write_misses 0 # DTB write misses
357 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
358 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
359 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
360 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
361 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
362 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
363 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
364 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
365 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
366 system.cpu.dtb.read_accesses 0 # DTB read accesses
367 system.cpu.dtb.write_accesses 0 # DTB write accesses
368 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
369 system.cpu.dtb.hits 0 # DTB hits
370 system.cpu.dtb.misses 0 # DTB misses
371 system.cpu.dtb.accesses 0 # DTB accesses
372 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
373 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
374 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
375 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
376 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
377 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
378 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
379 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
380 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
381 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
382 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
383 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
384 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
385 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
386 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
387 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
388 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
389 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
390 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
391 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
392 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
393 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
394 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
395 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
396 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
397 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
398 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
399 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
400 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
401 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
402 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
403 system.cpu.itb.walker.walks 0 # Table walker walks requested
404 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
405 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
406 system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
407 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
408 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
409 system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
410 system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
411 system.cpu.itb.inst_hits 0 # ITB inst hits
412 system.cpu.itb.inst_misses 0 # ITB inst misses
413 system.cpu.itb.read_hits 0 # DTB read hits
414 system.cpu.itb.read_misses 0 # DTB read misses
415 system.cpu.itb.write_hits 0 # DTB write hits
416 system.cpu.itb.write_misses 0 # DTB write misses
417 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
418 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
419 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
420 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
421 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
422 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
423 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
424 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
425 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
426 system.cpu.itb.read_accesses 0 # DTB read accesses
427 system.cpu.itb.write_accesses 0 # DTB write accesses
428 system.cpu.itb.inst_accesses 0 # ITB inst accesses
429 system.cpu.itb.hits 0 # DTB hits
430 system.cpu.itb.misses 0 # DTB misses
431 system.cpu.itb.accesses 0 # DTB accesses
432 system.cpu.workload.numSyscalls 46 # Number of system calls
433 system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states
434 system.cpu.numCycles 2300712593 # number of cpu cycles simulated
435 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
436 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
437 system.cpu.committedInsts 1544563088 # Number of instructions committed
438 system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
439 system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit
440 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
441 system.cpu.cpi 1.489556 # CPI: cycles per instruction
442 system.cpu.ipc 0.671341 # IPC: instructions per cycle
443 system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
444 system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction
445 system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
446 system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
447 system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
448 system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
449 system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
450 system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
451 system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction
452 system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
453 system.cpu.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction
454 system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
455 system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
456 system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
457 system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
458 system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
459 system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
460 system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
461 system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
462 system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
463 system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
464 system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
465 system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
466 system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
467 system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
468 system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
469 system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
470 system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
471 system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
472 system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
473 system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
474 system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
475 system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction
476 system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction
477 system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction
478 system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction
479 system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
480 system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
481 system.cpu.op_class_0::total 1664032481 # Class of committed instruction
482 system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked
483 system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped
484 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
485 system.cpu.dcache.tags.replacements 9220185 # number of replacements
486 system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use
487 system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks.
488 system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks.
489 system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks.
490 system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit.
491 system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor
492 system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy
493 system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy
494 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
495 system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
496 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id
497 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
498 system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id
499 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
500 system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses
501 system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses
502 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
503 system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits
504 system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits
505 system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits
506 system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits
507 system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
508 system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
509 system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
510 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
511 system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
512 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
513 system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits
514 system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits
515 system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits
516 system.cpu.dcache.overall_hits::total 624504140 # number of overall hits
517 system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses
518 system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses
519 system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses
520 system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses
521 system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
522 system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
523 system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses
524 system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses
525 system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses
526 system.cpu.dcache.overall_misses::total 9590358 # number of overall misses
527 system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles
528 system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles
529 system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles
530 system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles
531 system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles
532 system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles
533 system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles
534 system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles
535 system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses)
536 system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses)
537 system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
538 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
539 system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
540 system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
541 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
542 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
543 system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
544 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
545 system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses
546 system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses
547 system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses
548 system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses
549 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses
550 system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses
551 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses
552 system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses
553 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
554 system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
555 system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses
556 system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses
557 system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses
558 system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses
559 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency
560 system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency
561 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency
562 system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency
563 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency
564 system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency
565 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency
566 system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency
567 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
568 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
569 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
570 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
571 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
572 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
573 system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks
574 system.cpu.dcache.writebacks::total 3670078 # number of writebacks
575 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
576 system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
577 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits
578 system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits
579 system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits
580 system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits
581 system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits
582 system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits
583 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses
584 system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses
585 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses
586 system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses
587 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
588 system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
589 system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses
590 system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses
591 system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses
592 system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses
593 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles
594 system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles
595 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles
596 system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles
597 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles
598 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles
599 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles
600 system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles
601 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles
602 system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles
603 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses
604 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses
605 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
606 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
607 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
608 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
609 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses
610 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses
611 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses
612 system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses
613 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency
614 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency
615 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency
616 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency
617 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency
618 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency
619 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency
620 system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency
621 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency
622 system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency
623 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
624 system.cpu.icache.tags.replacements 33 # number of replacements
625 system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use
626 system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks.
627 system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks.
628 system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks.
629 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
630 system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor
631 system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy
632 system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy
633 system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id
634 system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
635 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
636 system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id
637 system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id
638 system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses
639 system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses
640 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
641 system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits
642 system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits
643 system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits
644 system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits
645 system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits
646 system.cpu.icache.overall_hits::total 466324528 # number of overall hits
647 system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses
648 system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses
649 system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses
650 system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses
651 system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses
652 system.cpu.icache.overall_misses::total 822 # number of overall misses
653 system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles
654 system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles
655 system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles
656 system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles
657 system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles
658 system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles
659 system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses)
660 system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses)
661 system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses
662 system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses
663 system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses
664 system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses
665 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
666 system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
667 system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
668 system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
669 system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
670 system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
671 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency
672 system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency
673 system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency
674 system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency
675 system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency
676 system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency
677 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
678 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
679 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
680 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
681 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
682 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
683 system.cpu.icache.writebacks::writebacks 33 # number of writebacks
684 system.cpu.icache.writebacks::total 33 # number of writebacks
685 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses
686 system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses
687 system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses
688 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses
689 system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses
690 system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses
691 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles
692 system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles
693 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles
694 system.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles
695 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles
696 system.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles
697 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
698 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
699 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
700 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
701 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
702 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
703 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127 # average ReadReq mshr miss latency
704 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127 # average ReadReq mshr miss latency
705 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency
706 system.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency
707 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency
708 system.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency
709 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
710 system.cpu.l2cache.tags.replacements 2032379 # number of replacements
711 system.cpu.l2cache.tags.tagsinuse 31895.934748 # Cycle average of tags in use
712 system.cpu.l2cache.tags.total_refs 16378358 # Total number of references to valid blocks.
713 system.cpu.l2cache.tags.sampled_refs 2065147 # Sample count of references to valid blocks.
714 system.cpu.l2cache.tags.avg_refs 7.930844 # Average number of references to valid blocks.
715 system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit.
716 system.cpu.l2cache.tags.occ_blocks::writebacks 10.372068 # Average occupied blocks per requestor
717 system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.532774 # Average occupied blocks per requestor
718 system.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906 # Average occupied blocks per requestor
719 system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy
720 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy
721 system.cpu.l2cache.tags.occ_percent::cpu.data 0.972291 # Average percentage of cache occupancy
722 system.cpu.l2cache.tags.occ_percent::total 0.973387 # Average percentage of cache occupancy
723 system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
724 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
725 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id
726 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id
727 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id
728 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id
729 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
730 system.cpu.l2cache.tags.tag_accesses 149614963 # Number of tag accesses
731 system.cpu.l2cache.tags.data_accesses 149614963 # Number of data accesses
732 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
733 system.cpu.l2cache.WritebackDirty_hits::writebacks 3670078 # number of WritebackDirty hits
734 system.cpu.l2cache.WritebackDirty_hits::total 3670078 # number of WritebackDirty hits
735 system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
736 system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
737 system.cpu.l2cache.ReadExReq_hits::cpu.data 1078495 # number of ReadExReq hits
738 system.cpu.l2cache.ReadExReq_hits::total 1078495 # number of ReadExReq hits
739 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits
740 system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits
741 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081752 # number of ReadSharedReq hits
742 system.cpu.l2cache.ReadSharedReq_hits::total 6081752 # number of ReadSharedReq hits
743 system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits
744 system.cpu.l2cache.demand_hits::cpu.data 7160247 # number of demand (read+write) hits
745 system.cpu.l2cache.demand_hits::total 7160284 # number of demand (read+write) hits
746 system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits
747 system.cpu.l2cache.overall_hits::cpu.data 7160247 # number of overall hits
748 system.cpu.l2cache.overall_hits::total 7160284 # number of overall hits
749 system.cpu.l2cache.ReadExReq_misses::cpu.data 812338 # number of ReadExReq misses
750 system.cpu.l2cache.ReadExReq_misses::total 812338 # number of ReadExReq misses
751 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses
752 system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses
753 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251696 # number of ReadSharedReq misses
754 system.cpu.l2cache.ReadSharedReq_misses::total 1251696 # number of ReadSharedReq misses
755 system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses
756 system.cpu.l2cache.demand_misses::cpu.data 2064034 # number of demand (read+write) misses
757 system.cpu.l2cache.demand_misses::total 2064819 # number of demand (read+write) misses
758 system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses
759 system.cpu.l2cache.overall_misses::cpu.data 2064034 # number of overall misses
760 system.cpu.l2cache.overall_misses::total 2064819 # number of overall misses
761 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78265681500 # number of ReadExReq miss cycles
762 system.cpu.l2cache.ReadExReq_miss_latency::total 78265681500 # number of ReadExReq miss cycles
763 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72863000 # number of ReadCleanReq miss cycles
764 system.cpu.l2cache.ReadCleanReq_miss_latency::total 72863000 # number of ReadCleanReq miss cycles
765 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 126082122000 # number of ReadSharedReq miss cycles
766 system.cpu.l2cache.ReadSharedReq_miss_latency::total 126082122000 # number of ReadSharedReq miss cycles
767 system.cpu.l2cache.demand_miss_latency::cpu.inst 72863000 # number of demand (read+write) miss cycles
768 system.cpu.l2cache.demand_miss_latency::cpu.data 204347803500 # number of demand (read+write) miss cycles
769 system.cpu.l2cache.demand_miss_latency::total 204420666500 # number of demand (read+write) miss cycles
770 system.cpu.l2cache.overall_miss_latency::cpu.inst 72863000 # number of overall miss cycles
771 system.cpu.l2cache.overall_miss_latency::cpu.data 204347803500 # number of overall miss cycles
772 system.cpu.l2cache.overall_miss_latency::total 204420666500 # number of overall miss cycles
773 system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670078 # number of WritebackDirty accesses(hits+misses)
774 system.cpu.l2cache.WritebackDirty_accesses::total 3670078 # number of WritebackDirty accesses(hits+misses)
775 system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
776 system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
777 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890833 # number of ReadExReq accesses(hits+misses)
778 system.cpu.l2cache.ReadExReq_accesses::total 1890833 # number of ReadExReq accesses(hits+misses)
779 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses)
780 system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses)
781 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333448 # number of ReadSharedReq accesses(hits+misses)
782 system.cpu.l2cache.ReadSharedReq_accesses::total 7333448 # number of ReadSharedReq accesses(hits+misses)
783 system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses
784 system.cpu.l2cache.demand_accesses::cpu.data 9224281 # number of demand (read+write) accesses
785 system.cpu.l2cache.demand_accesses::total 9225103 # number of demand (read+write) accesses
786 system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses
787 system.cpu.l2cache.overall_accesses::cpu.data 9224281 # number of overall (read+write) accesses
788 system.cpu.l2cache.overall_accesses::total 9225103 # number of overall (read+write) accesses
789 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429619 # miss rate for ReadExReq accesses
790 system.cpu.l2cache.ReadExReq_miss_rate::total 0.429619 # miss rate for ReadExReq accesses
791 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses
792 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses
793 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170683 # miss rate for ReadSharedReq accesses
794 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170683 # miss rate for ReadSharedReq accesses
795 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses
796 system.cpu.l2cache.demand_miss_rate::cpu.data 0.223761 # miss rate for demand accesses
797 system.cpu.l2cache.demand_miss_rate::total 0.223826 # miss rate for demand accesses
798 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses
799 system.cpu.l2cache.overall_miss_rate::cpu.data 0.223761 # miss rate for overall accesses
800 system.cpu.l2cache.overall_miss_rate::total 0.223826 # miss rate for overall accesses
801 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96346.202566 # average ReadExReq miss latency
802 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96346.202566 # average ReadExReq miss latency
803 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92819.108280 # average ReadCleanReq miss latency
804 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92819.108280 # average ReadCleanReq miss latency
805 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100729.028454 # average ReadSharedReq miss latency
806 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100729.028454 # average ReadSharedReq miss latency
807 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency
808 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency
809 system.cpu.l2cache.demand_avg_miss_latency::total 99001.736472 # average overall miss latency
810 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency
811 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency
812 system.cpu.l2cache.overall_avg_miss_latency::total 99001.736472 # average overall miss latency
813 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
816 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
817 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819 system.cpu.l2cache.writebacks::writebacks 1060173 # number of writebacks
820 system.cpu.l2cache.writebacks::total 1060173 # number of writebacks
821 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 7 # number of ReadSharedReq MSHR hits
822 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits
823 system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
824 system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
825 system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
826 system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
827 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses
828 system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses
829 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812338 # number of ReadExReq MSHR misses
830 system.cpu.l2cache.ReadExReq_mshr_misses::total 812338 # number of ReadExReq MSHR misses
831 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses
832 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses
833 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251689 # number of ReadSharedReq MSHR misses
834 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251689 # number of ReadSharedReq MSHR misses
835 system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses
836 system.cpu.l2cache.demand_mshr_misses::cpu.data 2064027 # number of demand (read+write) MSHR misses
837 system.cpu.l2cache.demand_mshr_misses::total 2064812 # number of demand (read+write) MSHR misses
838 system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses
839 system.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses
840 system.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses
841 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles
842 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles
843 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles
844 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles
845 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles
846 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles
847 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles
848 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles
849 system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles
850 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles
851 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles
852 system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles
853 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
854 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
855 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses
856 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses
857 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses
858 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses
859 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses
860 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses
861 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses
862 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses
863 system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses
864 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses
865 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses
866 system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses
867 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency
868 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency
869 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency
870 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency
871 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency
872 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency
873 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency
874 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency
875 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency
876 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency
877 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency
878 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency
879 system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter.
880 system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data.
881 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
882 system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter.
883 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
884 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
885 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
886 system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution
887 system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution
888 system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution
889 system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution
890 system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution
891 system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution
892 system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution
893 system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution
894 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes)
895 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes)
896 system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes)
897 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes)
898 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes)
899 system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes)
900 system.cpu.toL2Bus.snoops 2032379 # Total snoops (count)
901 system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes)
902 system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram
903 system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram
904 system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram
905 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
906 system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram
907 system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram
908 system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
909 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
910 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
911 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
912 system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram
913 system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks)
914 system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
915 system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks)
916 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
917 system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks)
918 system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
919 system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter.
920 system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data.
921 system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
922 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
923 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
924 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
925 system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states
926 system.membus.trans_dist::ReadResp 1252474 # Transaction distribution
927 system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution
928 system.membus.trans_dist::CleanEvict 970977 # Transaction distribution
929 system.membus.trans_dist::ReadExReq 812338 # Transaction distribution
930 system.membus.trans_dist::ReadExResp 812338 # Transaction distribution
931 system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution
932 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes)
933 system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes)
934 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes)
935 system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes)
936 system.membus.snoops 0 # Total snoops (count)
937 system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
938 system.membus.snoop_fanout::samples 2064812 # Request fanout histogram
939 system.membus.snoop_fanout::mean 0 # Request fanout histogram
940 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
941 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
942 system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram
943 system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
944 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
945 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
946 system.membus.snoop_fanout::max_value 0 # Request fanout histogram
947 system.membus.snoop_fanout::total 2064812 # Request fanout histogram
948 system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks)
949 system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
950 system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks)
951 system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
953 ---------- End Simulation Statistics ----------
projects / gem5.git / blob