2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 1.095875 # Number of seconds simulated
4 sim_ticks 1095875470500 # Number of ticks simulated
5 final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 232088 # Simulator instruction rate (inst/s)
8 host_op_rate 250040 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 164667871 # Simulator tick rate (ticks/s)
10 host_mem_usage 318056 # Number of bytes of host memory used
11 host_seconds 6655.07 # Real time elapsed on the host
12 sim_insts 1544563087 # Number of instructions simulated
13 sim_ops 1664032480 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory
17 system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory
18 system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
19 system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
20 system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory
21 system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory
22 system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory
23 system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory
24 system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory
25 system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory
26 system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s)
27 system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s)
30 system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s)
31 system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s)
32 system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s)
33 system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s)
34 system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s)
35 system.physmem.readReqs 2055298 # Number of read requests accepted
36 system.physmem.writeReqs 1046304 # Number of write requests accepted
37 system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue
38 system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue
39 system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM
40 system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue
41 system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM
42 system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side
43 system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side
44 system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue
45 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47 system.physmem.perBankRdBursts::0 127944 # Per bank write bursts
48 system.physmem.perBankRdBursts::1 125151 # Per bank write bursts
49 system.physmem.perBankRdBursts::2 122313 # Per bank write bursts
50 system.physmem.perBankRdBursts::3 124176 # Per bank write bursts
51 system.physmem.perBankRdBursts::4 123203 # Per bank write bursts
52 system.physmem.perBankRdBursts::5 123365 # Per bank write bursts
53 system.physmem.perBankRdBursts::6 123797 # Per bank write bursts
54 system.physmem.perBankRdBursts::7 124247 # Per bank write bursts
55 system.physmem.perBankRdBursts::8 131879 # Per bank write bursts
56 system.physmem.perBankRdBursts::9 134089 # Per bank write bursts
57 system.physmem.perBankRdBursts::10 132451 # Per bank write bursts
58 system.physmem.perBankRdBursts::11 133680 # Per bank write bursts
59 system.physmem.perBankRdBursts::12 133764 # Per bank write bursts
60 system.physmem.perBankRdBursts::13 133810 # Per bank write bursts
61 system.physmem.perBankRdBursts::14 129795 # Per bank write bursts
62 system.physmem.perBankRdBursts::15 130290 # Per bank write bursts
63 system.physmem.perBankWrBursts::0 65788 # Per bank write bursts
64 system.physmem.perBankWrBursts::1 64108 # Per bank write bursts
65 system.physmem.perBankWrBursts::2 62418 # Per bank write bursts
66 system.physmem.perBankWrBursts::3 62855 # Per bank write bursts
67 system.physmem.perBankWrBursts::4 62808 # Per bank write bursts
68 system.physmem.perBankWrBursts::5 62982 # Per bank write bursts
69 system.physmem.perBankWrBursts::6 64271 # Per bank write bursts
70 system.physmem.perBankWrBursts::7 65268 # Per bank write bursts
71 system.physmem.perBankWrBursts::8 67081 # Per bank write bursts
72 system.physmem.perBankWrBursts::9 67609 # Per bank write bursts
73 system.physmem.perBankWrBursts::10 67274 # Per bank write bursts
74 system.physmem.perBankWrBursts::11 67626 # Per bank write bursts
75 system.physmem.perBankWrBursts::12 67000 # Per bank write bursts
76 system.physmem.perBankWrBursts::13 67431 # Per bank write bursts
77 system.physmem.perBankWrBursts::14 66125 # Per bank write bursts
78 system.physmem.perBankWrBursts::15 65635 # Per bank write bursts
79 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81 system.physmem.totGap 1095875382500 # Total gap between requests
82 system.physmem.readPktSize::0 0 # Read request sizes (log2)
83 system.physmem.readPktSize::1 0 # Read request sizes (log2)
84 system.physmem.readPktSize::2 0 # Read request sizes (log2)
85 system.physmem.readPktSize::3 0 # Read request sizes (log2)
86 system.physmem.readPktSize::4 0 # Read request sizes (log2)
87 system.physmem.readPktSize::5 0 # Read request sizes (log2)
88 system.physmem.readPktSize::6 2055298 # Read request sizes (log2)
89 system.physmem.writePktSize::0 0 # Write request sizes (log2)
90 system.physmem.writePktSize::1 0 # Write request sizes (log2)
91 system.physmem.writePktSize::2 0 # Write request sizes (log2)
92 system.physmem.writePktSize::3 0 # Write request sizes (log2)
93 system.physmem.writePktSize::4 0 # Write request sizes (log2)
94 system.physmem.writePktSize::5 0 # Write request sizes (log2)
95 system.physmem.writePktSize::6 1046304 # Write request sizes (log2)
96 system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see
97 system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see
98 system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
99 system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100 system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
106 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
107 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
128 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
129 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
130 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
131 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
132 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
133 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
134 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
135 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192 system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation
206 system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes
207 system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes
208 system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes
209 system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes
210 system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes
211 system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
212 system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
213 system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
214 system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
215 system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
216 system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
217 system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
218 system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes
219 system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads
220 system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads
221 system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads
222 system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads
223 system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads
224 system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads
225 system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads
226 system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads
227 system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads
228 system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads
232 system.physmem.totQLat 38124649000 # Total ticks spent queuing
233 system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM
234 system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers
235 system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst
236 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
237 system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst
238 system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s
239 system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s
240 system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s
241 system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s
242 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
243 system.physmem.busUtil 1.41 # Data bus utilization in percentage
244 system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads
245 system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes
246 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
247 system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing
248 system.physmem.readRowHits 779774 # Number of row buffer hits during reads
249 system.physmem.writeRowHits 408484 # Number of row buffer hits during writes
250 system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads
251 system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes
252 system.physmem.avgGap 353325.60 # Average gap between requests
253 system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined
254 system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states
255 system.physmem.memoryStateTime::REF 36593440000 # Time in different power states
256 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
257 system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states
258 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
259 system.membus.throughput 181136026 # Throughput (bytes/s)
260 system.membus.trans_dist::ReadReq 1255348 # Transaction distribution
261 system.membus.trans_dist::ReadResp 1255348 # Transaction distribution
262 system.membus.trans_dist::Writeback 1046304 # Transaction distribution
263 system.membus.trans_dist::ReadExReq 799950 # Transaction distribution
264 system.membus.trans_dist::ReadExResp 799950 # Transaction distribution
265 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes)
266 system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes)
267 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes)
268 system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes)
269 system.membus.data_through_bus 198502528 # Total data (bytes)
270 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
271 system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks)
272 system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
273 system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks)
274 system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
275 system.cpu_clk_domain.clock 500 # Clock period in ticks
276 system.cpu.branchPred.lookups 239641872 # Number of BP lookups
277 system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted
278 system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect
279 system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups
280 system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits
281 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
282 system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage
283 system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target.
284 system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
285 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
286 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
287 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
288 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
289 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
290 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
291 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
292 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
293 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
294 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
295 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
296 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
297 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
298 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
299 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
300 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
301 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
302 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
303 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
304 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
305 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
306 system.cpu.dtb.inst_hits 0 # ITB inst hits
307 system.cpu.dtb.inst_misses 0 # ITB inst misses
308 system.cpu.dtb.read_hits 0 # DTB read hits
309 system.cpu.dtb.read_misses 0 # DTB read misses
310 system.cpu.dtb.write_hits 0 # DTB write hits
311 system.cpu.dtb.write_misses 0 # DTB write misses
312 system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
313 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
314 system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
315 system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
316 system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
317 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
318 system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
319 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
320 system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
321 system.cpu.dtb.read_accesses 0 # DTB read accesses
322 system.cpu.dtb.write_accesses 0 # DTB write accesses
323 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
324 system.cpu.dtb.hits 0 # DTB hits
325 system.cpu.dtb.misses 0 # DTB misses
326 system.cpu.dtb.accesses 0 # DTB accesses
327 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
328 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
329 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
330 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
331 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
332 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
333 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
334 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
335 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
336 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
337 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
338 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
339 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
340 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
341 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
342 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
343 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
344 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
345 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
346 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
347 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
348 system.cpu.itb.inst_hits 0 # ITB inst hits
349 system.cpu.itb.inst_misses 0 # ITB inst misses
350 system.cpu.itb.read_hits 0 # DTB read hits
351 system.cpu.itb.read_misses 0 # DTB read misses
352 system.cpu.itb.write_hits 0 # DTB write hits
353 system.cpu.itb.write_misses 0 # DTB write misses
354 system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
355 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
356 system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
357 system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
358 system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
359 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
360 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
361 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
362 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
363 system.cpu.itb.read_accesses 0 # DTB read accesses
364 system.cpu.itb.write_accesses 0 # DTB write accesses
365 system.cpu.itb.inst_accesses 0 # ITB inst accesses
366 system.cpu.itb.hits 0 # DTB hits
367 system.cpu.itb.misses 0 # DTB misses
368 system.cpu.itb.accesses 0 # DTB accesses
369 system.cpu.workload.num_syscalls 46 # Number of system calls
370 system.cpu.numCycles 2191750941 # number of cpu cycles simulated
371 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
372 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
373 system.cpu.committedInsts 1544563087 # Number of instructions committed
374 system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
375 system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit
376 system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
377 system.cpu.cpi 1.419010 # CPI: cycles per instruction
378 system.cpu.ipc 0.704717 # IPC: instructions per cycle
379 system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked
380 system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped
381 system.cpu.icache.tags.replacements 29 # number of replacements
382 system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use
383 system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks.
384 system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
385 system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks.
386 system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
387 system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor
388 system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy
389 system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy
390 system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
391 system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
392 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
393 system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
394 system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
395 system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses
396 system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses
397 system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits
398 system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits
399 system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits
400 system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits
401 system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits
402 system.cpu.icache.overall_hits::total 464847257 # number of overall hits
403 system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
404 system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
405 system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
406 system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
407 system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
408 system.cpu.icache.overall_misses::total 820 # number of overall misses
409 system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles
410 system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles
411 system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles
412 system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles
413 system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles
414 system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles
415 system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses)
416 system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses)
417 system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses
418 system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses
419 system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses
420 system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses
421 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
422 system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
423 system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
424 system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
425 system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
426 system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
427 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency
428 system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency
429 system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
430 system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency
431 system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
432 system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency
433 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
434 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
435 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
436 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
437 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
438 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
439 system.cpu.icache.fast_writes 0 # number of fast writes performed
440 system.cpu.icache.cache_copies 0 # number of cache copies performed
441 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
442 system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
443 system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
444 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
445 system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
446 system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
447 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles
448 system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles
449 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles
450 system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles
451 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles
452 system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles
453 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
454 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
455 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
456 system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
457 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
458 system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
459 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency
460 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency
461 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency
462 system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency
463 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency
464 system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency
465 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
466 system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s)
467 system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution
468 system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution
469 system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution
470 system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution
471 system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution
472 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
473 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes)
474 system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes)
475 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
476 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes)
477 system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes)
478 system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes)
479 system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
480 system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks)
481 system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
482 system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks)
483 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
484 system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks)
485 system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
486 system.cpu.l2cache.tags.replacements 2022594 # number of replacements
487 system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use
488 system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks.
489 system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks.
490 system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks.
491 system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit.
492 system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor
493 system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor
494 system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy
495 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy
496 system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy
497 system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
498 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
499 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
500 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
501 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
502 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
503 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
504 system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses
505 system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses
506 system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits
507 system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits
508 system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits
509 system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits
510 system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits
511 system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits
512 system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits
513 system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits
514 system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits
515 system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits
516 system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses
517 system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses
518 system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses
519 system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses
520 system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses
521 system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses
522 system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses
523 system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses
524 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles
525 system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles
526 system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # number of ReadExReq miss cycles
527 system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles
528 system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles
529 system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles
530 system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles
531 system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles
532 system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses)
533 system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses)
534 system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses)
535 system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses)
536 system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses)
537 system.cpu.l2cache.ReadExReq_accesses::total 1890876 # number of ReadExReq accesses(hits+misses)
538 system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses
539 system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses
540 system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses
541 system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses
542 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses
543 system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses
544 system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses
545 system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses
546 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses
547 system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses
548 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses
549 system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses
550 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693 # average ReadReq miss latency
551 system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693 # average ReadReq miss latency
552 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014 # average ReadExReq miss latency
553 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014 # average ReadExReq miss latency
554 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency
555 system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161 # average overall miss latency
556 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency
557 system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161 # average overall miss latency
558 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
559 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
560 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
561 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
562 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
563 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
564 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
565 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
566 system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks
567 system.cpu.l2cache.writebacks::total 1046304 # number of writebacks
568 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
569 system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
570 system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
571 system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
572 system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
573 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
574 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses
575 system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses
576 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses
577 system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses
578 system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses
579 system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses
580 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses
581 system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses
582 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles
583 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles
584 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles
585 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles
586 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles
587 system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles
588 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles
589 system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles
590 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses
591 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses
592 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses
593 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses
594 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses
595 system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses
596 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses
597 system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses
598 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency
599 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency
600 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency
601 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency
602 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency
603 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency
604 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency
605 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency
606 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
607 system.cpu.dcache.tags.replacements 9222351 # number of replacements
608 system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use
609 system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks.
610 system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks.
611 system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks.
612 system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit.
613 system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor
614 system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy
615 system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy
616 system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
617 system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id
618 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id
619 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
620 system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
621 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
622 system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses
623 system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses
624 system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits
625 system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits
626 system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits
627 system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits
628 system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
629 system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
630 system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
631 system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
632 system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits
633 system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits
634 system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits
635 system.cpu.dcache.overall_hits::total 624001136 # number of overall hits
636 system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses
637 system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses
638 system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses
639 system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses
640 system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses
641 system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses
642 system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses
643 system.cpu.dcache.overall_misses::total 9576382 # number of overall misses
644 system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles
645 system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles
646 system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles
647 system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles
648 system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles
649 system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles
650 system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles
651 system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles
652 system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses)
653 system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses)
654 system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
655 system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
656 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
657 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
658 system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
659 system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
660 system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses
661 system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses
662 system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses
663 system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses
664 system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses
665 system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses
666 system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses
667 system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses
668 system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses
669 system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses
670 system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses
671 system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses
672 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency
673 system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency
674 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency
675 system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency
676 system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency
677 system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency
678 system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency
679 system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency
680 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
683 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
684 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686 system.cpu.dcache.fast_writes 0 # number of fast writes performed
687 system.cpu.dcache.cache_copies 0 # number of cache copies performed
688 system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks
689 system.cpu.dcache.writebacks::total 3700895 # number of writebacks
690 system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits
691 system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits
692 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits
693 system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits
694 system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits
695 system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits
696 system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits
697 system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits
698 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses
699 system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses
700 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses
701 system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses
702 system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses
703 system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses
704 system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses
705 system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses
706 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles
707 system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles
708 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles
709 system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles
710 system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles
711 system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles
712 system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles
713 system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles
714 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses
715 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses
716 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
717 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
718 system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses
719 system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses
720 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses
721 system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses
722 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency
723 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency
724 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency
725 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency
726 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency
727 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency
728 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency
729 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency
730 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
732 ---------- End Simulation Statistics ----------
projects / gem5.git / blob